CN113534937A - Single-chip microcomputer electrostatic impact reset detection recovery device and control method - Google Patents
Single-chip microcomputer electrostatic impact reset detection recovery device and control method Download PDFInfo
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- CN113534937A CN113534937A CN202010309313.0A CN202010309313A CN113534937A CN 113534937 A CN113534937 A CN 113534937A CN 202010309313 A CN202010309313 A CN 202010309313A CN 113534937 A CN113534937 A CN 113534937A
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- chip microcomputer
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- 238000001514 detection method Methods 0.000 title claims abstract description 19
- 238000011084 recovery Methods 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 title claims abstract description 12
- 239000003990 capacitor Substances 0.000 claims abstract description 46
- 238000004146 energy storage Methods 0.000 claims abstract description 46
- 230000035939 shock Effects 0.000 claims abstract description 14
- 230000002159 abnormal effect Effects 0.000 claims description 4
- 230000003068 static effect Effects 0.000 abstract description 6
- 238000011161 development Methods 0.000 abstract description 3
- 230000005611 electricity Effects 0.000 abstract description 2
- 238000012360 testing method Methods 0.000 description 6
- 230000006870 function Effects 0.000 description 2
- 238000012356 Product development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0428—Safety, monitoring
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/24—Pc safety
- G05B2219/24032—Power on reset, powering up
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- Engineering & Computer Science (AREA)
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- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Automation & Control Theory (AREA)
- General Engineering & Computer Science (AREA)
- Microcomputers (AREA)
Abstract
The invention relates to a single chip microcomputer electrostatic shock reset detection recovery device and a control method thereof, wherein the single chip microcomputer electrostatic shock reset detection recovery device comprises an energy storage capacitor, a discharge resistor and a memory, wherein one end of the energy storage capacitor is grounded, the other end of the energy storage capacitor is connected with one IO port of the single chip microcomputer, the IO port is used for detecting voltages at two ends of the energy storage capacitor, two ends of the discharge resistor are connected in parallel with two ends of the energy storage capacitor, and the memory is a part inside the single chip microcomputer or an independent element connected with the single chip microcomputer through a data line and used for storing working state data of a product controlled by the single chip microcomputer. Compared with the prior art, the invention has the advantages that: the improved single chip microcomputer electrostatic shock reset detection and recovery device can recover the working state before restarting in time after the single chip microcomputer is restarted by static electricity, and can effectively reduce development time and cost.
Description
Technical Field
The invention relates to a single chip microcomputer electrostatic shock reset detection recovery device and a control method.
Background
The national mandatory standard of household electrical appliances has an electrostatic discharge test requirement, the national standard is GB 4343.1, and the highest test voltage is 15 KV.
However, most control panels of home appliances use a single chip. However, when a lot of single chip chips are subjected to electrostatic testing, the chips are likely to be abnormally reset and restarted, but the function of the product cannot be lost when the electrostatic discharge test is carried out according to the national standard. For example, when a discharge test is performed on a product touch operation area, the touch chip can be reset due to electrostatic interference, and abnormal phenomena such as shutdown of the product can occur during resetting.
In addition, the electrostatic discharge problem is generally characterized by difficult analysis of reasons, difficult rectification, long rectification period and the like. The problems that the cost is increased and the product development period is prolonged are caused by the fact that a chip with stronger static resistance is required to be replaced for solving the problem of static discharge in many times. Therefore, the development of the single chip microcomputer electrostatic shock reset detection recovery device is very necessary.
Disclosure of Invention
The invention aims to solve the primary technical problem of providing a single chip microcomputer electrostatic impact reset detection and recovery device aiming at the prior art, and when the single chip microcomputer is reset under electrostatic impact, the single chip microcomputer can recover the working state before resetting.
The invention further aims to solve the technical problem of providing a control method of the single chip microcomputer electrostatic impact reset detection recovery device.
The technical scheme adopted by the invention for solving the above-mentioned primary technical problems is as follows: the utility model provides a singlechip electrostatic shock detection recovery unit that resets, is connected with the singlechip which characterized in that: including energy storage capacitor, discharge resistor and memory, wherein energy storage capacitor's one end ground connection, energy storage capacitor's the other end and one of them IO mouth of singlechip are connected, and this IO mouth is used for detecting energy storage capacitor both ends voltage, and discharge resistor's both ends parallel connection is at energy storage capacitor's both ends, and the memory is the inside some of singlechip or for passing through the independent component that the data line was connected with the singlechip for the storage is by singlechip control's product operating condition data.
The electrostatic discharge impact is usually tens of nanoseconds, and the reset time of the chip under the electrostatic impact is usually in the microsecond level. Therefore, it is generally required that the discharge time of the energy storage capacitor is not too short. Meanwhile, the normal plugging and unplugging of the product is considered, the discharge time cannot be too long, and otherwise the normal plugging and unplugging is easily judged by mistake. It is recommended to design between 1ms and 10 ms. While the charging time is generally as small as possible.
The working voltage of a common singlechip is 5V, the high level is 3.7V, and the low level is 1.3V; if the discharge resistance is 10K omega, the storage capacitance is approximately between 74nF and 740 nF.
The technical scheme adopted by the invention for solving the further technical problems is as follows: after the single chip microcomputer is reset and started, reading a signal of an IO port connected with the energy storage capacitor, if the signal of the IO port is in a low level, judging that the single chip microcomputer is normally powered on and started, changing the IO port into an output state by the single chip microcomputer at the moment, and outputting a high level to charge the energy storage capacitor; the singlechip stores the working state data of the product into the memory in real time in the normal power-on working process; if the signal of the IO port is in a high level, the single chip microcomputer is judged to be in abnormal impact reset starting, at the moment, the single chip microcomputer reads the latest product working state data from the storage, and the product is restored to the working state before the single chip microcomputer is reset.
After the single chip microcomputer is reset and started, if the read signal of the IO port connected with the energy storage capacitor is at a high level, the single chip microcomputer reads the latest product working state data from the storage, restores the product to the working state before the single chip microcomputer is reset, simultaneously modifies the IO port connected with the energy storage capacitor into an output state again, and outputs the high level to charge the energy storage capacitor.
Compared with the prior art, the invention has the advantages that: the improved single chip microcomputer electrostatic shock reset detection and recovery device can recover the working state before restarting in time after the single chip microcomputer is restarted by static electricity, and can effectively reduce development time and cost.
Drawings
Fig. 1 is a circuit diagram of a single chip microcomputer electrostatic shock reset detection recovery device in the embodiment of the invention.
Fig. 2 is a flow chart of a control method of the single chip microcomputer electrostatic shock reset detection recovery device in the embodiment of the invention.
Detailed Description
The invention is described in further detail below with reference to the accompanying examples.
The single-chip microcomputer electrostatic shock reset detection recovery device shown in fig. 1 is used for being connected with a single-chip microcomputer, and comprises an energy storage capacitor, a discharge resistor and a memory, wherein one end of the energy storage capacitor is grounded, the other end of the energy storage capacitor is connected with one IO port of the single-chip microcomputer, the IO port is a P1 pin, the IO port is used for detecting voltages at two ends of the energy storage capacitor, two ends of the discharge resistor are connected to two ends of the energy storage capacitor in parallel, the memory is an independent element which is connected with the single-chip microcomputer through a data line or is a part inside the single-chip microcomputer, and the memory is used for storing product working state data controlled by the single-chip microcomputer.
The electrostatic discharge impact is usually tens of nanoseconds, and the reset time of the chip under the electrostatic impact is usually in the microsecond level. Therefore, it is generally required that the discharge time of the energy storage capacitor is not too short. Meanwhile, the normal plugging and unplugging of the product is considered, the discharge time cannot be too long, and otherwise the normal plugging and unplugging is easily judged by mistake. It is recommended to design between 1ms and 10 ms. While the charging time is generally as small as possible.
The working voltage of a common singlechip is 5V, the high level is 3.7V, and the low level is 1.3V; if the discharge resistance is 10K omega, the storage capacitance is approximately between 74nF and 740 nF.
If the single chip microcomputer has no electric energy in the circuit under the condition of normal power failure, the voltage at two ends of the energy storage capacitor is 0, and the voltage of an IO port connected with the energy storage capacitor in the single chip microcomputer is 0. The control method of the single-chip microcomputer electrostatic impact reset detection recovery device is described in detail as follows, and is described in reference to fig. 2:
after the singlechip is normally powered on, reset and started, the voltage of an IO port connected with the energy storage capacitor in the singlechip is 0 because the original circuit is not powered; after the single chip microcomputer is started, setting an IO port pin connected with the energy storage capacitor to be in a reading state in a bottom layer initialization stage, reading a signal of the IO port connected with the energy storage capacitor, judging that the single chip microcomputer is normally powered on and started if the signal of the IO port is in a low level, then modifying the IO port into an output state by the single chip microcomputer, and outputting the high level to charge the energy storage capacitor; then entering a product function initialization program, and then entering a standby state;
in the normal power-on process of the single chip microcomputer, because the pin P1 of the single chip microcomputer outputs high level to charge the energy storage capacitor, the single chip microcomputer stores the working state data of the product into the memory in real time;
when the static test is carried out, the single chip microcomputer is reset due to static impact, after the single chip microcomputer is reset and started, the voltage of an IO port connected with the energy storage capacitor is set to be 0 in a bottom layer initialization stage to be in a reading state, then, a signal of the IO port is read immediately, the discharging time of the energy storage capacitor is long, the signal of the IO port connected with the energy storage capacitor is still in a high level at the moment, the IO port is read to be in the high level, the single chip microcomputer is judged to be in abnormal impact reset and started, the latest product working state data are read from the storage, the product is restored to the working state before the single chip microcomputer is reset, meanwhile, the IO port connected with the energy storage capacitor is modified into an output state again by the single chip microcomputer, and the high level is output to charge the energy storage capacitor.
Claims (5)
1. The utility model provides a singlechip electrostatic shock detection recovery unit that resets, is connected with the singlechip which characterized in that: including energy storage capacitor, discharge resistor and memory, wherein energy storage capacitor's one end ground connection, energy storage capacitor's the other end and one of them IO mouth of singlechip are connected, and this IO mouth is used for detecting energy storage capacitor both ends voltage, and discharge resistor's both ends parallel connection is at energy storage capacitor's both ends, and the memory is the inside some of singlechip or for passing through the independent component that the data line was connected with the singlechip for the storage is by singlechip control's product operating condition data.
2. The single-chip microcomputer electrostatic shock reset detection and recovery device according to claim 1, characterized in that: the discharge time of the energy storage capacitor is between 1ms and 10 ms.
3. The single-chip microcomputer electrostatic shock reset detection and recovery device according to claim 1, characterized in that: the resistance value of the discharge resistor is 10K omega, and the capacity of the energy storage capacitor is 74 nF-740 nF.
4. A control method of the single-chip microcomputer electrostatic shock reset detection recovery device as claimed in claim 1, 2 or 3, characterized in that: after the single chip microcomputer is reset and started, reading a signal of an IO port connected with the energy storage capacitor, if the signal of the IO port is in a low level, judging that the single chip microcomputer is normally powered on and started, changing the IO port into an output state by the single chip microcomputer at the moment, and outputting a high level to charge the energy storage capacitor; the singlechip stores the working state data of the product into the memory in real time in the normal power-on working process; if the signal of the IO port is in a high level, the single chip microcomputer is judged to be in abnormal impact reset starting, at the moment, the single chip microcomputer reads the latest product working state data from the storage, and the product is restored to the working state before the single chip microcomputer is reset.
5. The control method according to claim 4, characterized in that: after the single chip microcomputer is reset and started, if the read signal of the IO port connected with the energy storage capacitor is at a high level, the single chip microcomputer reads the latest product working state data from the storage, restores the product to the working state before the single chip microcomputer is reset, simultaneously modifies the IO port connected with the energy storage capacitor into an output state again, and outputs the high level to charge the energy storage capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010309313.0A CN113534937A (en) | 2020-04-20 | 2020-04-20 | Single-chip microcomputer electrostatic impact reset detection recovery device and control method |
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| CN202010309313.0A CN113534937A (en) | 2020-04-20 | 2020-04-20 | Single-chip microcomputer electrostatic impact reset detection recovery device and control method |
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| CN113534937A true CN113534937A (en) | 2021-10-22 |
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| KR20000003195A (en) * | 1998-06-26 | 2000-01-15 | 전주범 | Apparatus and method of compensating present time after interruption of electric power |
| US20090106609A1 (en) * | 2007-10-18 | 2009-04-23 | Fujitsu Microelectronics Limited | Semiconductor integrated circuit and debug mode determination method |
| CN201518478U (en) * | 2009-09-25 | 2010-06-30 | 赣州市英唐电子科技有限公司 | Capacitive touch induction circuit |
| CN103209534A (en) * | 2013-04-02 | 2013-07-17 | 中冶辽宁德龙钢管有限公司 | Anti-static device and method for plasma cutting device |
| CN106847318A (en) * | 2017-01-24 | 2017-06-13 | 上海麦歌恩微电子股份有限公司 | Nonvolatile memory based on electric capacity |
| CN108279760A (en) * | 2018-02-28 | 2018-07-13 | 上海顺久电子科技有限公司 | A kind of power on detection circuit, chip and wearable device |
| CN208673086U (en) * | 2018-07-23 | 2019-03-29 | 福建飞毛腿动力科技有限公司 | A kind of low cost low-power consumption single-chip microcontroller timing wake-up circuit |
| CN110769552A (en) * | 2019-10-31 | 2020-02-07 | 深圳市崧盛电子股份有限公司 | Output short circuit back quick recovery circuit and LED drive power supply |
-
2020
- 2020-04-20 CN CN202010309313.0A patent/CN113534937A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000003195A (en) * | 1998-06-26 | 2000-01-15 | 전주범 | Apparatus and method of compensating present time after interruption of electric power |
| US20090106609A1 (en) * | 2007-10-18 | 2009-04-23 | Fujitsu Microelectronics Limited | Semiconductor integrated circuit and debug mode determination method |
| CN201518478U (en) * | 2009-09-25 | 2010-06-30 | 赣州市英唐电子科技有限公司 | Capacitive touch induction circuit |
| CN103209534A (en) * | 2013-04-02 | 2013-07-17 | 中冶辽宁德龙钢管有限公司 | Anti-static device and method for plasma cutting device |
| CN106847318A (en) * | 2017-01-24 | 2017-06-13 | 上海麦歌恩微电子股份有限公司 | Nonvolatile memory based on electric capacity |
| CN108279760A (en) * | 2018-02-28 | 2018-07-13 | 上海顺久电子科技有限公司 | A kind of power on detection circuit, chip and wearable device |
| CN208673086U (en) * | 2018-07-23 | 2019-03-29 | 福建飞毛腿动力科技有限公司 | A kind of low cost low-power consumption single-chip microcontroller timing wake-up circuit |
| CN110769552A (en) * | 2019-10-31 | 2020-02-07 | 深圳市崧盛电子股份有限公司 | Output short circuit back quick recovery circuit and LED drive power supply |
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