CN113523597B

CN113523597B - Wafer cutting method

Info

Publication number: CN113523597B
Application number: CN202110773446.8A
Authority: CN
Inventors: 田应超
Original assignee: Hubei Sanwei Semiconductor Integrated Manufacturing Innovation Center Co ltd
Current assignee: Hubei Sanwei Semiconductor Integrated Manufacturing Innovation Center Co ltd
Priority date: 2021-07-08
Filing date: 2021-07-08
Publication date: 2022-07-19
Anticipated expiration: 2041-07-08
Also published as: CN113523597A; WO2023279653A1

Abstract

The invention provides a wafer cutting method, which comprises the steps of firstly, adopting a first laser cutting process to groove downwards along the surface of a device wafer to form a first groove with larger transverse width, then etching the surface of the device wafer, removing the particles which are generated when the first groove is formed and are attached to the surface of the device wafer, then flattening the surface of the device wafer to ensure the cleanliness and the flatness of the surface of the device wafer, then adopting a second laser cutting process to groove downwards along the bottom surface of the first groove to form a second groove which is communicated with the first groove and has smaller transverse width, the particles generated by the second laser cutting process can be only accumulated in the first groove and the second groove, the cleanliness and the flatness of the surface of the device wafer can not be influenced, the cleanliness and the flatness of the surface of a single chip generated after cutting are ensured, and the bonding effect of the hybrid bonding process can be improved.

Description

Wafer cutting method

Technical Field

The invention relates to the technical field of semiconductors, in particular to a wafer cutting method.

Background

With the semiconductor technology entering the post-molarity, chip structures are developing towards three dimensions in order to meet the requirements of high integration and high performance. The bonding technology is one of important technologies of the supermolecule law, and can be used for carrying out high-density interconnection on chips in different process node processes, so that system-level integration with smaller size, higher performance and lower power consumption is realized. The conventional bonding methods generally include wafer-to-wafer bonding (W2W), chip-to-chip bonding (C2C), and chip-to-wafer bonding (C2W). C2W is favored by global semiconductor macros because it can reject bad chips and yield is high.

The C2W can be realized by a simple metal bonding process or a hybrid bonding process with higher bonding strength, and the hybrid bonding technology has higher I/O connection density and better heat dissipation performance, so that the hybrid bonding technology is widely applied, and has extremely high requirements on the cleanliness and the flatness of the surface of a chip.

The current method for cutting a wafer mainly comprises: the cutting method of the knife flywheel is large in destructiveness, so that a dielectric layer in a wafer is easily cracked to generate jumping or layering, the performance of a chip is affected, the transverse width of a cutting path formed by the knife flywheel is large, the chip is not beneficial to micro shrinkage, and the cleanliness and the flatness of the surface of the chip are affected by particles generated by cutting; the transverse width of a cutting channel formed in a laser cutting mode is small, but the thermal remelting phenomenon of materials can be caused, and even if protective glue is covered on the surface of a wafer, slag serving as particles can be accumulated around a notch; the plasma cutting mode has a narrow application range, the selection difficulty of an etchant is high, and byproducts generated by etching can be attached to the surface of a chip. Therefore, the existing wafer cutting methods are good and bad, but the cleanliness and the flatness of the chip surface cannot be guaranteed, and the hybrid bonding effect is poor.

Disclosure of Invention

The invention aims to provide a wafer cutting method which can ensure the cleanliness of the surface of a chip and improve the bonding effect.

In order to achieve the above object, the present invention provides a wafer dicing method, comprising:

providing a device wafer for hybrid bonding;

adopting a first laser cutting process to groove downwards along the surface of the device wafer to form a first groove extending from the surface of the device wafer into the device wafer;

etching to remove particles on the surface of the device wafer;

planarizing the surface of the device wafer; and the number of the first and second groups,

and adopting a second laser cutting process to groove downwards along the bottom surface of the first groove to form a second groove communicated with the first groove, wherein the transverse width of the first groove is greater than that of the second groove.

Optionally, a line width of the laser of the first laser cutting process is greater than a line width of the laser of the second laser cutting process, so that a lateral width of the first groove is greater than a lateral width of the second groove.

Optionally, the lateral width of the first groove is 10 micrometers to 30 micrometers; and/or the width of the second groove is 8-20 microns.

Optionally, the energy of the laser of the first laser cutting process is less than the energy of the laser of the second laser cutting process, so that the depth of the first groove is less than the depth of the second groove.

Optionally, a wet etching process is used to remove the particles on the surface of the device wafer, and the rate of etching the particles by the wet etching process is greater than the rate of etching the material on the surface of the device wafer.

Optionally, the device wafer includes a substrate, an interconnection structure layer and a hybrid bonding layer, the interconnection structure layer covers the front side of the substrate, the hybrid bonding layer covers the interconnection structure layer, and when a groove is formed downwards along the surface of the device wafer, a groove is formed downwards along the surface of the hybrid bonding layer.

Optionally, the first groove and the second groove at least commonly penetrate through the hybrid bonding layer and the interconnection structure layer.

Optionally, the first groove and the second groove jointly penetrate through the device wafer and form a scribe line.

Optionally, the second groove extends from the bottom surface of the first groove into the substrate, and after the second groove is formed, the method further includes:

and a groove is formed downwards along the bottom surface of the second groove to form a third groove communicated with the second groove, and the first groove, the second groove and the third groove commonly penetrate through the device wafer to form a cutting channel.

Optionally, the device wafer includes a substrate, an interconnection structure layer and a hybrid bonding layer, the interconnection structure layer covers the front side of the substrate, the hybrid bonding layer covers the back side of the substrate, a through fourth groove is formed in the interconnection structure layer, and when a groove is formed downwards along the surface of the device wafer, a groove is formed downwards along the surface of the hybrid bonding layer.

Optionally, the first groove and the second groove at least jointly penetrate through the hybrid bonding layer.

Optionally, the first groove and the second groove penetrate through the hybrid bonding layer and the substrate and are communicated with the fourth groove, and the first groove, the second groove and the fourth groove penetrate through the device wafer together and form a scribe line.

and a groove is formed downwards along the bottom surface of the second groove to form a third groove communicated with the second groove and the fourth groove, and the first groove, the second groove, the third groove and the fourth groove jointly penetrate through the device wafer to form a cutting channel.

Optionally, the third groove is formed by a plasma etching process or a cutter wheel cutting process.

In the wafer cutting method provided by the invention, firstly, a groove is formed downwards along the surface of a device wafer by adopting a first laser cutting process to form a first groove with larger transverse width, then the surface of the device wafer is etched, particles which are generated when the first groove is formed and are attached to the surface of the device wafer are removed, then the surface of the device wafer is flattened to ensure the cleanliness and the flatness of the surface of the device wafer, then a groove is formed downwards along the bottom surface of the first groove by adopting a second laser cutting process to form a second groove which is communicated with the first groove and has smaller transverse width, at the moment, the particles generated by the second laser cutting process are only accumulated in the first groove and the second groove, the cleanliness and the flatness of the surface of the device wafer are not influenced, and the cleanliness and the flatness of the surface of a single chip generated after cutting are ensured, the bonding effect of the hybrid bonding process can be improved.

Drawings

Fig. 1 is a flowchart of a wafer dicing method according to an embodiment of the invention;

fig. 2a to fig. 2f are schematic structural diagrams corresponding to respective steps of a wafer dicing method according to an embodiment of the invention;

FIG. 3 is a schematic diagram of a scribe line according to a second embodiment of the present invention;

fig. 4a is a schematic view of a device wafer according to a third embodiment of the present invention;

FIG. 4b is a schematic diagram of a scribe line according to a third embodiment of the present invention;

FIG. 5 is a schematic diagram of a scribe line according to a fourth embodiment of the present invention;

wherein the reference numerals are:

100-a substrate; 100 a-the front side of the substrate; 100 b-the back side of the substrate; 110-an interconnect structure layer; 111-a dielectric layer; 112-an interconnect structure; 120-hybrid bonding layer; 121-an insulating bonding layer; 122-conductive bond pads; 200-cutting a street; 200-cutting a street; 201-a first groove; 202-a second groove; 203-a third groove; 204-a fourth groove;

h1 — lateral width of first groove; h2 — the lateral width of the second groove.

Detailed Description

The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Example one

Fig. 1 is a flowchart of a wafer dicing method according to this embodiment. As shown in fig. 1, the wafer dicing method includes:

step S100: providing a device wafer for hybrid bonding;

step S200: adopting a first laser cutting process to groove downwards along the surface of the device wafer to form a first groove extending from the surface of the device wafer to the inside of the device wafer;

step S300: etching to remove particles on the surface of the device wafer;

step S400: planarizing the surface of the device wafer; and the number of the first and second groups,

step S500: and adopting a second laser cutting process to groove downwards along the bottom surface of the first groove to form a second groove communicated with the first groove, wherein the transverse width of the first groove is greater than that of the second groove.

Fig. 2a to fig. 2f are schematic structural diagrams corresponding to respective steps of the wafer dicing method provided in this embodiment. Next, the wafer dicing method provided in this embodiment will be described in detail with reference to fig. 2a to 2 f.

Referring to fig. 2a, step S100 is executed to provide the device wafer, which is a device wafer for face-to-face hybrid bonding in this embodiment. The device wafer comprises a substrate 100, an interconnection structure layer 110 and a hybrid bonding layer 120, wherein the substrate 100 is provided with a front surface 100a and a back surface 100b, the interconnection structure layer 110 covers the front surface 100a of the substrate 100, and the hybrid bonding layer 120 covers the interconnection structure layer 110, so that the substrate 100, the interconnection structure layer 110 and the hybrid bonding layer 120 are sequentially stacked from bottom to top.

The substrate 100 has a device structure formed therein, which may be a MOS device, a sensing device, a memory device, and/or other passive devices.

The interconnection structure layer 110 includes a dielectric layer 111 and an interconnection structure 112 formed in the dielectric layer 111, and the interconnection structure 112 is interconnected with the device structure; the dielectric layer 111 may be a single-layer or multi-layer structure, the interconnection structure 112 may be one or more metal layers (schematically, a layer is used to replace the layer in fig. 2 a), and the different metal layers may be interconnected by electrical connectors such as contact plugs, interconnection layers and/or vias.

The hybrid bonding layer 120 includes an insulating bonding layer 121 and conductive bonding pads 122, the conductive bonding pads 122 being located in the insulating bonding layer 121 and interconnected with the interconnect structure. Typically, the conductive bonding pads 122 are formed on the interconnect structure and are respectively interconnected with the top metal layer of the interconnect structure to achieve electrical extraction of the interconnect structure.

Optionally, the dielectric layer 111 and the insulating bonding layer 121 may be made of a dielectric material or a low-K dielectric material, such as Silicon oxide, Silicon nitride, Silicon oxynitride, NDC (Nitrogen doped Silicon Carbide), or a combination thereof, the interconnect structure 112 may be made of a metal material, such as tungsten, aluminum, copper, or a combination thereof, and the conductive bonding pad 122 may be made of a bonding metal material, such as copper, gold, or a combination thereof.

Referring to fig. 2b, step S200 is performed, a groove is formed along the surface of the device wafer by a first laser cutting process, and a first groove 201 extending from the surface of the device wafer into the device wafer is formed. In this embodiment, the first groove 201 is located in the hybrid bonding layer 120, that is, the depth of the first groove 201 is smaller than the thickness of the hybrid bonding layer 120, so that the first groove 201 does not penetrate through the hybrid bonding layer 120.

Optionally, the lateral width h1 of the first groove 201 is 10 microns to 30 microns.

Further, the first recess 201 is not limited to be located in the hybrid bonding layer 120, the first recess 201 may also extend through the hybrid bonding layer 120 and into the interconnect structure layer 110, and the first recess 201 may even extend through the hybrid bonding layer 120 and the interconnect structure layer 110 and into the substrate 100, which is not limited by the present invention.

It should be understood that when the first groove 201 is formed by the first laser cutting process, the first laser cutting process is prone to cause a hot remelting phenomenon of the material, so that particles made of slag are accumulated on the inner wall of the first groove 201 and on the surface of the hybrid bonding layer 120, which affects the cleanliness and flatness of the surface of the hybrid bonding layer 120, and the particles are generally viscous and difficult to remove.

Referring to fig. 2c, step S300 is performed to etch and remove particles on the surface of the device wafer. Specifically, a wet etching process is used to etch the surface of the hybrid bonding layer 120, so as to remove the particles.

In this embodiment, the rate of etching the particles by the wet etching process is greater than the rate of etching the materials (the insulating bonding layer 121 and the conductive bonding pad 122) on the surface of the device wafer, and preferably, an etchant having a large etching selectivity ratio to the materials on the surface of the device wafer may be used to etch the particles, so as to prevent the materials on the surface of the device wafer from being damaged when the particles are etched.

It should be understood that the wet etching process may etch the surface of the hybrid bonding layer 120 while removing the particles, resulting in a reduced flatness of the surface of the hybrid bonding layer 120.

Referring to fig. 2d, step S400 is performed to planarize the surface of the device wafer. Specifically, the surface of the hybrid bonding layer 120 is planarized using, for example, a chemical mechanical polishing process, thereby improving the flatness of the surface of the hybrid bonding layer 120.

Of course, when the surface of the hybrid bonding layer 120 is planarized, the thickness of the hybrid bonding layer 120 is also reduced, but this does not affect the implementation of the present invention.

Referring to fig. 2e, step S500 is executed to form a groove along the bottom surface of the first groove 201 by a second laser cutting process, so as to form a second groove 202 communicating with the first groove 201. In this embodiment, the second groove 202 extends from the bottom of the first groove 201 into the substrate 100, but does not penetrate through the substrate 100.

Referring to fig. 2d and 2e, the line width of the laser of the first laser cutting process is greater than the line width of the laser of the second laser cutting process, so that the lateral width h1 of the first groove 201 is greater than the lateral width h2 of the second groove 202. Alternatively, the lateral width h2 of the second groove 202 may be 8-20 microns.

It should be understood that when the second groove 202 is formed by the second laser cutting process, similarly, the second laser cutting process also easily causes hot remelting phenomenon of the material, so as to generate particles, but since the lateral width of the second groove 202 is smaller than that of the first groove 201, the particles generated by the second laser cutting process can only be accumulated in the first groove 201 and the second groove 202, and the cleanliness and flatness of the surface of the hybrid bonding layer 120 are not affected.

Further, the energy of the laser of the first laser cutting process is smaller than the energy of the laser of the second laser cutting process, so that the depth of the first groove 201 is smaller than the depth of the second groove 202, thereby reducing particles formed by the first laser cutting process and reducing the difficulty of the wet etching process, but not limited thereto. As an alternative embodiment, the energy of the laser of the first laser cutting process may also be greater than or equal to the energy of the laser of the second laser cutting process, so that the depth of the first groove 201 is greater than or equal to the depth of the second groove 202.

Optionally, the second groove 202 is not limited to extend from the bottom of the first groove 201 into the substrate 100, and may just expose the surface of the substrate 100, that is, the first groove 201 and the second groove 202 may just jointly penetrate through the hybrid bonding layer 120 and the interconnect structure layer 110.

Referring to fig. 2f, a groove is formed downwards along the bottom surface of the second groove 202 to form a third groove 203 communicating with the second groove 202, and the first groove 201, the second groove 202, and the third groove 203 commonly penetrate through the device wafer to form a scribe line 200. The streets 200 are distributed across the device wafer to separate the device wafer into individual chips that can then be bonded to a target wafer using a hybrid bonding process. Since the particles generated by the first laser cutting process are removed and the particles generated by the second laser cutting process are only accumulated in the first groove 201 and the second groove 202, the cleanliness and flatness of the surface of a single chip are high, and the bonding effect of the hybrid bonding process can be improved.

Further, since the second groove 202 extends into the substrate 100, when the groove is formed downwards along the bottom surface of the second groove 202 to form the third groove 203, only the substrate 100 at the bottom of the second groove 202 needs to be removed, in this embodiment, the substrate 100 at the bottom of the second groove 202 is etched by using a plasma etching process until the substrate 100 is etched through, so as to form the third groove 203.

It can be understood that, since it is difficult to etch the metal material and the dielectric material by the plasma etching process, when the third groove 203 is formed by the plasma etching process, the first groove 201 and the second groove 202 at least need to jointly penetrate through the hybrid bonding layer 120 and the interconnect structure layer 110.

As an alternative embodiment, for example, a cutter wheel cutting process may be used to form the third groove 203, and in this case, the first groove 201 and the second groove 202 need not to jointly penetrate through the hybrid bonding layer 120 and the interconnect structure layer 110, and are located in the first groove 201 and the second groove 202, which is not limited in this embodiment.

Example two

Fig. 3 is a schematic diagram of a scribe line 200 according to the present embodiment. As shown in fig. 3, the difference from the first embodiment is that in the present embodiment, when the second groove 202 is formed, the second groove 202 penetrates through the hybrid bonding layer 120, the interconnect structure layer 110, and the substrate 100 downward along the bottom of the first groove 201. In this way, the first groove 201 and the second groove 202 jointly penetrate through the device wafer and form the scribe line 200, so that the step of forming the third groove 203 can be omitted, and the process flow is simplified.

EXAMPLE III

Fig. 4a is a schematic diagram of a device wafer provided in this embodiment. As shown in fig. 4a, the difference from the first embodiment is that in this embodiment, the device wafer is a device wafer for performing back-to-back hybrid bonding, the interconnect structure layer 110 covers the front surface 100a of the substrate 100, the hybrid bonding layer 120 covers the back surface 100b of the substrate 100, and the interconnect structure layer 110 has a fourth recess 204 therein.

Optionally, the fourth groove 204 may be prepared before the hybrid bonding layer 120 of the device wafer is formed, so that the preparation of the fourth groove 204 does not adversely affect the cleanliness and flatness of the hybrid bonding layer 120.

Specifically, fig. 4b is a schematic diagram of the scribe line 200 provided in this embodiment. As shown in fig. 4b, the first groove 201 is located in the hybrid bonding layer 120, the second groove 202 extends from the bottom of the first groove 201 into the substrate 100, and the third groove 203 communicates the second groove 202 and the fourth groove 204. The first groove 201, the second groove 202, the third groove 203, and the fourth groove 204 collectively penetrate the device wafer and form the scribe line 200.

It can be understood that, since it is difficult to etch the metal material and the dielectric material by the plasma etching process, when the third groove 203 is formed by the plasma etching process, the first groove 201 and the second groove 202 at least need to jointly penetrate through the hybrid bonding layer 120.

Example four

Fig. 5 is a schematic diagram of the scribe line 200 provided in this embodiment. As shown in fig. 5, the difference from the third embodiment is that, in the present embodiment, when the second groove 202 is formed, the second groove 202 penetrates the hybrid bonding layer 120, the interconnect structure layer 110, and the substrate 100 downward along the bottom of the first groove 201. In this way, the first groove 201, the second groove 202 and the fourth groove 204 commonly penetrate through the device wafer and form the scribe line 200, so that the step of forming the third groove 203 can be omitted, and the process flow is simplified.

In summary, in the wafer dicing method provided in the embodiment of the present invention, a first laser dicing process is first used to form a groove along a surface of a device wafer to form a first groove with a relatively large lateral width, then the surface of the device wafer is etched to remove particles that are generated during forming the first groove and adhere to the surface of the device wafer, then the surface of the device wafer is planarized to ensure cleanliness and flatness of the surface of the device wafer, and then a second laser dicing process is used to form a groove along a bottom surface of the first groove to form a second groove that is communicated with the first groove and has a relatively small lateral width, at this time, the particles generated by the second laser dicing process are only accumulated in the first groove and the second groove, which does not affect the cleanliness and flatness of the surface of the device wafer, and ensures cleanliness and flatness of the surface of a single chip generated after dicing, the bonding effect of the hybrid bonding process can be improved.

It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.

It should be noted that, although the present invention has been described with reference to the preferred embodiments, the above embodiments are not intended to limit the present invention. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.

It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.

It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A method of dicing a wafer, comprising:

providing a device wafer for hybrid bonding;

firstly, etching to remove particles on the surface of the device wafer, and then flattening the surface of the device wafer; and the number of the first and second groups,

adopting a second laser cutting process to groove downwards along the bottom surface of the first groove to form a second groove communicated with the first groove, wherein the transverse width of the first groove is greater than that of the second groove;

the device wafer at least comprises a substrate and a mixed bonding layer positioned on the substrate, and the first groove and the second groove at least penetrate through the substrate and the mixed bonding layer, so that splitting is completed;

the hybrid bonding layer covers the back surface of the substrate, the front surface of the substrate is covered with an interconnection structure layer, a through fourth groove is formed in the interconnection structure layer, and when a groove is formed downwards along the surface of the device wafer, the groove is formed downwards along the surface of the hybrid bonding layer until the groove is communicated with the fourth groove.

2. The wafer cutting method as claimed in claim 1, wherein the linewidth of the laser of the first laser cutting process is greater than the linewidth of the laser of the second laser cutting process, so that the lateral width of the first groove is greater than the lateral width of the second groove.

3. The wafer dicing method according to claim 1 or 2, wherein a lateral width of the first groove is 10 micrometers to 30 micrometers; and/or the width of the second groove is 8-20 microns.

4. The wafer dicing method of claim 1, wherein an energy of the laser of the first laser dicing process is smaller than an energy of the laser of the second laser dicing process so that a depth of the first groove is smaller than a depth of the second groove.

5. The wafer cutting method as claimed in claim 1, wherein a wet etching process is used for etching to remove the particles on the surface of the device wafer, and the rate of the wet etching process for etching the particles is greater than the rate of etching the material on the surface of the device wafer.

6. The method as claimed in claim 1, wherein the first recess and the second recess jointly penetrate through the hybrid bonding layer and the substrate and then communicate with the fourth recess, and the first recess, the second recess and the fourth recess jointly penetrate through the device wafer and form scribe lines.