CN101840870A - Wafer-level chip size package method - Google Patents
Wafer-level chip size package method Download PDFInfo
- Publication number
- CN101840870A CN101840870A CN 200910030159 CN200910030159A CN101840870A CN 101840870 A CN101840870 A CN 101840870A CN 200910030159 CN200910030159 CN 200910030159 CN 200910030159 A CN200910030159 A CN 200910030159A CN 101840870 A CN101840870 A CN 101840870A
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- wafer
- back surface
- wafer rear
- chip size
- size package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
The invention discloses a wafer-level chip size package method comprising the following steps: a) fixing and covering a layer of glass on the front surface of a wafer, thinning the wafer to the set size and the thickness by grinding from the back surface, and carrying out the plasma etching on the back surface of the wafer; b) washing the back surface of the wafer; c) carry out laser punching on the back surface of the wafer according to the design, forming a plurality of micro-holes on the back surface of the wafer according to the design, exposing via parts on the front surface of the wafer on the back surface of the wafer and forming a plurality of via points; d) electroplating the back surface of the wafer according to the design to form metal wires which correspond to the via points in number, wherein the metal wires are connected to the via points and the positions where balls need to be welded on the back surface of the wafer; e) welding balls on the positions on the back surface of the wafer according to the design; and f) cutting the wafer into the singly packaged devices along the cutting lines. As the method utilizes the laser punching technology to produce the micro-holes, the method can avoid the burnt residue, process the holes with high quality and cleanliness therein, effectively improve the production efficiency, reduce the production cost and improve the production environment.
Description
Technical field
The present invention relates to a kind of crystal wafer chip dimension encapsulation technology field, especially a kind of wafer-level chip size package method.
Background technology
Crystal wafer chip dimension encapsulation (WLCSP) integrates chip size packages (CSP) and wafer-level packaging (WLP), after wafer encapsulation preceding working procedure is finished, directly wafer is encapsulated, tests, and cutting and separating becomes individual devices then.This technology has not only improved packaging density, packaging efficiency, has reduced packaging cost, has also improved circuit performance and quality simultaneously, has reduced inductance, electric capacity and other undesirable characteristics between I/O widely.Along with industry to the improving constantly of the requirements such as size, density, cost of encapsulation, the crystal wafer chip dimension encapsulation technology will inevitably more and more paid attention to aspect chip integrated circuit (IC) and wafer-level micro electromechanical system (MEMS) encapsulation.
The making of micropore realizes by photoetching process and etching method in traditional WLCSP technological process, however this method technology expensive time of numerous and diverse needs, but also a large amount of pollutants that produce can discharge photoetching and etching the time.
Summary of the invention
In order to overcome above-mentioned defective, the invention provides a kind of wafer-level chip size package method, can enhance productivity, reduce production costs and improve production environment.
The present invention for the technical scheme that solves its technical problem and adopt is:
A kind of wafer-level chip size package method, carry out as follows:
A. at the fixing covering in the front of wafer one deck glass, by grinder wafer is thinned to the setting dimensional thickness from grinding back surface, again wafer rear is carried out any surface finish of plasma etching until wafer rear, make wafer rear reply bright and cleanly smooth the time, eliminated the stress that wafer gathers because of grinding because of the coarse surface of grinding;
B. wafer rear is clean with acetone rinsing, remove the remaining acetone of wafer rear again with air gun;
C. carry out laser drilling at wafer rear by designing requirement by laser-beam drilling machine, form some micropores by designing requirement, form some firing points but this micropore exposes to wafer rear with wafer frontside conducting place partly at wafer rear;
D. wafer rear is electroplated by designing requirement and formed the metal wire corresponding with firing point quantity, this metal wire connection firing point and wafer rear need be planted the place of soldered ball;
E. plant soldered ball by designing requirement in the place that wafer rear need be planted soldered ball, thereby the external tie point of each device in the wafer is transferred on each soldered ball from each firing point;
F. wafer is cut into single packaged device along line of cut.
What described laser drilling was adopted is Ultra-Violet Laser punching technology, and its optical maser wavelength is 1064nm, and ion segregation coefficient (Nd concentration) is 0.6～1.1at.% (promptly adopting ultraviolet Nd:YAG laser drilling).
Described micropore is the hole of aperture smaller or equal to 50 μ m.
The invention has the beneficial effects as follows: carry out any surface finish of plasma etching behind the grinding wafer attenuate, make wafer rear reply bright and cleanly smooth the time, eliminated the stress that wafer gathers because of grinding because of the coarse surface of grinding until wafer rear; Utilize ultraviolet Nd:YAG laser drilling to carry out the making of micropore, because ultraviolet Nd:YAG laser has the short characteristics of concentration of energy, high-energy and wavelength, can be soon after the absorbed organic molecule key of material and metallic bond destroyed and be formed suspended particulate, atomic group, micel, atom or molecule and material is isolated in loss, form accurate hole, this process does not exist heat to burn residue, cleaning effectively raises production efficiency, reduced production cost and has improved production environment in the more excellent and hole of the hole quality that processes.
Description of drawings
Fig. 1 is the product structure schematic diagram behind the step a of the present invention;
Fig. 2 is the product structure schematic diagram after the steps d of the present invention;
Fig. 3 is the product structure schematic diagram behind the step e of the present invention.
Embodiment
Embodiment: a kind of wafer-level chip size package method, carry out as follows:
A. at the fixing covering in the front of wafer one deck glass 6, by grinder wafer is thinned to the setting dimensional thickness from grinding back surface, again wafer rear is carried out any surface finish of plasma etching until wafer rear, make wafer rear reply bright and cleanly smooth the time, eliminated the stress that wafer gathers because of grinding because of the coarse surface of grinding;
B. wafer rear is clean with acetone rinsing, remove the remaining acetone of wafer rear again with air gun;
C. carry out laser drilling at wafer rear by designing requirement by laser-beam drilling machine, form some micropores 3 by designing requirement, form some firing points 2 but this micropore 3 exposes to wafer rear with wafer frontside conducting place partly at wafer rear;
D. wafer rear is electroplated by designing requirement and formed the metal wire 4 corresponding with firing point 2 quantity, these metal wire 4 connection firing points 2 and wafer rear need be planted the place of soldered ball;
E. plant soldered ball 5 by designing requirement in the place that wafer rear need be planted soldered ball, thereby the external tie point of each device in the wafer is transferred on each soldered ball 5 from each firing point 2;
F. wafer is cut into single packaged device 8 along line of cut 7.
What described laser drilling was adopted is Ultra-Violet Laser punching technology, and its optical maser wavelength is 1064nm, and ion segregation coefficient (Nd concentration) is 0.6～1.1at.% (promptly adopting ultraviolet Nd:YAG laser drilling).
Described micropore 3 is the hole of aperture smaller or equal to 50 μ m.
Claims (3)
1. wafer-level chip size package method is characterized in that: carry out as follows:
A. the fixing one deck glass (6) that covers in the front of wafer is thinned to setting dimensional thickness with wafer from grinding back surface by grinder, again wafer rear is carried out any surface finish of plasma etching until wafer rear;
B. wafer rear is clean with acetone rinsing, remove the remaining acetone of wafer rear again with air gun;
C. carry out laser drilling at wafer rear by designing requirement by laser-beam drilling machine, form some micropores (3) by designing requirement, form some firing points (2) but this micropore exposes to wafer rear with wafer frontside conducting place partly at wafer rear;
D. wafer rear is electroplated by designing requirement and formed the metal wire (4) corresponding with firing point quantity, this metal wire connection firing point and wafer rear need be planted the place of soldered ball;
E. plant soldered ball (5) by designing requirement in the place that wafer rear need be planted soldered ball;
F. wafer is cut into single packaged device (8) along line of cut (7).
2. wafer-level chip size package method according to claim 1 is characterized in that: what described laser drilling was adopted is Ultra-Violet Laser punching technology, and its optical maser wavelength is 1064nm, and the ion segregation coefficient is 0.6～1.1at.%.
3. wafer-level chip size package method according to claim 1 is characterized in that: described micropore is the hole of aperture smaller or equal to 50 μ m.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910030159 CN101840870A (en) | 2009-03-20 | 2009-03-20 | Wafer-level chip size package method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910030159 CN101840870A (en) | 2009-03-20 | 2009-03-20 | Wafer-level chip size package method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101840870A true CN101840870A (en) | 2010-09-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200910030159 Pending CN101840870A (en) | 2009-03-20 | 2009-03-20 | Wafer-level chip size package method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103579020A (en) * | 2012-08-07 | 2014-02-12 | 万国半导体股份有限公司 | Packaging method for wafer-level chip |
| CN108436604A (en) * | 2018-04-23 | 2018-08-24 | 宜特(上海)检测技术有限公司 | Resist delamination grinding method applied to low dielectric material crystal covered chip |
| CN113523597A (en) * | 2021-07-08 | 2021-10-22 | 湖北三维半导体集成制造创新中心有限责任公司 | Wafer cutting method |
| CN115732321A (en) * | 2022-11-30 | 2023-03-03 | 深圳泰研半导体装备有限公司 | Wafer etching and cleaning equipment and method |
-
2009
- 2009-03-20 CN CN 200910030159 patent/CN101840870A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103579020A (en) * | 2012-08-07 | 2014-02-12 | 万国半导体股份有限公司 | Packaging method for wafer-level chip |
| CN103579020B (en) * | 2012-08-07 | 2016-06-08 | 万国半导体股份有限公司 | The method for packing of a kind of wafer stage chip |
| CN108436604A (en) * | 2018-04-23 | 2018-08-24 | 宜特(上海)检测技术有限公司 | Resist delamination grinding method applied to low dielectric material crystal covered chip |
| CN113523597A (en) * | 2021-07-08 | 2021-10-22 | 湖北三维半导体集成制造创新中心有限责任公司 | Wafer cutting method |
| CN115732321A (en) * | 2022-11-30 | 2023-03-03 | 深圳泰研半导体装备有限公司 | Wafer etching and cleaning equipment and method |
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Application publication date: 20100922 |