CN113517375A - III-V nitride semiconductor substrate and preparation method thereof - Google Patents

III-V nitride semiconductor substrate and preparation method thereof Download PDF

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Publication number
CN113517375A
CN113517375A CN202110324699.7A CN202110324699A CN113517375A CN 113517375 A CN113517375 A CN 113517375A CN 202110324699 A CN202110324699 A CN 202110324699A CN 113517375 A CN113517375 A CN 113517375A
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Prior art keywords
substrate
nitride semiconductor
iii
layer
semiconductor substrate
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Inventor
冯美鑫
蒋天浩
孙钱
邓彪
李昌群
杨勇
吕小翠
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Foshan Institute Of Industrial Technology Chinese Academy Of Sciences
Suzhou Institute of Nano Tech and Nano Bionics of CAS
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Foshan Institute Of Industrial Technology Chinese Academy Of Sciences
Suzhou Institute of Nano Tech and Nano Bionics of CAS
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Priority to CN202110324699.7A priority Critical patent/CN113517375A/en
Publication of CN113517375A publication Critical patent/CN113517375A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen

Abstract

The invention discloses a preparation method of a III-V group nitride semiconductor substrate, which comprises the following steps: the method comprises the following steps: preparing a sample, and growing and forming a buffer layer on the first surface of the substrate; growing a layer of III-V nitride semiconductor material on the buffer layer; step two: and performing electrochemical corrosion on the sample, namely putting the sample and inert metal into an electrolyte solution, connecting the second surface of the substrate with a positive electrode of a power supply, connecting a negative electrode of the power supply with the inert metal, electrifying for performing electrochemical corrosion, and performing corrosion separation between the substrate and the buffer layer to obtain the III-V group nitride semiconductor substrate. According to the technical scheme, the heterojunction is formed between the substrate and the buffer layer, the high conducting layer is formed at the interface, and the electrochemical corrosion starts from the high conducting layer, so that the III-V group nitride semiconductor material layer and the substrate are stripped.

Description

III-V nitride semiconductor substrate and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a III-V nitride semiconductor substrate and a preparation method thereof.
Background
The III-V group nitride semiconductor is called as a third-generation semiconductor material, has the advantages of large forbidden band width, good chemical stability, strong radiation resistance, strong breakdown field, high efficiency and the like, can be used for manufacturing semiconductor photoelectric devices, electronic devices and the like, and has important application markets in the fields of semiconductor illumination, laser display, new energy automobiles, 5G mobile communication, terahertz security inspection, mobile phone quick charging and the like.
Most III-V nitride semiconductor materials are heteroepitaxially grown on sapphire substrates because of the small size and high price of free-standing GaN or AlN substrates. The sapphire substrate has low thermal conductivity, so that the thermal resistance of the device is high, and the heat dissipation of the device is seriously influenced. In addition, for III-V nitride semiconductor light emitting diodes, a thicker sapphire substrate also affects the light extraction efficiency of the device.
For sapphire substrate III-V group nitride devices, a laser lift-off method is generally adopted to prepare thin film devices, a large amount of heat and stress are generated due to laser lift-off, cracks are very easily generated, the phenomenon is particularly serious when preparing sapphire substrate AlGaN thin film devices with high Al components, AlN is generally adopted as a buffer layer when the AlGaN thin film devices with high Al components are grown, the forbidden bandwidth of AlN is large (6.2eV), AlN epitaxial materials are brittle, and the thin film semiconductor devices are easy to crack when being impacted, so that the thin film semiconductor devices are difficult to prepare.
In order to prepare the group III-V nitride thin film semiconductor device, the prior art proposes that a large-size and low-cost silicon substrate is adopted to prepare the group III-V nitride semiconductor device through epitaxial growth, and then the silicon substrate is removed through processes such as thinning, grinding, dry etching or wet etching, so as to prepare the group III-V nitride thin film semiconductor device substrate. This approach has several major disadvantages: (1) because the silicon substrate is thicker, the silicon substrate needs to be thinned by methods such as thinning and grinding and then subjected to dry etching or wet etching, so that the preparation process is complex; (2) in the process of removing the silicon substrate by dry etching or wet etching, the structure of the device is easily damaged, and the performance of the device is influenced; (3) the silicon substrate for growing the III-V group nitride semiconductor material is removed in the preparation process and cannot be reused, so that the cost of the device is high.
Disclosure of Invention
The invention mainly aims to provide a preparation method of a III-V group nitride semiconductor substrate, aiming at solving the problems of complex substrate separation process, high cost and poor performance of the existing III-V group nitride semiconductor substrate.
To achieve the above object, the present invention provides a method for producing a group III-V nitride semiconductor substrate, comprising:
the method comprises the following steps: preparation of a sample comprising:
providing a substrate having a first surface and a second surface oppositely arranged;
growing and forming a buffer layer on the first surface of the substrate;
growing a layer of III-V nitride semiconductor material on the buffer layer;
step two: and performing electrochemical corrosion on the sample, namely putting the sample and inert metal into an electrolyte solution, connecting the second surface of the substrate with a positive electrode of a power supply, connecting a negative electrode of the power supply with the inert metal, electrifying for performing electrochemical corrosion, and performing corrosion separation between the substrate and the buffer layer to obtain the III-V group nitride semiconductor substrate.
Optionally, the first step: the preparation of the sample further comprises:
depositing a bonding layer on the layer of III-V nitride semiconductor material;
and bonding a support substrate on the bonding layer.
Optionally, the substrate includes any one of a silicon substrate, a sapphire substrate, and a silicon carbide substrate or a combination of two or more thereof.
Optionally, the buffer layer material comprises a single layer or multiple layers of AlxInyGa1-x-yN, wherein x is more than or equal to 0, y is less than or equal to 1, and (x + y) is more than or equal to 0 and less than or equal to 1.
Optionally, the buffer layer material includes any one or a combination of two or more of GaN, AlN, and AlGaN.
Optionally, the bonding layer includes a metal bonding layer or a non-metal bonding layer, the metal bonding layer is made of a material including any one or a combination of two or more of AuSn, NiSn, AuAu and NiGe, and the non-metal bonding layer includes an organic bonding layer and/or an oxide bonding layer.
Optionally, the support substrate includes any one or a combination of two or more of a silicon substrate, a copper support sheet, a molybdenum-copper support sheet, a molybdenum support sheet, a ceramic substrate, aluminum nitride, and diamond.
Optionally, the second surface of the substrate is formed with a metal electrode comprising any one or a combination of two or more of Ni, Ti, Pd, Pt, Au, Al, In, TiN, ITO, AuGe, AuGeNi, and IGZO.
Optionally, the electrolyte solution comprises an alkaline solution or an acidic solution, the alkaline solution comprising KOH, NaOH, TMAH, or (NH)4)2S, and the like, and the acidic solution comprises H3PO4Oxalic acid, HF or HNO3And the like, or a combination of two or more thereof.
The invention also provides a III-V group nitride semiconductor substrate prepared by any one of the preparation methods of the III-V group nitride semiconductor substrate.
According to the technical scheme, the heterojunction is formed between the substrate and the buffer layer, the high conducting layer is formed at the interface, and the electrochemical corrosion starts from the high conducting layer, so that the III-V group nitride semiconductor material layer and the silicon substrate are stripped.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a schematic view of a structure after sequentially growing a buffer layer and a III-V nitride semiconductor material layer on a substrate;
FIG. 2 is a schematic diagram of the structure after deposition of a bonding layer on the layer of III-V nitride semiconductor material and bonding of a support substrate;
FIG. 3 is a schematic view of an electrochemical etching apparatus according to the present embodiment;
FIG. 4 is a schematic structural view of the present invention after the substrate is completely peeled;
fig. 5 is a schematic flow chart of a method for manufacturing a group III-V nitride semiconductor substrate according to the present embodiment.
The reference numbers illustrate:
101: a substrate; 102: a buffer layer; 103: a layer of III-V nitride semiconductor material; 104: a bonding layer; 105: support substrate, 106: and a metal electrode.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a preparation method of a III-V group nitride semiconductor substrate, which has the advantages of simple process and low cost and is suitable for large-scale production.
In an embodiment of the present invention, referring to fig. 5, a method for fabricating a III-V nitride semiconductor substrate is provided, including:
the method comprises the following steps: preparation of a sample comprising:
a substrate is provided having oppositely disposed first and second surfaces.
Specifically, the substrate plays a supporting role, and can be sapphire, SiC, Si or MgAl2O4、LiTaO3、ZrB2、CrB2And the substrate is preferably a silicon substrate, a sapphire substrate, or a silicon carbide substrate, or more preferably a silicon substrate, and the silicon substrate for growth is required to have a good crystal orientation and surface finish, because of reactivity with a group III-V nitride semiconductor, a difference in thermal expansion coefficient, and high-temperature stability.
And growing and forming a buffer layer on the first surface of the substrate.
Specifically, referring to fig. 1, a buffer layer 102 is grown on a first surface of a substrate 101, on one hand, at a boundary between the buffer layer 102 and the substrate 101, metal ions of the buffer layer 102 are doped into the substrate 101, and when both materials of the buffer layer 102 and the substrate 101 are grown, they are single-crystal, aligned in crystal lattice, and have a large energy band difference, so that a heterojunction is formed at a boundary between the buffer layer 102 and the substrate 101, thereby forming a high-conductivity layer. The heterojunction may be a homotype heterojunction or a heterotype heterojunction, and is not limited herein. On the other hand, the buffer layer 102 has a stress and defect regulating effect for regulating lattice mismatch and thermal mismatch between the substrate 101 and the III-V semiconductor material layer.
Optionally, the buffer layer 102 material comprises a single layer or multiple layers of AlxInyGa1-x-yN, wherein x is more than or equal to 0, y is less than or equal to 1, and (x + y) is more than or equal to 0 and less than or equal to 1. Preferably, the buffer layer 101 material includes any one or two or more components of GaN, AlN, and AlGaN.
In one embodiment, the buffer layer 102 has a thickness of 5-10000A, preferably 100-5000A, and more preferably 200-4000A. The excessively thin buffer layer 102 fails to satisfy the nucleation requirements required for the subsequent growth of the group III-V nitride semiconductor material layer 103, resulting in a decrease in the growth quality of the group III-V nitride semiconductor material layer 103; too thick buffer layer 102 may cause insufficient recrystallization of III-V nitride semiconductor material layer 103 during subsequent temperature raising, affecting the quality of III-V nitride semiconductor material layer 103; too thick a buffer layer 102 also affects the light extraction efficiency of the fabricated LED.
Preferably, the buffer layer 102 is any amorphous or polycrystalline material that can be recrystallized by annealing to form hexagonal symmetric crystals, and is more preferably selected from the group consisting of: al prepared by metal organic compound chemical vapor deposition methodxGa1-xN, x is more than or equal to 0 and less than or equal to 0.5, preferably more than or equal to 0 and less than or equal to 0.2, and the preparation temperature range is 450-700 ℃, preferably 500-600 ℃; the AlN prepared by the metal organic compound chemical vapor deposition method has the temperature range of 700-1000 ℃.
Due to the fact that the preparation temperature of the buffer layer is low, the required thickness is small, the subsequent nucleation growth of the luminous III-V group nitride semiconductor material structure (especially the GaN-based luminous III-V group nitride semiconductor material structure) is guaranteed, and meanwhile the production cost can be effectively reduced. Compared with low temperature AlxGa1-xThe N layer and the AlN layer prepared by the sputtering method have the advantages of strong thickness controllability and higher crystal orientation degree, and are also beneficial to the nucleation growth of a luminous III-V group nitride semiconductor material structure (especially a GaN-based luminous III-V group nitride semiconductor material structure).
Growing a layer of III-V nitride semiconductor material on the buffer layer.
Specifically, referring to fig. 2, a III-V nitride semiconductor material layer 103 is grown on the buffer layer 102, and the III-V nitride semiconductor material may be grown by, for example, a Metal Organic Vapor Phase Epitaxy (MOVPE), a Halide Vapor Phase Epitaxy (HVPE), or a Molecular Beam Epitaxy (MBE).
Specifically, the group III-V nitride semiconductor material is usually AlxInyGa1-x-yN is represented by x, y is less than or equal to 1, and 0 is less than or equal to (x + y) is less than or equal to 1, and the III-V nitride device can be any one or the combination of more than two of a light emitting diode, a laser, a super-radiation light emitting diode, a Schottky diode, a detector, a modulator, an amplifier, a waveguide, a high electron mobility transistor, a field effect transistor and the like.
Further, the preparation of the sample further comprises forming a metal electrode on the second surface of the substrate.
Specifically, referring to fig. 4, the metal electrode 106 is formed on a second surface portion of the substrate 101, and the metal electrode 106 is deposited or coated on the second surface of the substrate 101. While the III-V nitride semiconductor material layer 103 and the metal electrode 106 are formed on the first surface and the second surface of the substrate 101, respectively, it is understood that the metal electrode 106 may be formed simultaneously with the III-V nitride semiconductor material layer 103, the metal electrode 106 may be formed after the III-V nitride semiconductor material layer 103 is formed, and the metal electrode 106 may be formed before the III-V nitride semiconductor material layer 103 is formed, which is not limited herein. It is understood that, in the embodiment of the present invention, the metal electrode 106 is not formed on the second surface of the substrate 101, but it is also possible to connect the power source through other connection methods as long as the sample can be powered on.
Alternatively, the metal electrode 106 includes any one or a combination of two or more of Ni, Ti, Pd, Pt, Au, Al, In, TiN, ITO, AuGe, AuGeNi, and IGZO, preferably AuGe.
Step two: and performing electrochemical corrosion on the sample, namely putting the sample and inert metal into an electrolyte solution, connecting the second surface of the substrate with a positive electrode of a power supply, connecting a negative electrode of the power supply with the inert metal, electrifying for performing electrochemical corrosion, and performing corrosion separation between the substrate and the buffer layer to obtain the III-V group nitride semiconductor substrate.
Specifically, referring to fig. 3 and 4, the sample prepared in the first step and the inert metal are placed in an electrolyte solution to be electrified, the second surface of the substrate is connected to the positive electrode of a power supply, the negative electrode of the power supply is connected to the inert metal, electrochemical corrosion can occur, the inert metal can be platinum, gold, and the like, and the inert metal is inactive, so that a cathode reaction occurs during the electrochemical corrosion, and the sample undergoes an anode reaction and is corroded. Since the substrate 101 and the buffer layer 102 may form a heterojunction, a highly conductive layer may be formed at the interface, and electrochemical etching may start from this highly conductive layer to peel off the group III-V nitride semiconductor material layer 103 and the substrate 101. And taking out the completely stripped sample, cleaning, wherein the stripped substrate 101 can be recycled, and the stripped III-V nitride semiconductor substrate can be prepared into a thin film device through a micro-nano processing technology.
Specifically, the corrosion rate is controlled by controlling the voltage of the electrochemical corrosion, for example, the voltage can be 1-30V, and the corrosion rate is 10-10000 nm/min.
Optionally, the electrolyte solution comprises an alkaline solution or an acidic solution, the alkaline solution comprising KOH, NaOH, TMAH, or (NH)4)2S, and the like, and the acidic solution comprises H3PO4Oxalic acid, HF or HNO3And the like, or a combination of two or more thereof.
The invention provides a method for preparing a thin film semiconductor device by stripping a substrate 101 through an electrochemical corrosion method by utilizing a high conductive layer formed between the substrate 101 and a III-V nitride semiconductor material layer 103. Compared with the prior art, the preparation method provided by the invention has three advantages: (1) the thin film device can be prepared only by electrochemical corrosion without methods such as thinning, grinding, dry etching and the like, so that the preparation process is simple; (2) the high conductive layer between the substrate 101 and the buffer layer 102 is used for electrochemical wet etching without a dry etching process, so that the structure of the device is not damaged; (3) the peeled substrate 101 can still be recycled, and thus the device cost can be reduced. In conclusion, the III-V nitride thin film semiconductor device provided by the invention has the advantages of simple process, low cost and the like, and is suitable for large-scale production.
Optionally, growing the III-V nitride semiconductor material layer on the buffer layer may further include:
and depositing a bonding layer on the III-V nitride semiconductor material layer.
Specifically, referring to fig. 2 and 4, a bonding layer 104 is deposited on the III-V nitride semiconductor material layer 103, and the bonding layer 104 is used to fix the III-V nitride semiconductor material layer 103 on the supporting substrate 105. Optionally, the bonding layer 104 includes a metal bonding layer 104 or a non-metal bonding layer 104, the metal bonding layer 104 is made of a material including any one or a combination of two or more of AuSn, NiSn, AuAu and NiGe, and the non-metal bonding layer 104 includes an organic bonding layer 104 and/or an oxide bonding layer 104.
And bonding a support substrate on the bonding layer.
Specifically, referring to fig. 2 and 4, a supporting substrate 105 is bonded on the bonding layer 104, and the supporting substrate 105 includes a temporary supporting substrate 105, a passive array display driving backplane or an active array display driving backplane.
In the embodiment of the present invention, the support substrate 105 is a substrate for transferring or fixing the group III-V nitride semiconductor material layer 103. The support substrate 105 may be a temporary support substrate 105 used only for transferring a semiconductor device, and optionally, the support substrate 105 includes any one or a combination of two or more of a silicon substrate, a copper support wafer, a molybdenum-copper support wafer, a molybdenum support wafer, a ceramic substrate, aluminum nitride, and diamond. For example, in the embodiment of the present invention, the supporting substrate 105 is a metal plate, and the semiconductor device is transferred to the next process for processing through the supporting substrate 105.
The supporting substrate 105 may also be a passive array display driving backplane or an active array display driving backplane having a certain function, wherein the passive array display driving backplane or the active array display driving backplane has a circuit and an electronic device, which is not limited in the embodiment of the present invention. By fixing the III-V nitride semiconductor material layer 103 on the support substrate 105, the semiconductor device can be easily transferred.
Embodiments of the present invention will be described in detail below with reference to specific examples, but those skilled in the art will appreciate that the following examples are only illustrative of the present invention and should not be construed as limiting the scope of the present invention. The examples, in which specific conditions are not specified, were conducted under conventional conditions or conditions recommended by the manufacturer. The reagents or instruments used are not indicated by the manufacturer, and are all conventional products available commercially.
The first embodiment is as follows: the technical scheme is utilized to prepare the Schottky diode with the GaN-based thin film structure.
The method comprises the following steps: preparation of a sample comprising:
s1: a silicon substrate is provided, the silicon substrate having a first surface and a second surface disposed opposite.
S2: AlN and AlGaN are grown on the first surface of the silicon substrate to form a buffer layer.
S3: and growing a GaN-based Schottky diode material layer on the buffer layer.
S4: and depositing silicon dioxide on the silicon substrate GaN-based Schottky diode material layer.
S5: the GaN-based schottky diode material layer is then bonded to a high thermal conductivity AlN support substrate.
S6: and depositing a metal electrode AuGe on the second surface part region of the silicon substrate.
Step two: and (3) electrochemical corrosion of the sample, namely putting the sample and platinum into an oxalic acid solution, connecting a metal electrode of the sample with a positive electrode of a power supply, connecting a negative electrode of the power supply with the platinum, electrifying for electrochemical corrosion, and corroding and separating the substrate and the buffer layer to obtain the III-V group nitride semiconductor substrate. And taking out the completely stripped sample, and cleaning. The stripped silicon substrate can be recycled, and III-V nitride semiconductor materials continue to grow; the stripped GaN-based Schottky diode film can be prepared into a GaN-based Schottky diode film device through a micro-nano processing technology.
Example two: the ultraviolet LED with the AlGaN-based thin film structure is prepared by the technical scheme.
The method comprises the following steps: preparation of a sample comprising:
s1: a silicon carbide substrate is provided having oppositely disposed first and second surfaces.
S2: AlN and AlGaN are grown on the first surface of the silicon carbide substrate to form a buffer layer.
S3: and growing an AlGaN-based ultraviolet LED material layer on the buffer layer.
S4: and depositing silicon dioxide on the AlGaN-based ultraviolet LED material layer of the silicon carbide substrate.
S5: the AlGaN-based ultraviolet LED material layer is then bonded to a high thermal conductivity molybdenum copper support substrate.
S6: and depositing metal electrodes Cr and Au on the second surface part region of the silicon carbide substrate.
Step two: and (3) electrochemical corrosion of the sample, namely putting the sample and platinum into a nitric acid solution, connecting a metal electrode of the sample with a positive electrode of a power supply, connecting a negative electrode of the power supply with the platinum, electrifying for electrochemical corrosion, and corroding and separating the substrate and the buffer layer to obtain the III-V group nitride semiconductor substrate. And taking out the completely stripped sample, and cleaning. The stripped silicon carbide substrate can be recycled, and III-V nitride semiconductor materials continue to grow; the stripped AlGaN-based ultraviolet LED film can be prepared into an AlGaN-based ultraviolet LED film device through a micro-nano processing technology.
The above description is only an alternative embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims (10)

1. A method for producing a group III-V nitride semiconductor substrate, comprising:
the method comprises the following steps: preparation of a sample comprising:
providing a substrate having a first surface and a second surface oppositely arranged;
growing and forming a buffer layer on the first surface of the substrate;
growing a layer of III-V nitride semiconductor material on the buffer layer;
step two: and performing electrochemical corrosion on the sample, namely putting the sample and inert metal into an electrolyte solution, connecting the second surface of the substrate with a positive electrode of a power supply, connecting a negative electrode of the power supply with the inert metal, electrifying for performing electrochemical corrosion, and performing corrosion separation between the substrate and the buffer layer to obtain the III-V group nitride semiconductor substrate.
2. The method of producing a group III-V nitride semiconductor substrate according to claim 1, wherein the first step: the preparation of the sample further comprises:
depositing a bonding layer on the layer of III-V nitride semiconductor material;
and bonding a support substrate on the bonding layer.
3. The method for producing a group III-V nitride semiconductor substrate according to claim 2, wherein the substrate includes any one of a silicon substrate, a sapphire substrate, and a silicon carbide substrate or a combination of two or more thereof.
4. The method of manufacturing a group III-V nitride semiconductor substrate according to claim 3, wherein the buffer layer material includes a single layer or a plurality of layers of AlxInyGa1-x-yN, wherein x is more than or equal to 0, y is less than or equal to 1, and (x + y) is more than or equal to 0 and less than or equal to 1.
5. The production method of a group III-V nitride semiconductor substrate according to claim 4, wherein the buffer layer material comprises any one or two or more components of GaN, AlN, and AlGaN.
6. The method for manufacturing a group III-V nitride semiconductor substrate according to claim 4, wherein the bonding layer includes a metal bonding layer or a non-metal bonding layer, the metal bonding layer is made of a material including any one or a combination of two or more of AuSn, NiSn, AuAu, and NiGe, and the non-metal bonding layer includes an organic bonding layer and/or an oxide bonding layer.
7. The method for producing a group III-V nitride semiconductor substrate according to claim 6, wherein the support substrate includes any one of a silicon substrate, a copper support piece, a molybdenum-copper support piece, a molybdenum support piece, a ceramic substrate, aluminum nitride, and diamond, or a combination of two or more thereof.
8. The method according to claim 7, wherein a metal electrode is formed on the second surface of the substrate, and the metal electrode comprises any one or a combination of two or more of Ni, Ti, Pd, Pt, Au, Al, In, TiN, ITO, AuGe, AuGeNi, and IGZO.
9. The method of claim 8, wherein the electrolyte solution comprises an alkaline solution or an acidic solution, and wherein the alkaline solution comprises KOH, NaOH, TMAH, or (NH)4)2S, and the like, and the acidic solution comprises H3PO4Oxalic acid, HF or HNO3And the like, or a combination of two or more thereof.
10. A group III-V nitride semiconductor substrate produced by the method for producing a group III-V nitride semiconductor substrate according to any one of claims 1 to 9.
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CN110085518A (en) * 2019-05-06 2019-08-02 南京邮电大学 A kind of preparation method for the transferable GaN film and its device that selective electrochemical method is removed
CN110620167A (en) * 2019-08-26 2019-12-27 华南师范大学 Deep ultraviolet LED based on large-area substrate stripping and preparation method thereof
CN111968907A (en) * 2020-07-10 2020-11-20 南昌大学 Nitrogen polarity III group nitride coarsening method

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