CN113517339B - High-temperature and high-pressure clamping protection device structure and manufacturing method - Google Patents
High-temperature and high-pressure clamping protection device structure and manufacturing method Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 28
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000010410 layer Substances 0.000 claims description 83
- 238000007254 oxidation reaction Methods 0.000 claims description 40
- 230000003647 oxidation Effects 0.000 claims description 38
- 239000001301 oxygen Substances 0.000 claims description 35
- 229910052760 oxygen Inorganic materials 0.000 claims description 35
- 238000000034 method Methods 0.000 claims description 34
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 26
- 238000009792 diffusion process Methods 0.000 claims description 26
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 21
- 229910052698 phosphorus Inorganic materials 0.000 claims description 21
- 239000011574 phosphorus Substances 0.000 claims description 21
- 239000012535 impurity Substances 0.000 claims description 19
- 238000001259 photo etching Methods 0.000 claims description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 239000007788 liquid Substances 0.000 claims description 11
- 239000013078 crystal Substances 0.000 claims description 10
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 8
- 238000004321 preservation Methods 0.000 claims description 8
- 239000011241 protective layer Substances 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 8
- 239000002131 composite material Substances 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 239000004642 Polyimide Substances 0.000 claims description 6
- 229920001721 polyimide Polymers 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000003786 synthesis reaction Methods 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 230000008020 evaporation Effects 0.000 claims description 4
- 238000001704 evaporation Methods 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 4
- 230000001681 protective effect Effects 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- 230000000903 blocking effect Effects 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 230000003247 decreasing effect Effects 0.000 claims description 2
- 238000007599 discharging Methods 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 1
- 229920005591 polysilicon Polymers 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 abstract description 18
- 239000002184 metal Substances 0.000 abstract description 18
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 4
- 239000000460 chlorine Substances 0.000 description 4
- 229910052801 chlorine Inorganic materials 0.000 description 4
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 3
- 239000010953 base metal Substances 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 2
- 229910008065 Si-SiO Inorganic materials 0.000 description 2
- 229910006405 Si—SiO Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000026058 directional locomotion Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/735—Lateral transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/6625—Lateral transistors
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- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
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- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a device structure for high-temperature and high-pressure clamping protection and a manufacturing method thereof. The high-temperature and high-pressure clamp protection device structure comprises a heavy phosphorus-doped substrate, wherein a high-resistance region is arranged above the heavy phosphorus-doped substrate; a main groove is formed in the center of the high-resistance region, a junction terminal extension region is formed in the main groove, a groove is formed in the bottom of the right end of the junction terminal extension region, a base region is formed in the groove, and an emitter region is formed in the base region; an oxide layer is formed above the high-resistance region; the metal connection layer of the base region and the metal connection layer of the emission region are positioned above the oxide layer, the metal connection layer of the base region is in short circuit with the base region, and the metal connection layer of the emission region is in short circuit with the emission region; the aluminum clamping protection structure is in short circuit with the base region and is located on the periphery of the base region. The aluminum clamping protection can shield movable charges under high temperature and high pressure outside a main junction of the base region, and the influence of the collected charges on the main junction is reduced.
Description
Technical Field
The invention relates to the field of semiconductor devices, in particular to a clamping device and a manufacturing method thereof.
Background
With the maturity of a high back voltage power device circuit, the requirement of a terminal application on a power transistor is higher and higher, the power transistor usually works at the highest junction temperature of a chip of 150 ℃, when a peripheral circuit omits an RCD absorption loop and the power transistor works in an off state, high voltage provided by a primary side of a transformer is directly applied to a PN junction of the power transistor, external movable charge ions generate directional motion at high temperature and high voltage, after accumulation for a certain time, the movable charge can be accumulated in an oxidation layer, the accumulated movable charge can cause breakdown degradation of the power transistor, a channel can cause large leakage current and other abnormalities, and the service life of the power transistor is influenced.
Disclosure of Invention
The invention aims to provide a high-temperature and high-pressure clamp protection device structure and a manufacturing method thereof by adopting the design of an aluminum clamp structure on the basis of not increasing the cost, so as to obtain a high-reliability and high-safety power device.
The technical scheme of the invention is as follows: the high-temperature high-pressure clamp protection device structure comprises a chip body, wherein a terminal protection area is arranged at the edge of the chip body;
a main groove is formed in the center of the high-resistance region, a junction terminal extension region is formed in the main groove, a groove is formed in the bottom of the right end of the junction terminal extension region, a base region is formed in the groove, and an emitter region is formed in the base region;
an oxide layer is formed above the high-resistance region;
the metal connection layer of the base region and the metal connection layer of the emitter region are positioned above the oxide layer, the metal connection layer of the base region is in short circuit with the base region, and the metal connection layer of the emitter region is in short circuit with the emitter region;
the aluminum clamping protection structure is in short circuit with the base region and is positioned at the periphery of the base region; and forming a protective layer by adopting polyimide photoresist, wherein the protective layer is positioned above the base region metal connecting layer, the emitting region metal connecting layer and the aluminum clamping structure.
Further preferably, the oxide layer includes a thermal oxide layer, a thermal oxide PSG, a deposited PSG oxide layer, and a UDO oxide layer, which are disposed from bottom to top.
Further preferably, the width of the clamp protection structure is 30-45 micrometers.
Further preferably, the heavy-duty phosphorus-doped substrate has a resistivity of 30-70 ohms per centimeter.
Further preferably, the junction depth of the terminal extension region is 6-10 microns, and the junction depth of the base region is 14-22 microns.
The manufacturing method of the high-temperature and high-pressure clamping protection device structure is characterized by comprising the following steps of:
step one, adopting a silicon N-type single crystal wafer with high resistivity of 30-70 ohm per centimeter, wherein the crystal orientation of the single crystal wafer is<111>Using liquid POCL on both sides of a single wafer3Heavily doping phosphorus on a source, wherein the square resistance after heavy doping is less than 0.5 ohm per square, completing high-temperature diffusion at 1286 ℃ in a furnace tube after heavy doping is completed, the diffusion depth is between 160 and 240 microns, forming a substrate area after diffusion is completed, forming oxide layers with the thickness of 1-2 microns on the upper side and the lower side of the substrate area, and blocking the heavily doped phosphorus to further form the oxide layers, the substrate layer, the high-resistance area, the substrate layer and the oxide layers from top to bottom in sequence;
exposing the high-resistance area in a grinding and polishing mode, wherein the thickness of the high-resistance area is 70-100 micrometers;
growing an oxide layer of 12000-14000 angstroms in the furnace tube, forming a terminal region window of the junction terminal extension region in a negative photoresist photoetching mode, injecting boron atoms with the dosage of 1E 13-1.2E 14 into the terminal region window, and growing the oxide layer of 9500-11000 angstroms in the terminal region window in a furnace tube oxidation mode at 1000 ℃;
step three, forming a base region window in the terminal region window in a negative photoresist photoetching mode, and utilizing a furnace tube to adopt liquid B2O3The source is subjected to constant source diffusion and doped with boron impurity of which the square is 20-40 ohms per square in the base window;
then, impurity redistribution is carried out on the terminal region window and the base region window simultaneously in a mode of carrying out dry oxygen oxidation, wet oxygen oxidation of chlorine-doped hydrogen-oxygen synthesis, dry oxygen oxidation and high-temperature diffusion in sequence at high temperature of the furnace tube, a terminal extension region and a base region are respectively formed, the junction depth of the terminal extension region is 6-10 microns, the junction depth of the base region is 14-22 microns, and meanwhile, an oxide layer structure with the thickness of 1.3-1.7 microns is formed on the upper parts of the terminal extension region and the base region;
forming openings in the base region and the scribing feed area of the chip by using a negative photoresist and a wet etching mode, doping impurity phosphorus with a sheet resistance of 10-20 ohms per square in the openings by using a furnace tube and adopting a liquid phosphorus source as an impurity source to form an emitter region positioned in the base region and a terminal protection region positioned in the scribing feed area of the chip, and keeping high-concentration thermal oxidation PSG formed by doping after discharging to fix movable charges;
step five, utilizing a furnace tube to adopt a method of hydrogen-oxygen synthetic oxidation and high-temperature diffusion to ensure that hFEThe temperature is controlled to be 20-30, meanwhile, an oxide layer of 0.9-1.25 microns is formed on the upper part of the emission region, then an oxide layer of 4000-;
step six, forming contact holes for leads in the terminal protection region, the base region and the emitter region by adopting a photoetching mode, forming a 3.5-5 micron aluminum film on the upper part of the chip by adopting an evaporation process, removing a short circuit part of the bipolar transistor by adopting a photoetching and wet etching mode, and simultaneously forming an aluminum clamping structure with the width of 30-45 microns outside the base region, wherein the aluminum clamping structure is in short circuit with the base region;
and step seven, forming a protective layer with a protective effect on the upper part of the aluminum film by adopting polyimide photoresist.
Preferably, in the fifth step, the composite oxide layer is deposited by APCVD, the thickness of the composite oxide layer above the emitter region is 4000-.
Preferably, in the third step, the oxidation process includes five stages with different oxidation atmospheres, which are a first stage, a second stage, a third stage, a fourth stage and a fifth stage;
in the first stage, the temperature is heated from 850 ℃ to 1100 ℃ at the speed of 5 +/-0.1 ℃/min, and oxygen is introduced at the flow rate of 10 +/-0.1L/min;
in the second stage, the temperature is kept at 1100 ℃, oxygen is introduced at the flow rate of 10 +/-0.1L/min, and HCl is introduced at the flow rate of 400 +/-40 mL/min;
in the third stage, the temperature is kept at 1100 ℃, oxygen is introduced at the flow rate of 6 +/-0.6L/min, hydrogen is introduced at the flow rate of 9.5 +/-0.9 mL/min, and HCl is introduced at the flow rate of 400 +/-40 mL/min;
in the fourth stage, the temperature is kept at 1100 ℃, and oxygen is introduced at the flow rate of 10 +/-0.1L/min;
in the fifth stage, the temperature is increased from 1100 ℃ to 1200 ℃ at the speed of 5 plus or minus 0.1 ℃/min, the temperature is kept for 240 minutes, the temperature is decreased to 850 ℃ at the speed of 1.7 plus or minus 0.1 ℃/min, and nitrogen is introduced at the flow rate of 10 plus or minus 0.1L/min.
The first stage, heat preservation is carried out for 10 minutes at 1100 ℃;
in the second stage, the temperature is maintained at 1100 ℃ for 15 minutes;
the third stage, keeping the temperature at 1100 ℃ for 300 +/-30 minutes;
the fourth stage, heat preservation is carried out for 30 minutes at 1100 ℃;
in the fifth stage, the temperature is kept at 1200 ℃ for 240 minutes.
The positive progress effects of the invention are as follows:
1) the process design of the power transistor is different from the conventional dry-wet-dry oxidation mode, high-temperature chlorine doping oxidation is carried out in the wet oxygen process of base region oxidation, and Si-SiO is repaired through the chlorine doping oxidation2On the other hand, the interface state of (2) utilizes the characteristic of negative charge of chloride ions to the movable charge Na+、K+And the power transistor is fixed, so that the electrical performance and the reliability of the power transistor are improved.
2) The process is different from the conventional process of soaking and removing the PSG of high-concentration phosphorus formed after pre-diffusion after doping a gaseous impurity source, the PSG of the high-concentration phosphorus is reserved in the process, and the movable charge Na of the high-concentration phosphorus in an oxide layer is utilized+、K+Carry out fixation, further improve the workRate transistor electrical performance and reliability.
3) The aluminum clamp structure is widened in structural design, and movable charges under high temperature and high pressure can be shielded outside the main base region by aluminum clamp protection, so that the influence of the gathered charges on the main base region is reduced, the adaptability of the power device is fundamentally improved, and the requirement on subsequent packaging is lowered. The structure of the invention does not need additional working procedures so as to improve the cost of products, can meet the requirements through a photoetching mode and matching of proper alloy processes, and has simple process and easy realization.
Drawings
Fig. 1 is a schematic structural diagram of a device structure for high-temperature and high-voltage clamp protection according to embodiment 1 of the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
Referring to fig. 1, in embodiment 1, the high-temperature and high-pressure clamp protection device structure includes a chip body, a terminal protection region is disposed at an edge of the chip body, and the terminal protection region includes a terminal protection metal layer 71 and a terminal protection doped region 51 disposed above and below the terminal protection metal layer. The chip body comprises a heavy phosphorus-doped substrate 1, and a high-resistance region 2 is arranged above the heavy phosphorus-doped substrate 1; a main groove is formed in the center of the high-resistance region 2, a junction terminal extension region 3 is formed in the main groove, a groove is formed in the bottom of the right end of the junction terminal extension region 3, a base region 4 is formed in the groove, and an emitter region 5 is formed in the base region 4; an oxide layer 6 is formed above the high-resistance region 2; the metal-based emitter region short circuit structure further comprises a base metal connecting layer 72 and an emitter region metal connecting layer 73 which are arranged on the left and right sides, wherein the base metal connecting layer 72 and the emitter region metal connecting layer 73 are located above the oxide layer 6, the base metal connecting layer 72 is in short circuit with the base region 4, and the emitter region metal connecting layer 73 is in short circuit with the emitter region 5; the aluminum clamping protection structure is in short circuit with the base region 4 and is positioned at the periphery of the base region 4; and forming a protective layer 8 by adopting polyimide photoresist, wherein the protective layer 8 is positioned above the base region metal connecting layer 72, the emitter region metal connecting layer 73 and the aluminum clamping structure.
Further preferably, the oxide layer includes a thermal oxide layer, a thermal oxide PSG, a deposited PSG oxide layer, and a UDO oxide layer, which are disposed from bottom to top.
Further preferably, the width of the clamp protection structure is 30-45 micrometers.
Further preferably, the heavy-duty phosphorus-doped substrate has a resistivity of 30-70 ohms per centimeter.
Further preferably, the junction depth of the terminal extension region is 6-10 microns, and the junction depth of the base region is 14-22 microns.
Specifically, the high-temperature and high-voltage clamp protection device structure comprises a silicon N-type crystal orientation with high resistivity of 30-70 ohm per centimeter<111>Heavily doping phosphorus on two sides of a single wafer by using a liquid POCL3 source, wherein the square resistance after heavy doping is less than 0.5 ohm per square, completing high-temperature diffusion at 1286 ℃ in a furnace tube after heavy doping is completed, the diffusion depth is between 160 and 240 micrometers, forming a heavy phosphorus-doped substrate 1 after diffusion is completed, producing an oxide layer with the thickness of 1-2 micrometers, sealing the heavily doped phosphorus, and then leaking out of a high-resistance region 2 in a polishing mode, wherein the thickness of the high-resistance region is usually 70-100 micrometers. Growing a primary oxide layer of 12000-14000 angstroms in a furnace tube, forming a doped terminal region window of a junction extension terminal in a negative photoresist photoetching mode, injecting boron atoms with the dosage of 1E 13-1.2E 14 into the terminal region window, growing an oxide layer of 9500-11000 angstroms in the terminal region window in a furnace tube oxidation mode at 1000 ℃, and adjusting the concentration of the terminal region window in an oxidation production process. Forming a base region window doped with a base region main junction in the terminal region window by negative photoresist photoetching, and using a furnace tube to adopt a liquid B2O3The source is subjected to constant source diffusion to dope boron as an impurity in each square of 20-40 ohms per square into the base window. And then, impurity redistribution is carried out on the terminal region window and the base region window simultaneously in a mode of carrying out dry oxygen oxidation, wet oxygen oxidation of chlorine-doped hydrogen-oxygen synthesis, dry oxygen oxidation and high-temperature diffusion in sequence at high temperature of the furnace tube, the junction depth of the terminal region is 6-10 microns, the junction depth of the base region is 14-22 microns, and meanwhile, an oxide layer with the thickness of 1.3-1.7 microns is formed on the upper part of the base region. Forming an emitter region in the base region and the dicing cutting region of the chip by using a negative photoresist and a wet etching method5 and a terminal protection doping region 51, wherein impurity phosphorus doping with sheet resistance of 10-20 ohm per square is performed in the emitter region 5 and the terminal protection doping region 51 by using a furnace tube and adopting a liquid phosphorus source as an impurity source. After the furnace is taken out, the high-concentration PSG formed by doping is remained to fix the movable charges. The method of hydrogen-oxygen synthetic oxidation and high-temperature diffusion is adopted by utilizing a furnace tube to ensure thatFEThe method is 20-30, and simultaneously an oxide layer grown on the emitter region is 0.9-1.25 microns, then a 4000-9000 angstrom PSG + UDO multi-layer structure oxide layer is deposited by an APCVD method, and annealing is carried out in a furnace tube by adopting a chlorine-doped atmosphere at 1000-1100 ℃. Forming contact holes for leads in the base region window and the emitter region window by adopting a photoetching mode, forming an aluminum film of 3.5-5 microns on the upper part of a wafer by adopting an evaporation process, removing a short-circuit part of a chip by adopting a photoetching and wet etching mode, and simultaneously forming an aluminum clamping structure with the width of 30-45 microns outside the base region, wherein the aluminum clamping structure is required to be short-circuited with the base region. And a polyimide photoresist is adopted on the upper part of the aluminum film to form a protective layer with a protective effect.
Impurity redistribution is carried out on the terminal region and the base region simultaneously in the modes of high-temperature hydrogen-oxygen synthesis oxidation and high-temperature diffusion of the furnace tube, and meanwhile, an oxide layer structure with the thickness of 1.3-1.7 microns is formed on the upper portion of the base region, so that the influence of a subsequent aluminum clamping structure on the power transistor is reduced.
The manufacturing method of the high-temperature and high-pressure clamping protection device structure comprises the following steps:
step one, adopting a silicon N-type single crystal wafer with high resistivity of 30-70 ohm per centimeter, wherein the crystal orientation of the single crystal wafer is<111>Using liquid POCL on both sides of a single wafer3Heavily doping phosphorus on a source, wherein the square resistance after heavy doping is less than 0.5 ohm per square, completing high-temperature diffusion at 1286 ℃ in a furnace tube after heavy doping is completed, the diffusion depth is between 160 and 240 microns, forming a substrate area after diffusion is completed, forming oxide layers with the thickness of 1-2 microns on the upper side and the lower side of the substrate area, and blocking the heavily doped phosphorus to further form the oxide layers, the substrate layer, the high-resistance area, the substrate layer and the oxide layers from top to bottom in sequence;
exposing the high-resistance area in a grinding and polishing mode, wherein the thickness of the high-resistance area is 70-100 micrometers;
growing an oxide layer with the temperature of 12000-14000 angstroms in a furnace tube, forming a terminal region window of a junction terminal extension region in a negative photoresist photoetching mode, injecting boron atoms with the dosage of 1E 13-1.2E 14 into the terminal region window, and growing the oxide layer with the temperature of 9500 angstroms with the temperature of 11000 angstroms in the terminal region window in a furnace tube oxidation mode at 1000 ℃;
step three, forming a base region window in the terminal region window in a negative photoresist photoetching mode, and utilizing a furnace tube to adopt liquid B2O3The source is subjected to constant source diffusion and doped with boron impurity of which the square is 20-40 ohms per square in the base window;
and then, impurity redistribution is carried out on the terminal region window and the base region window simultaneously in a mode of carrying out dry oxygen oxidation, wet oxygen oxidation of chlorine-doped hydrogen-oxygen synthesis, dry oxygen oxidation and high-temperature diffusion at high temperature of the furnace tube in sequence to respectively form a terminal extension region and a base region, the junction depth of the terminal extension region is 6-10 microns, the junction depth of the base region is 14-22 microns, and meanwhile, an oxide layer structure with the thickness of 1.3-1.7 microns is formed on the upper parts of the terminal extension region and the base region.
Forming openings in the inner part of the base region and the scribing feed area of the chip by using a negative photoresist and a wet etching mode, doping impurity phosphorus with a sheet resistance of 10-20 ohms per square by using a furnace tube as an impurity source in the openings to form an emitter region positioned in the base region and a terminal protection region positioned in the scribing feed area of the chip, and after the emitter region and the terminal protection region are taken out of the furnace, reserving high-concentration thermal oxidation PSG formed by doping to fix movable charges;
step five, utilizing a furnace tube to adopt a method of hydrogen-oxygen synthetic oxidation and high-temperature diffusion to ensure that hFEThe thickness is 20-30, meanwhile, an oxide layer of 0.9-1.25 microns is formed on the upper part of the emitter region, then a 4000- & ltSP & gt 9000 & ltANG & gt composite oxide layer is deposited in an APCVD mode, and the composite oxide layer is a deposited PSG oxide layer and a UDO oxide layer which are arranged from bottom to top. Depositing a PSG oxide layer, namely a phosphorosilicate glass layer. The UDO oxide layer is a silicon oxide deposition layer. Annealing in a furnace tube by adopting a chlorine-doped atmosphere at 1000-1100 ℃;
step six, forming contact holes for leads in the terminal protection region, the base region and the emitter region by adopting a photoetching mode, forming a 3.5-5 micron aluminum film on the upper part of the chip by adopting an evaporation process, removing a short circuit part of the bipolar transistor by adopting a photoetching and wet etching mode, and simultaneously forming an aluminum clamping structure with the width of 30-45 microns outside the base region, wherein the aluminum clamping structure is in short circuit with the base region;
and step seven, forming a protective layer with a protective effect on the upper part of the aluminum film by adopting polyimide photoresist.
Preferably, in the third step, the oxidation process includes five stages with different oxidation atmospheres, which are a first stage, a second stage, a third stage, a fourth stage and a fifth stage;
in the first stage, the temperature is heated from 850 ℃ to 1100 ℃ at the speed of 5 +/-0.1 ℃/min, and oxygen is introduced at the flow rate of 10 +/-0.1L/min;
in the second stage, the temperature is kept at 1100 ℃, oxygen is introduced at the flow rate of 10 +/-0.1L/min, and HCl is introduced at the flow rate of 400 +/-40 mL/min;
in the third stage, the temperature is kept at 1100 ℃, oxygen is introduced at the flow rate of 6 +/-0.6L/min, hydrogen is introduced at the flow rate of 9.5 +/-0.9 mL/min, and HCl is introduced at the flow rate of 400 +/-40 mL/min;
in the fourth stage, the temperature is kept at 1100 ℃, and oxygen is introduced at the flow rate of 10 +/-0.1L/min;
in the fifth stage, the temperature is heated from 1100 ℃ to 1200 ℃ at the speed of 5 plus or minus 0.1 ℃/min, the temperature is kept for 240 minutes, the temperature is reduced to 850 ℃ at the speed of 1.7 plus or minus 0.1 ℃/min, and nitrogen is introduced at the flow rate of 10 plus or minus 0.1L/min.
The first stage, heat preservation is carried out for 10 minutes at 1100 ℃;
in the second stage, the temperature is maintained at 1100 ℃ for 15 minutes;
the third stage, heat preservation is carried out for 300 plus or minus 30 minutes at 1100 ℃;
the fourth stage, heat preservation is carried out for 30 minutes at 1100 ℃;
in the fifth stage, the temperature is kept at 1200 ℃ for 240 minutes.
The finished product is subjected to complete machine verification, the conditions of the complete machine verification are that the environment temperature is 80 ℃, the aging power is 12W, and the temperature of a plastic package body monitored by a thermocouple is 140 ℃; the temperature of the chip is calculated to be about 160 ℃. In particular, see the following table:
the positive progress effects of the invention are as follows:
1) the process design of the power transistor is different from the conventional dry-wet-dry oxidation mode, high-temperature chlorine doping oxidation is carried out in the wet oxygen process of base region oxidation, and Si-SiO is repaired through the chlorine doping oxidation2On the other hand, the interface state of (1) utilizes the negatively charged characteristic of chloride ions to the movable charge Na+、K+And the power transistor is fixed, so that the electrical performance and the reliability of the power transistor are improved.
2) The process is different from the conventional process for removing the high-concentration phosphorus PSG bubble formed after the doping of the gaseous impurity source in the process, the PSG for reserving the high-concentration phosphorus is adopted in the process, and the high-concentration phosphorus in the oxide layer is utilized to remove the movable charge Na+、K+The power transistor is fixed, and the electrical performance and reliability of the power transistor are further improved.
3) The aluminum clamp structure is widened in structural design, and the aluminum clamp protection structure can shield movable charges at high temperature and high pressure outside the main base region, so that the influence of the gathered charges on the main base region is reduced, the adaptability of the power device is comprehensively improved, and the requirement on subsequent packaging is reduced. The structure of the invention does not need additional working procedures so as to improve the cost of products, can meet the requirements through a photoetching mode and matching of proper alloy processes, and has simple process and easy realization.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that it is obvious to those skilled in the art that various modifications and improvements can be made without departing from the principle of the present invention, and these modifications and improvements should also be considered as the protection scope of the present invention.
Claims (5)
1. A manufacturing method of a high-temperature and high-pressure clamp protection device structure is characterized by comprising the following steps:
step one, adopting a silicon N-type single crystal wafer with high resistivity of 30-70 ohm per centimeter, wherein the crystal orientation of the single crystal wafer is<111>Using liquid POCL on both sides of a single wafer3Heavily doping phosphorus on a source, wherein the square resistance after heavily doping is less than 0.5 ohm per square, completing high-temperature diffusion at 1286 ℃ in a furnace tube after heavily doping is completed, the diffusion depth is between 160-240 microns, forming a substrate area after diffusion is completed, forming oxide layers with the thickness of 1-2 microns on the upper side and the lower side of the substrate area, and blocking the heavily doped phosphorus to further form the oxide layer, a substrate layer, a high-resistance area, the substrate layer and the oxide layer from top to bottom;
exposing the high-resistance area in a grinding and polishing mode, wherein the thickness of the high-resistance area is 70-100 micrometers;
growing an oxide layer of 12000-14000 angstroms in the furnace tube, forming a terminal region window of the junction terminal extension region in a negative photoresist photoetching mode, injecting boron atoms with the dosage of 1E 13-1.2E 14 into the terminal region window, and growing the oxide layer of 9500-11000 angstroms in the terminal region window in a furnace tube oxidation mode at 1000 ℃;
step three, forming a base region window in the terminal region window in a negative photoresist photoetching mode, and utilizing a furnace tube to adopt liquid B2O3The source is subjected to constant source diffusion, and boron impurities with square blocks of 20-40 ohms per square are doped into the window of the base region;
then, impurity redistribution is carried out on the terminal region window and the base region window simultaneously in a mode of carrying out dry oxygen oxidation, wet oxygen oxidation of chlorine-doped hydrogen-oxygen synthesis, dry oxygen oxidation and high-temperature diffusion in sequence at high temperature of the furnace tube again to respectively form a terminal extension region and a base region, the junction depth of the terminal extension region is smaller than that of the base region, and meanwhile, an oxide layer structure with the thickness of 1.3-1.7 microns is formed on the upper parts of the terminal extension region and the base region;
forming openings in the base region and the scribing feed area of the chip by using a negative photoresist and a wet etching mode, doping impurity phosphorus with a sheet resistance of 10-20 ohms per square in the openings by using a furnace tube and adopting a liquid phosphorus source as an impurity source to form an emitter region positioned in the base region and a terminal protection region positioned in the scribing feed area of the chip, and keeping high-concentration thermal oxidation PSG formed by doping after discharging to fix movable charges;
step five, utilizing a furnace tube to adopt a method of hydrogen-oxygen synthetic oxidation and high-temperature diffusion to ensure that hFEThe temperature is controlled to be 20-30, meanwhile, an oxide layer of 0.9-1.25 microns is formed on the upper part of the emission region, then an oxide layer of 4000-;
step six, forming contact holes for leads in the terminal protection region, the base region and the emitter region by adopting a photoetching mode, forming a 3.5-5 micron aluminum film on the upper part of the chip by adopting an evaporation process, removing a short circuit part of the bipolar transistor by adopting a photoetching and wet etching mode, and simultaneously forming an aluminum clamping structure with the width of 30-45 microns outside the base region, wherein the aluminum clamping structure is in short circuit with the base region;
and step seven, forming a protective layer with a protective effect on the upper part of the aluminum film by adopting polyimide photoresist.
2. The method for manufacturing a high-temperature high-voltage clamp protected device structure according to claim 1, wherein: and step five, depositing a composite oxide layer in an APCVD (advanced plasma chemical vapor deposition) mode, wherein the thickness of the composite oxide layer above the emission region is 4000-9000 angstroms, and the composite oxide layer is a deposited PSG (patterned polysilicon gate) oxide layer and a UDO (ultra-violet oxide) oxide layer which are arranged from bottom to top.
3. The method for manufacturing a high-temperature high-voltage clamp protected device structure according to claim 1, wherein: the junction depth of the terminal extension region is 6-10 microns, and the junction depth of the base region is 14-22 microns.
4. The method for manufacturing a high-temperature high-voltage clamp protected device structure according to claim 1, wherein: in the third step, the oxidation process is respectively carried out in sequence for five stages with different oxidation atmospheres, namely a first stage, a second stage, a third stage, a fourth stage and a fifth stage;
in the first stage, the temperature is heated from 850 ℃ to 1100 ℃ at the speed of 5 +/-0.1 ℃/min, and oxygen is introduced at the flow rate of 10 +/-0.1L/min;
in the second stage, the temperature is kept at 1100 ℃, and oxygen is introduced at the flow rate of 10 +/-0.1L/min; introducing HCl at a flow rate of 400 +/-40 mL/min;
in the third stage, the temperature is kept at 1100 ℃, and oxygen is introduced at the flow rate of 6 +/-0.6L/min; introducing hydrogen at a flow rate of 9.5 +/-0.9 mL/min, and introducing HCl at a flow rate of 400 +/-40 mL/min;
in the fourth stage, the temperature is kept at 1100 ℃, and oxygen is introduced at the flow rate of 10 +/-0.1L/min;
in the fifth stage, the temperature is increased from 1100 ℃ to 1200 ℃ at the speed of 5 plus or minus 0.1 ℃/min, the temperature is kept for 240 minutes, the temperature is decreased to 850 ℃ at the speed of 1.7 plus or minus 0.1 ℃/min, and nitrogen is introduced at the flow rate of 10 plus or minus 0.1L/min.
5. The method for manufacturing a high-temperature high-voltage clamp protected device structure according to claim 4, wherein:
the first stage, heat preservation is carried out for 10 minutes at 1100 ℃;
in the second stage, the temperature is maintained at 1100 ℃ for 15 minutes;
the third stage, heat preservation is carried out for 300 plus or minus 30 minutes at 1100 ℃;
the fourth stage, heat preservation is carried out for 30 minutes at 1100 ℃;
and in the fifth stage, the temperature is kept at 1200 ℃ for 240 minutes.
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