CN113517305A - Array substrate and display panel - Google Patents

Array substrate and display panel Download PDF

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Publication number
CN113517305A
CN113517305A CN202110571874.2A CN202110571874A CN113517305A CN 113517305 A CN113517305 A CN 113517305A CN 202110571874 A CN202110571874 A CN 202110571874A CN 113517305 A CN113517305 A CN 113517305A
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pattern
patterns
region
array substrate
metal layer
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杨剑波
张波
熊黎
张毅
赵吾阳
张旭东
唐成
唐霞
魏悦
邓雷
杨国强
郭洪伟
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

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  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

The invention provides an array substrate and a display panel, wherein the array substrate comprises a source drain metal layer and a flat layer, and a preset pattern is arranged in the region, which is not covered by the flat layer, of the source drain metal layer so as to increase the exposed area of the source drain metal layer; the region, which is not covered by the flat layer, in the source drain metal layer comprises a first region; the first area is located between adjacent VDD wirings and VSS wirings on the IC side and is not covered by the flat layer. The preset pattern is added in the region, which is not coated by the flat layer, of the source drain metal layer, so that the side exposure area of the metal of the source drain metal layer can be increased, the effect of distributing developing solution to reduce the developing load effect is achieved, the side corrosion effect of the developing process on the metal is reduced, the Undercut depth is reduced, the packaging effect is improved, the CVD packaging failure risk is reduced, the GDSX problem caused by the fact that water and oxygen invade the AA region is solved, and the reliability of an OLED device is guaranteed.

Description

Array substrate and display panel
Technical Field
The invention belongs to the technical field of OLED display, and particularly relates to an array substrate and a display panel.
Background
At present, the OLED display panel is developed rapidly, VDD & VSS wiring is located on the IC side of the OLED display panel and is likely to be a channel through which water and oxygen invade an AA Area (Active Area, display Area), and the reliability of the OLED device is affected by the package effect of the VDD wiring and the VSS wiring of a source drain metal layer (SD layer).
In the actual process, the HPLN (half-tone PLN) development process in the BP (back plate) process will generate the side etching effect (2Al +2OH- + 2H) to the Al exposed at the side of the source/drain metal layer2O＝2AlO2-+3H2×) formed into hollow underwrit structure of Ti-Al-Ti, and excessive depth of the underwrit structure is liable to cause CVD (chemical vapor deposition)Long) poor Crack of the encapsulating film layer, resulting in failure of the encapsulation of the OLED device, as shown in fig. 1.
Therefore, there is a need in the art to reduce the depth of underrout and improve the packaging effect to ensure the reliability of the OLED device.
Disclosure of Invention
In order to solve the problems of reducing the depth of underrout and improving the packaging effect so as to ensure the reliability of an OLED device, the invention provides an array substrate and a display panel.
In a first aspect, an embodiment of the present invention provides an array substrate, including a source/drain metal layer and a planarization layer, where a region of the source/drain metal layer that is not covered by the planarization layer is provided with a preset pattern to increase an exposed area of the source/drain metal layer; the area, which is not covered by the flat layer, in the source drain metal layer comprises a first area, and the first area is located between adjacent VDD wiring and VSS wiring on the IC side and is not covered by the flat layer.
In some embodiments, a region of the source-drain metal layer that is not covered by the planarization layer further includes a second region, where the second region includes VDD traces and VSS traces that are adjacent to the IC side that is not covered by the planarization layer.
In some embodiments, the preset pattern disposed in the first region includes a hollow pattern or a stripe pattern;
when the preset patterns arranged in the first area comprise strip patterns, the strip patterns are one or more than one.
In some embodiments, when the plurality of stripe patterns are provided, the plurality of stripe patterns are arranged in the first region in parallel in the transverse direction or the longitudinal direction.
In some embodiments, the width of at least one of the stripe patterns ranges from 1 μm to 5 μm, and the interval between two adjacent stripe patterns ranges from 1 μm to 30 μm.
In some embodiments, a distance between the bar pattern closest to the VDD trace and the VDD trace is Δ b, a distance between the bar pattern closest to the VSS trace and the VSS trace is Δ c, and Δ b ═ Δ c is 1 μm to 30 μm.
In some embodiments, the width of the stripe pattern ranges from 20 μm to 70 μm, and the interval between two adjacent stripe patterns ranges from 10 μm to 50 μm.
In some embodiments, a plurality of first protrusion-shaped patterns are further disposed on both sides of the stripe pattern in the length direction.
In some embodiments, the first pattern of convex shapes comprises: the circular pattern and the connection part pattern of the circular pattern and the strip pattern, the convex pattern and the strip pattern are connected to form an arc, and the diameter range of the circular pattern and the diameter range of a circle where the arc is located are 1-30 mu m.
In some embodiments, the predetermined pattern disposed in the second region includes a hollow pattern.
In some embodiments, the hollow pattern includes a plurality of squares, and the squares form a plurality of grid-like patterns with mutually perpendicular stripe patterns in the first region or the second region; the width range of the strip-shaped patterns is 1-30 mu m, and the interval range between two adjacent parallel strip-shaped patterns is 1-10 mu m.
In some embodiments, the predetermined pattern of the first region arrangement includes a plurality of second convex shape patterns;
one part of the second convex-shaped patterns is connected with a VDD wire, and the other part of the second convex-shaped patterns is connected with a VSS wire; or
The second convex-shaped patterns are connected with a VDD (voltage-VDD) wire; or
The second raised shape patterns are connected with the VSS wiring.
In a second aspect, an embodiment of the present invention provides a display panel, including the array substrate of the first aspect.
One or more embodiments of the invention provide at least the following benefits:
according to the array substrate and the display panel provided by the invention, the preset pattern is added in the region which is not coated by the flat layer in the source drain metal layer, so that the side exposure area of the metal of the source drain metal layer can be increased, the effect of distributing developing solution to reduce the developing load effect is achieved, the side corrosion effect of the developing process on the metal is reduced, the underrcut depth is reduced, the packaging effect is improved, the CVD packaging failure risk is reduced, the SXGD problem caused by water and oxygen invading the AA region is solved, the reliability of an OLED device is ensured, and the GDSX defect of the OLED device is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a graph showing the poor effect of Crack on CVD encapsulation films;
FIG. 2 is a development load effect test result;
FIG. 3 is a schematic diagram of a design of a source drain metal layer of an array substrate at a position adjacent to VDD and VSS traces on an IC side in the related art;
FIG. 4 is a schematic view of a display panel according to the related art;
FIG. 5 is a schematic plan view of a VDD trace and a VSS trace in the related art;
FIG. 6 is a cross-sectional view of VDD in accordance with the schematic design shown in FIG. 3;
FIG. 7 is a schematic diagram of a predetermined pattern including a stripe pattern according to an embodiment of the present invention;
fig. 8A is a schematic view illustrating a plurality of stripe patterns transversely arranged in parallel in a first area according to an embodiment of the present invention;
FIG. 8B is a corresponding cross-sectional view of FIG. 8A;
fig. 9 is a schematic view illustrating a plurality of stripe patterns longitudinally arranged in parallel in a first area according to an embodiment of the present invention;
fig. 10 is a schematic view illustrating a plurality of first protrusion-shaped patterns when a plurality of stripe-shaped patterns are transversely arranged in parallel in a first region according to an embodiment of the present invention;
fig. 11 is a schematic view illustrating a plurality of first protrusion-shaped patterns when a plurality of stripe-shaped patterns are longitudinally arranged in parallel in a first region according to an embodiment of the present invention;
FIG. 12 is a schematic view of a first pattern of raised shapes provided by an embodiment of the present invention;
fig. 13A is a schematic diagram of a preset pattern including a hollow pattern in a second region according to an embodiment of the present invention;
FIG. 13B is a corresponding cross-sectional view of FIG. 13A;
fig. 14 is a schematic diagram of a preset pattern of the first region including a plurality of second protrusion-shaped patterns according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
Through the analysis of a packaging failure mechanism and the comparison of various products, the following results are found: GDSX defects strongly correlate with CVD fill depth: the smaller the CVD filling depth, the better the encapsulation effect, and the smaller the risk of GDSX failure (CVD filling depth target <450 nm); meanwhile, the filling depth of CVD is related to the size of the top Ti Undercut and the PI residual quantity (PI THK) in the hollow Undercut structure of Ti-Al-Ti. The data are shown in table 1.
Table 1: correlation between CVD filling depth of each product and residual quantity of Ti Undercut and PI at top
Figure BDA0003083005880000041
Through analysis and comparison, the following results are obtained:
1. the reduction of the residual PI can be realized by over-exposure and over-display of the HPDL process.
2. The Ti Underrout on the top of the source-drain metal layer is reduced, and the process can be realized by reducing the development time of the HPLN process, but the risk of residue of the HPLN process hole in the AA region and residue of other groove regions exists;
the applicant actually tests the development load effect principle, the test result is shown in fig. 2, which proves that the development load effect really exists, and according to the data after the development by the HPLN process, the developing solution has a strong side etching effect on the Al of the source and drain metal layer, and the pattern density is as follows from large to small: AA area is larger than FOP/COP is larger than VDD/VSS, and the Undercuts of the source and drain metal layers are as follows from small to large: AA region (0 μm) < FOP (0.08 μm)/COP (0.1 μm) < VSS (0.86 μm). The main reasons are as follows: the smaller the pattern density of the source-drain metal layer is, the higher the replacement efficiency of the developing solution is, and the deeper the side etching of Al is.
The pattern design at the IC side adjacent to the VDD trace and the VSS trace of the source/drain metal layer of the array substrate in the related art is shown in fig. 3, the region shown in fig. 3 is located in a region a at the IC side of the display Panel (Panel) shown in fig. 4, the VDD trace and the VSS trace in the region a are adjacent and are not covered by the PLN layer, the region a includes a first region 1 located between the VDD trace and the VSS trace at the IC side and not covered by the planarization layer, and a second region 2 including the VDD trace and the VSS trace at the IC side not covered by the planarization layer, a cross-sectional view corresponding to fig. 3 is shown in fig. 6, it can be seen that the boundary position of the PLN layer is about 50 μm, the source/drain metal layer region covered by the PLN layer is not covered by the PLN layer, and the exposed Al on the side surface can be laterally etched, so as to form a Ti-Al-Ti hollow structure. Fig. 5 is a schematic plane view of a layout of VDD and VSS traces in the related art, and in practical applications, the layout is not limited to the layout shown in fig. 5, and fig. 5 cannot be regarded as a unique limitation to the layout of VDD and VSS traces in the embodiment of the present invention. After the applicant has carried out a detailed analysis, the following conclusions are reached: the interval between the VDD wire and the VSS wire is large, the pattern density is small, the Al side exposed area of the source drain metal layer is limited, and side corrosion is easy to occur, so that a deeper Undercut structure is formed, the packaging failure risk exists, in the reliability process, water and oxygen invade an AA area, pixel failure is easy to cause, and GDSX is poor.
The embodiment of the invention provides an array substrate and a display panel, and by designing a pattern on an IC side area which is not coated by a flat layer in a source drain metal layer, the metal side exposed area of the source drain metal layer is increased to the maximum extent, the effect of unit area development load effect is finally reduced, the side corrosion effect of a development process on metal is reduced, the Undercut depth is reduced, the encapsulation effect is improved, the CVD encapsulation failure risk is reduced, the GDSX problem caused by water oxygen invading an AA area is solved, and the reliability of an OLED device is ensured.
The following examples are provided to illustrate specific embodiments of the present invention.
Example one
The embodiment provides an array substrate, which comprises a source and drain metal layer and a flat layer (PLN layer), wherein a preset pattern is arranged in a region, which is not covered by the flat layer, of the source and drain metal layer so as to increase the exposed area of the source and drain metal layer, and the region, which is not covered by the flat layer, of the source and drain metal layer comprises a first region, and the first region is located between adjacent VDD wiring and VSS wiring of an IC side and is not covered by the flat layer.
The array substrate provided by the embodiment can increase the side exposed area of the metal of the source and drain electrode metal layer by increasing the pattern in the first area which is positioned between the adjacent VDD wiring and VSS wiring of the display panel IC side and is not coated by the flat layer in the source and drain electrode metal layer, so that the effect of distributing the developing solution to reduce the developing load effect is achieved, the side corrosion effect of the developing process on the metal is reduced, the undercutback depth is reduced, the packaging effect is improved, the CVD packaging failure risk is reduced, the GDSX problem caused by the fact that water oxygen invades the AA area is solved, and the reliability of an OLED device is ensured.
Furthermore, the region of the source-drain metal layer which is not covered by the flat layer further comprises a second region, and the second region comprises adjacent VDD wiring and VSS wiring of the IC side which is not covered by the flat layer.
Through the first area which is located between the adjacent VDD wiring and VSS wiring of the display panel IC side and is not coated by the flat layer, and the adjacent VDD wiring and VSS wiring of the IC side which is not coated by the flat layer are provided with patterns, the original flat layer boundary is not required to be changed, the side exposed area of the metal of the source drain electrode metal layer can be greatly increased, the effect of distributing developing solution to reduce the developing load effect is achieved, the side corrosion effect of the developing process on the metal is reduced, the Undercut depth is reduced, the packaging effect is effectively improved, the CVD packaging failure risk is reduced, the GDSX problem caused by the fact that water and oxygen invade the AA area is solved, and the reliability of an OLED device is guaranteed.
In one case, the array substrate may be an array substrate including a PVX layer (inorganic layer), the first region and the second region of the source and drain metal layer of the array substrate, which are not covered by the planarization layer, are provided with preset patterns to increase the exposed area of the source and drain metal layer, the PVX layer is formed by adding a whole set of PVX mask process (including exposure → development → dry etching → stripping), and the side of the source and drain metal layer is covered to prevent the side of the source and drain metal layer from reacting with the developer of the HPLN process, so that the problem of GDSX caused by water and oxygen invading the AA region can be effectively solved, and the packaging effect of the display panel is improved.
In another situation, the array substrate may be an array substrate without a PVX layer, for such an array substrate, the side of the source/drain metal layer is corroded due to the absence of the PVX layer protection on the IC side, and the adjacent VDD trace and VSS trace on the IC side are etched to form an underrout structure, which results in poor packaging effect of CVD1 and CVD2 on the IC side, and when the packaging is serious, direct packaging fails, a water-oxygen channel is formed on the IC side after the packaging fails, and water-oxygen is immersed in the AA region to cause pixel failure, which may cause a serious problem of reliability GDSX (black dot defect), if the PVX layer is used to package and protect the side of the source/drain metal layer, a whole set of mask process (including exposure → development → dry etching → stripping) needs to be added to form the PVX layer, which may greatly affect the production capacity of the OLED display panel, and the introduction of the PVX layer may cause the problems of parasitic capacitance change in the AA region, contact resistance increase, and the like, further affecting the display effect, such as the uniformity of the OLED product, resulting in non-uniform light emission. And through the first region and the second region which are not coated by the flat layer in the source drain metal layer of the array substrate, the preset pattern is arranged, so that the exposed area of the source drain metal layer can be effectively increased, the packaging effect is improved, the problem of GDSX caused by water oxygen invading the AA region is effectively solved, and the cost increase and the capacity loss of the PVX mask caused by the increase of the PVX layer for packaging protection can be avoided.
Example two
In this embodiment, on the basis of the first embodiment, the preset pattern disposed in the first region includes a hollow pattern or a stripe pattern.
When the preset pattern arranged in the first area comprises a strip pattern, the strip pattern is one or more rectangular strip patterns.
In some cases, when the first region has one stripe pattern, as shown in fig. 7, a stripe pattern 3 is disposed in the first region 1, which is not covered by the planarization layer, between the VDD trace and the VSS trace adjacent to the IC side, so as to increase the exposed area of the metal of the source/drain metal layer to a certain extent, distribute the developing solution in the developing process, and reduce the depth of underrout formed by the lateral etching.
In some embodiments, when the preset pattern includes a plurality of strip patterns 3, a plurality of strip patterns 3 are disposed in a region between adjacent VDD traces and VSS traces on the IC side, which is not covered by the flat layer, and the plurality of strip patterns 3 are disposed in parallel in the first region 1 in the transverse direction, as shown in fig. 8A and 8B, it can be seen that the area of the exposed metal on the side surface of the source/drain metal layer can be greatly increased by adding the plurality of strip patterns 3 in the first region 1, and the developing solution in the developing process can be effectively shared by the strip patterns 3, so that the underrcut depth is reduced, and the packaging effect is improved; or a plurality of strip patterns 3 are longitudinally arranged in parallel in the first area 1, as shown in fig. 9. It is understood that the transverse direction, the longitudinal direction and the parallel direction are only relative descriptions in a preferred embodiment, and do not only refer to the absolute horizontal direction, the absolute vertical direction and the absolute parallel direction, and in practical application, the transverse direction can be the horizontal direction, and can also be the direction with a certain inclination angle with the horizontal direction, for example, the direction with an inclination angle of ± 15 ° with the horizontal direction. The longitudinal direction may be a vertical direction or a direction inclined at an angle to the vertical, for example, at an angle of ± 15 ° to the vertical. The parallel may be absolute parallel between a plurality of strip patterns 3, or may be approximate parallel between a plurality of strip patterns 3, that is: when the stripe patterns 3 are arranged in parallel in the transverse direction or the longitudinal direction, they are also considered to be parallel within a certain angle range (e.g.. ltoreq.15 °), and the above 15 ° is only an example and does not constitute a limitation of the present invention. The first region 1 shown in fig. 7 to 9 is merely an illustration and is not a limitation of the present invention, and in practical applications, the first region may also include other regions of the source/drain metal layer on the IC side, which are not covered by the planarization layer.
Further, in the case where the predetermined pattern includes a plurality of stripe patterns 3, and the plurality of stripe patterns 3 are disposed in parallel in the horizontal or vertical direction in the first region 1, in order to satisfy the principle that the line width is as small as possible under the exposure resolution, the width range of at least one stripe pattern 3 is 1 μm to 5 μm in consideration of, on one hand, the minimum width (lower limit value of the width range) of the stripe pattern 3 that can be actually produced and, on the other hand, the effect of distributing the developer is reduced in consideration of the reduction in the number of blocks of the stripe pattern 3 due to the excessively wide width. In order to avoid that the interval between two adjacent stripe patterns 3 is too large to reduce the number of stripe patterns 3 and thus reduce the effect of distributing the developing solution, it is preferable that the interval between two adjacent stripe patterns 3 is in the range of Δ a 1 μm to 30 μm, and it should be understood that the width of a stripe pattern 3 refers to the distance between two long sides of a stripe pattern. The distance between the strip pattern closest to the VDD trace and the VDD trace is Δ b, the distance between the strip pattern closest to the VSS trace and the VSS trace is Δ c, and Δ b is 1 μm to 30 μm. In order to maximize the exposed area of the metal in the first region 1, preferably, the length of the strip pattern 3 is the difference between the distance between the VDD trace and the VSS trace and 2 Δ b, and the side exposed area of the metal of the source/drain metal layer is increased to the maximum extent, so that the underrout depth is reduced, the packaging effect is improved, and the reliability of the device is ensured.
It can be understood that the widths of the respective bar patterns may be the same or different, the intervals between two adjacent bar patterns may also be the same or different, the distance between the bar pattern closest to the VDD trace and the VDD trace, and the distance between the bar pattern closest to the VSS trace and the VSS trace may be the same or different, and this embodiment is not limited exclusively.
Taking fig. 8A as an example, when the plurality of bar patterns 3 are transversely disposed in parallel in the first area 1, if the lengths of the plurality of bar patterns 3 are the same, the positions of the short sides of each bar pattern 3 close to the VDD trace side and the VDD trace are the same, each bar pattern 3 is the bar pattern closest to the VDD trace, the distance between each bar pattern 3 and the VDD trace is Δ b, and similarly, the positions of the short sides of each bar pattern 3 close to the VSS trace side and the VSS trace are the same, and the distance between each bar pattern closest to the VSS trace and the VSS trace is Δ b.
Taking fig. 9 as an example, when the plurality of bar patterns 3 are longitudinally arranged in parallel in the first area 1, the leftmost bar pattern is the bar pattern closest to the VDD trace, the rightmost bar pattern is the bar pattern closest to the VSS trace, and the distance between the leftmost bar pattern and the VDD trace and the distance between the rightmost bar pattern and the VSS trace may be the same or different.
The plurality of strip-shaped patterns are transversely or longitudinally arranged in parallel in the first area, so that the side exposure area of metal of the source and drain metal layer can be increased to a greater extent, developing solution in a developing process is effectively shared, the depth of the underrout formed by the side etching effect is reduced, and the packaging effect is greatly improved.
In addition, in some cases, the predetermined pattern includes a plurality of stripe patterns 3, and in the case that the plurality of stripe patterns 3 are disposed in parallel in the first region in the transverse direction or the longitudinal direction, the width of the stripe patterns may also be in a range of 20 μm to 70 μm, and accordingly, the interval between two adjacent stripe patterns may be in a range of 10 μm to 50 μm.
EXAMPLE III
In this embodiment, on the basis of the first embodiment and the second embodiment, in order to increase the circumference of the side surface of the strip pattern to the maximum extent and to increase the metal exposed area of the source/drain metal layer greatly under the condition that the preset pattern includes a plurality of strip patterns which are arranged in parallel in the first region in the transverse direction or the longitudinal direction, a plurality of first protrusion-shaped patterns are further arranged on both sides of the strip pattern 3 along the length direction, so that a plurality of twist-shaped patterns 3 'are formed in the first region 1 which is not covered by the planarization layer between the adjacent VDD trace and VSS trace on the IC side, and the twist-shaped patterns 3' are obtained by adding a plurality of first protrusion-shaped patterns on both sides of the strip pattern 3 in the first embodiment in the length direction.
When the plurality of stripe patterns 3 are transversely arranged in parallel in the first region 1, a plurality of first convex-shaped patterns are arranged as shown in fig. 10. When the plurality of stripe patterns 3 are longitudinally arranged in parallel in the first region 1, a plurality of first convex-shaped patterns are arranged as shown in fig. 11.
In some cases, as shown in fig. 12, the first protrusion-shaped pattern includes: a circular pattern 31, and a connecting portion pattern 32 of the circular pattern 31 and the stripe pattern 3, the first protrusion-shaped pattern connecting with the stripe pattern 3 to form an arc, the diameter d1 range of the circular pattern 31 (inner circle) and the diameter d2 range of the (outer) circle where the arc is located being 1 μm to 30 μm. Each strip pattern 3 is provided with a plurality of first convex patterns connected with the strip pattern, so that each strip pattern is in a twist shape to increase the side perimeter of the original strip pattern.
The side perimeter of the strip-shaped patterns of the source and drain metal layers can be increased to the maximum extent through the first convex-shaped patterns, the metal side exposure area of the source and drain metal layers is greatly increased, developing solution is fully shared, the depth of the underrout formed by the side etching effect is reduced, and the packaging effect of the OLED device is guaranteed.
In other cases, the first protrusion-shaped pattern may also include a semicircular pattern connected to the stripe pattern 3, and a plurality of semicircular patterns are directly connected to the stripe pattern 3, the semicircular patterns having a diameter ranging from 1 μm to 30 μm. The purpose of increasing the side perimeter of the strip-shaped pattern of the source and drain metal layer can be achieved through the semicircular pattern, so that the metal side exposure area of the source and drain metal layer is increased.
In the present embodiment, the width of the twist pattern 3 ' is in the range of 1 μm to 5 μm in consideration of the fact that the minimum width (lower limit value of the width range) of the twist pattern 3 ' that can be actually produced, and in consideration of the fact that the effect of distributing the developing solution is reduced by decreasing the number of blocks of the twist pattern 3 ' due to an excessively wide width. In order to avoid that the spacing between adjacent twist-like patterns 3 ' is too large to reduce the number of the twist-like patterns 3 ' and thereby reduce the effect of distributing the developing solution, it is preferable that the spacing between two adjacent twist-like patterns 3 ' is in the range of Δ a from 1 μm to 30 μm, and it should be understood that the width of the twist-like pattern 3 ' refers to the distance between the outermost sides of the first protrusion-shaped patterns on both long sides of the twist-like pattern 3 '. The distance between the twist-like pattern 3 'nearest to the VDD trace and the distance between the twist-like pattern 3' nearest to the VSS trace and the VSS trace are Δ b equal to 1 μm to 30 μm, it should be understood that the distance between the twist-like pattern 3 'nearest to the VDD trace and the VDD trace is the distance between the outermost side of the first protrusion-shaped pattern on the side of the twist-like pattern 3' nearest to the VDD trace close to the VDD trace and the VDD trace, and the distance between the twist-like pattern 3 'nearest to the VSS trace and the VSS trace is the distance between the outermost side of the first protrusion-shaped pattern on the side of the twist-like pattern 3' nearest to the VSS trace close to the VSS trace. In order to maximize the exposed area of the metal in the first region 1, preferably, the length of the twist-shaped pattern 3' is the difference between the distance between the VDD trace and the VSS trace and 2 Δ b, and the side exposed area of the metal of the source/drain metal layer is increased to the maximum extent, so that the underrout depth is reduced, the packaging effect is improved, and the reliability of the device is ensured.
It can be understood that the width of each of the twist patterns 3 'may be the same or different, the interval between two adjacent twist patterns 3' may also be the same or different, the distance between the twist pattern 3 'nearest to the VDD trace and the VDD trace, and the distance between the twist pattern 3' nearest to the VSS trace and the VSS trace may be the same or different, and this embodiment is not limited uniquely.
Example four
In the embodiment, on the basis of the first embodiment, the preset pattern disposed in the second region 2 includes a hollow pattern.
In some cases, as shown in fig. 13A and 13B, the hollow pattern of the second region 2 includes a plurality of squares 4 (the squares may be squares or rectangles), the squares enable the second region 2 to form a plurality of grid patterns with mutually perpendicular bar patterns, the bar patterns in this case are similar to the bar patterns in the second embodiment, in order to enable the hollow pattern (the grid pattern) to provide more metal side exposed area to the source/drain metal layer, the width w of the bar patterns in the grid pattern ranges from 1 μm to 30 μm, the interval range between two adjacent bar patterns parallel to each other ranges from 1 μm to 10 μm, so that the metal side exposed area of the hollow pattern is as large as possible, thereby better distributing the developing solution, it can be understood that the width w of the bar patterns in the grid pattern is also the interval between two adjacent squares, the interval between two adjacent parallel strip patterns is also the width of a square. Fig. 13B is a schematic cross-sectional view of a VDD trace or a VSS trace having a hollow pattern, and it can be seen from fig. 13B that the metal side exposed area of the source/drain metal layer can be greatly increased by providing the hollow pattern for the VDD trace and the VSS trace adjacent to the IC side that is not covered by the flat layer, so that the developing solution is effectively shared in the developing process, thereby reducing the underrout depth, improving the packaging effect, ensuring the reliability of the device, and providing the VDD trace or the VSS trace as the hollow pattern.
In other cases, the hollow pattern may also include other shapes such as a plurality of circles and diamonds, so that the second region 2 forms a grid pattern to increase the metal side exposure area of the source/drain metal layer.
Similar to the hollow pattern arranged in the second region 2, when the preset pattern arranged in the first region 1 is a hollow pattern, the preset pattern may also include a plurality of squares (the squares may be squares or rectangles), and the squares enable the first region 1 to form a plurality of grid-like patterns with mutually perpendicular strip-like patterns, where the strip-like patterns in this case are similar to the strip-like patterns in the second embodiment, and in order to enable the hollow pattern (the grid-like pattern) to provide more metal side exposure area for the source/drain metal layer, the width range of the strip-like patterns in the grid-like patterns is also 1 μm to 30 μm, and the interval range between two adjacent parallel strip-like patterns is 1 μm to 10 μm, so that the metal side exposure area of the hollow pattern is as large as possible, and the developing solution is better distributed.
It should be understood that the above-mentioned mutually perpendicular does not only refer to absolute perpendicular between the stripe patterns, but also may be an angle formed between the stripe patterns of 90 ° ± α, for example, α ═ 15 °, that is, an angle formed between the stripe patterns of > 75 ° or less than 105 ° is regarded as mutually perpendicular.
Through the hollow-out patterns arranged at the VDD wiring and the VSS wiring which are adjacent to the IC side and are not coated by the flat layer, the metal side exposed area of the source drain metal layer can be greatly increased, so that developing solution is fully shared, the depth of underrcut formed by side etching is reduced, and the packaging effect of an OLED device is ensured.
It should be noted that the manner of providing the hollow patterns in the second region 2 provided in this embodiment may be implemented alone, or may be implemented in combination with the manner of providing one or more stripe patterns in the first region 1 in the second or third embodiments, or may be implemented in combination with the manner of providing the hollow patterns in the first region 1 in the second embodiment, and this embodiment is not limited to the alternative embodiment. That is to say, in practical application, the metal side exposure area of the source/drain metal layer can be increased by setting one or more strip patterns in the first region 1, the metal side exposure area of the source/drain metal layer can also be increased by setting hollow patterns in the second region 2, one or more strip patterns can be set in the first region 1, and hollow patterns can be set in the second region 2, so that the metal side exposure area of the source/drain metal layer can be increased, and the metal side exposure area of the source/drain metal layer can also be increased by setting hollow patterns in the first region 1 and the second region 2 at the same time, so that the depth of underrout formed by the side etching effect can be effectively reduced, and the packaging effect of the OLED device can be ensured.
EXAMPLE five
In the first embodiment, on the basis of the first embodiment, the first region 1, which is located between the VDD trace and the VSS trace on the IC side and is not covered by the planarization layer, as shown in fig. 14, the predetermined pattern may include a plurality of second protrusion-shaped patterns 5.
In the second convex-shaped patterns 5, one part is connected with the VDD wiring, and the other part is connected with the VSS wiring; or
The second convex-shaped patterns 5 are connected with the VDD wiring; or
The second bump-shaped patterns 5 are connected to the VSS wiring.
In the first region 1, as shown in fig. 14, a plurality of second protrusion-shaped patterns 5 are respectively connected to the VDD trace and the VSS trace, or only a plurality of second protrusion-shaped patterns 5 are connected to the VDD trace, or only a plurality of second protrusion-shaped patterns 5 are connected to the VSS trace, so that the metal side exposure area of the source/drain metal layer can be effectively increased.
In some cases, the second protrusion-like pattern 5 may be similar to the first protrusion-like pattern in the third embodiment, and include a circular pattern connected to the VDD trace or the VSS trace, and a connection portion pattern of the circular pattern and the VDD trace or the VSS trace, the second protrusion-like pattern 5 and the VDD trace or the VSS trace form a circular arc, and the range of the diameter d1 of the circular pattern (inner circle) and the range of the diameter d2 of the (outer) circle where the circular arc is located are 1 μm to 30 μm. A plurality of second convex-shaped patterns 5 connected with the VDD wiring or the VSS wiring are arranged at the edge of the VDD wiring or the VSS wiring in the first region 1, so that the perimeter of the edge of the VDD wiring or the VSS wiring is increased, and the metal side exposure area of the source drain metal layer is increased.
In other cases, the second protrusion-shaped pattern 5 may also include a plurality of semicircular patterns connected to the VDD trace or the VSS trace, the plurality of semicircular patterns are directly connected to the VDD trace or the VSS trace, and the diameter of each semicircular pattern ranges from 1 μm to 30 μm.
It can be understood that the second raised patterns 5 may be disposed only on the edge of the VDD trace in the first region 1 and connected thereto, may be disposed only on the edge of the VSS trace in the first region 1 and connected thereto, and may be disposed on the edges of the VDD trace and the VSS trace in the first region at the same time, so as to increase the exposed area of the metal side of the source/drain metal layer.
EXAMPLE six
The present embodiment provides a display panel, including the array substrate provided in the foregoing embodiments.
The display panel of the embodiment designs the pattern through the area which is not coated by the flat layer in the source drain metal layer of the array substrate, thereby increasing the metal side exposure area of the source drain metal layer to the maximum extent, reducing the effect of unit area development load effect, reducing the side corrosion effect of the development process on the metal, reducing the underrout depth, further improving the packaging effect, reducing the CVD packaging failure risk, further solving the problem that water oxygen invades the SXGD from the AA zone, improving the packaging effect of the display panel, and ensuring the reliability of the OLED device.
In the embodiments provided in the present invention, it should be understood that the disclosed system and method can be implemented in other ways. The system and method embodiments described above are merely illustrative.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Although the embodiments of the present invention have been described above, the above descriptions are only for the convenience of understanding the present invention, and are not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (13)

1. An array substrate comprises a source drain metal layer and a flat layer, and is characterized in that a preset pattern is arranged in a region, which is not covered by the flat layer, of the source drain metal layer so as to increase the exposed area of the source drain metal layer; the region, which is not covered by the flat layer, in the source drain metal layer comprises a first region; the first area is located between adjacent VDD wirings and VSS wirings on the IC side and is not covered by the flat layer.
2. The array substrate of claim 1, wherein a region of the source drain metal layer not covered by the planarization layer further comprises a second region, and the second region comprises adjacent VDD traces and VSS traces on the IC side not covered by the planarization layer.
3. The array substrate according to claim 1, wherein the predetermined pattern disposed in the first region comprises a hollow pattern or a stripe pattern;
when the preset patterns arranged in the first area comprise strip patterns, the strip patterns are one or more than one.
4. The array substrate of claim 3, wherein when the plurality of stripe patterns are arranged in parallel, the plurality of stripe patterns are arranged in the first region in a transverse or longitudinal direction.
5. The array substrate of claim 4, wherein the width of at least one of the stripe patterns ranges from 1 μm to 5 μm, and the interval between two adjacent stripe patterns ranges from 1 μm to 30 μm.
6. The array substrate of claim 4, wherein a distance between the strip pattern nearest to the VDD trace and the VDD trace is Δ b, a distance between the strip pattern nearest to the VSS trace and the VSS trace is Δ c, and Δ b- Δ c is 1 μm-30 μm.
7. The array substrate of claim 4, wherein the width of the stripe pattern ranges from 20 μm to 70 μm, and the interval between two adjacent stripe patterns ranges from 10 μm to 50 μm.
8. The array substrate of any one of claims 3 to 7, wherein the stripe pattern is further provided with a plurality of first protrusion-shaped patterns on both sides in a length direction.
9. The array substrate of claim 8, wherein the first pattern of raised shapes comprises: the first protruding-shaped pattern is connected with the strip-shaped pattern to form an arc, and the diameter range of the circular pattern and the diameter range of a circle where the arc is located are 1-30 micrometers.
10. The array substrate of claim 2, wherein the predetermined pattern disposed in the second region comprises a hollow pattern.
11. The array substrate according to claim 3 or 10, wherein the hollow pattern comprises a plurality of squares, and the squares form a plurality of grid patterns with mutually perpendicular stripe patterns in the first region or the second region; the width range of the strip-shaped patterns is 1-30 mu m, and the interval range between two adjacent parallel strip-shaped patterns is 1-10 mu m.
12. The array substrate of claim 1, wherein the predetermined pattern of the first regions comprises a plurality of second raised pattern;
one part of the second convex-shaped patterns is connected with a VDD wire, and the other part of the second convex-shaped patterns is connected with a VSS wire; or
The second convex-shaped patterns are connected with a VDD (voltage-VDD) wire; or
The second raised shape patterns are connected with the VSS wiring.
13. A display panel comprising the array substrate according to any one of claims 1 to 12.
CN202110571874.2A 2021-05-25 2021-05-25 Array substrate and display panel Pending CN113517305A (en)

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