CN113517180B

CN113517180B - Mask layout correction method and mask layout

Info

Publication number: CN113517180B
Application number: CN202010280503.4A
Authority: CN
Inventors: 郑二虎; 张冬平; 洪中山
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2020-04-10
Filing date: 2020-04-10
Publication date: 2023-08-18
Anticipated expiration: 2040-04-10
Also published as: CN113517180A

Abstract

A mask layout correction method and a mask layout, wherein the correction method comprises the following steps: forming a first mask layout, wherein the first mask layout comprises a plurality of first graphs extending along a first direction; acquiring second mask layout information, wherein the second mask layout information comprises a second mask layout, the second mask layout comprises a plurality of second graphs extending along a second direction, and after the first mask layout is overlapped with the second mask layout, the second graphs span over 1 first graph, and the second direction is mutually perpendicular to the first direction; and compensating and correcting the first patterns according to the layout information of the second mask. Thus, the performance of the semiconductor structure is improved.

Description

Mask layout correction method and mask layout

Technical Field

The invention relates to the technical field of semiconductors, in particular to a mask layout correction method and a mask layout.

Background

With the continuous progress of semiconductor integrated circuit manufacturing technology, performance is continuously improved and miniaturization of devices is accompanied. Increasingly advanced processes require as many devices as possible to be implemented in as small an area as possible.

In very large scale integrated circuits, the use of metal interconnect layers is one of the methods of achieving electrical interconnection between devices. In general, a cutting layer (Metal-cut layer) is used to insulate adjacent Metal interconnection layers, so that a distance between end portions of adjacent Metal interconnection layers needs to be smaller than an exposure limit size of an exposure process, so as to increase a density of the Metal interconnection layers and improve an integration level of an integrated circuit.

However, the performance of existing semiconductor structures is still poor.

Disclosure of Invention

The invention solves the technical problem of providing a mask layout correction method and a mask layout to improve the pattern precision of an interconnection structure and further improve the performance of a semiconductor structure.

In order to solve the technical problems, the technical scheme of the invention provides a mask layout correction method, which comprises the following steps: forming a first mask layout, wherein the first mask layout comprises a plurality of first graphs extending along a first direction; acquiring second mask layout information, wherein the second mask layout information comprises a second mask layout, the second mask layout comprises a plurality of second graphs extending along a second direction, and after the first mask layout is overlapped with the second mask layout, the second graphs span over 1 first graph, and the second direction is mutually perpendicular to the first direction; and compensating and correcting the first patterns according to the layout information of the second mask.

Optionally, each first pattern includes a plurality of first areas and a first area to be corrected, where the first areas are areas in the first pattern overlapping with the second patterns, and the first areas to be corrected are adjacent to the first areas.

Optionally, the compensation correction method includes: and forming a plurality of grooves on the first pattern boundary of the first area to be corrected, wherein the grooves are adjacent to the first area.

Optionally, along the first direction, each 4 grooves is located at two sides of 1 first area, and the 4 grooves are arranged in a central symmetry manner, and a symmetry center of the central symmetry arrangement is a center of the first area.

Optionally, each groove has a groove depth along the second direction, and the groove depth is 3% -15% of the width of the first pattern.

Optionally, each of the grooves has a groove width along the first direction, and the groove width ranges from 0.5 nm to 3 nm.

Optionally, the second mask layout further includes a plurality of third patterns extending along a second direction, and in the second direction, a length of the third patterns is greater than a length of the second patterns.

Optionally, the first patterns include first patterns to be corrected, each of the first patterns to be corrected spans the second pattern and the third pattern, and the second pattern and the third pattern are adjacent in the first direction.

Optionally, each first pattern to be corrected includes a plurality of second areas, a third area and a second area to be corrected, where the second areas are areas overlapping with the second pattern in the first pattern to be corrected, the third areas are areas overlapping with the third pattern in the first pattern to be corrected, and the second area to be corrected is adjacent to one or all of the second areas and the third areas.

Optionally, the compensation correction method includes: acquiring a first length, wherein the first length is the length of a second area to be corrected, which is positioned between the second area and the third area along a first direction; when the first length is below a preset value, cutting a first to-be-corrected graph boundary in the second to-be-corrected region between the second region and the third region to form a plurality of to-be-corrected boundary line segments, wherein each to-be-corrected boundary line segment is provided with a first interval, and the first interval is the minimum interval between the center of the to-be-corrected boundary line segment and an adjacent second region; and shifting the boundary line segments to be corrected towards the first graph to be corrected to form a corrected boundary line segment, wherein the shift amount of the boundary line segment to be corrected with small first spacing is smaller than that of the boundary line segment to be corrected with large first spacing.

Optionally, the offset of the boundary line segment to be corrected adjacent to the second region is greater than or equal to zero.

Optionally, the preset value is 30 nanometers at maximum.

Optionally, the plurality of correction boundary line segments are arranged in an axisymmetric manner, and a symmetry axis of the axisymmetric arrangement is a center line of the first graph to be corrected along the first direction.

Optionally, the method for compensating correction further includes: and forming a plurality of grooves on the boundary of the first pattern to be corrected of the second area to be corrected, which is adjacent to the second area only.

Optionally, the method for compensating correction further includes: and when the first length is below a preset value, forming a plurality of grooves on the boundary of the first pattern to be corrected of the second area to be corrected, which is adjacent to the third area only, and the grooves are adjacent to the third area.

Optionally, the method for compensating correction further includes: and when the first length is larger than a preset value, forming a plurality of grooves on the boundary of the first pattern to be corrected of the second area to be corrected, wherein the grooves are adjacent to one or all of the second area and the third area.

Optionally, along the first direction, every 4 grooves are located at two sides of 1 second area, and the 4 grooves are arranged in a central symmetry manner, and a center of symmetry of the central symmetry arrangement is a center of the second area.

Optionally, along the first direction, every 4 grooves are located at two sides of 1 third area, and the 4 grooves are arranged in a central symmetry manner, and a center of symmetry of the central symmetry arrangement is a center of the third area.

Optionally, the third pattern spans more than 2 first patterns, the first patterns further include second patterns to be corrected, and each second pattern to be corrected spans only the third pattern.

Optionally, each second pattern to be corrected includes a plurality of fourth areas and a third area to be corrected, where the fourth areas are areas overlapping with the third pattern in the second pattern to be corrected, and the third area to be corrected is adjacent to the fourth area.

Optionally, the method for compensating correction further includes: and forming a plurality of grooves on the boundary of the second pattern to be corrected of the third area to be corrected, wherein the grooves are adjacent to the fourth area.

Optionally, along the first direction, every 4 grooves are located at two sides of 1 fourth area, and the 4 grooves are arranged in a central symmetry manner, and a center of symmetry of the central symmetry arrangement is a center of the fourth area.

Optionally, the method for forming the first mask layout includes: providing a first target layout, and performing optical proximity correction on the first target layout to form the mask layout.

Correspondingly, the technical scheme of the invention also provides a mask layout, which comprises the following steps: the first mask layout comprises a plurality of first patterns extending along a first direction, each first pattern comprises a first area and a first area to be corrected, the first area to be corrected is adjacent to the first area, a plurality of grooves are formed in the first pattern boundary of the first area to be corrected, and the grooves are adjacent to the first area.

Optionally, each groove has a groove depth along a second direction, and the groove depth is 3% -15% of the width of the first pattern, and the second direction is perpendicular to the first direction.

Correspondingly, the technical scheme of the invention also provides a mask layout, which comprises the following steps: the first mask layout comprises: a plurality of first patterns extending along a first direction, the plurality of first patterns including a plurality of first patterns to be corrected, each first pattern to be corrected including a plurality of second regions, a third region, and a second region to be corrected, the second region to be corrected being adjacent to one or both of the second region and the third region, and a length of the second region to be corrected between the second region and the third region in the first direction being a first length; when the first length is below a preset value, the boundary of the first pattern to be corrected in the second area to be corrected is provided with a plurality of correction boundary line segments, in the second area to be corrected, the distance between every two adjacent correction boundary line segments along the second direction is smaller than or equal to the width of the first pattern to be corrected, the distance between every two adjacent correction boundary line segments along the second direction is reduced from the adjacent second area to the adjacent third area, and the first direction and the second direction are mutually perpendicular.

Optionally, when the first length is below a preset value, a plurality of grooves are formed on a first pattern boundary to be corrected of a second area to be corrected adjacent to the second area only, and the grooves are adjacent to the second area.

Optionally, when the first length is below a preset value, a plurality of grooves are formed on a first pattern boundary to be corrected of the second area to be corrected, which is adjacent to the third area only, and the grooves are adjacent to the third area.

Optionally, when the first length is greater than a preset value, a plurality of grooves are formed on the boundary of the first pattern to be corrected of the second area to be corrected, and the plurality of grooves are adjacent to one or all of the second area and the third area.

Optionally, the first patterns further include second patterns to be corrected, each second pattern to be corrected includes a fourth region and a third region to be corrected, the third region to be corrected is adjacent to the fourth region, a plurality of grooves are formed on the boundary of the second pattern to be corrected in the third region to be corrected, and the grooves are adjacent to the fourth region.

Compared with the prior art, the technical scheme of the invention has the following beneficial effects:

In the method for correcting the mask layout provided by the technical scheme of the invention, the first mask layout is used for forming the initial interconnection layer, the second mask layout is used for forming the cutting layer for cutting off the initial interconnection layer, and in the subsequent etching process, the distribution of the etching agent is easily influenced by the geometric figure transmitted by the cutting layer. Because the first patterns are compensated and corrected according to the layout information of the second mask, the first patterns can be corrected in advance according to the condition that the distribution of the etching agent is uneven caused by the geometric patterns transmitted by the cutting layer in the subsequent etching process, so that the different etching rates caused by the uneven distribution of the etching agent are compensated, an interconnection structure with high pattern precision and good appearance is formed, and the performance of the semiconductor structure is improved.

Further, since the grooves are formed on the boundary of the first pattern in the first region to be corrected, and the grooves are adjacent to the first region, in the case that the etching rate is high in the region near the pattern transferred by the cutting layer due to uneven etching agent distribution caused by the pattern transferred by the cutting layer formed by the second pattern, the grooves are formed, so that the material to be etched is increased, the interconnection structure with high pattern precision and good morphology is formed, and the performance of the semiconductor structure is improved.

Further, since the shapes of the second pattern and the third pattern are different, when the second pattern and the third pattern are closer, the etchant distribution between the second pattern and the third pattern is also disturbed by the other pattern. On the one hand, since the first length is acquired, the degree of the disturbance can be judged through the first length, so that whether the first pattern to be corrected in the second zone correction zone between the second zone and the third zone is required to be corrected according to the degree of the disturbance is judged; on the other hand, when the first length is below the preset value, that is, the degree of interference is larger, the plurality of boundary line segments to be corrected are shifted towards the first pattern to be corrected, and the shift amount of the boundary line segments to be corrected with small first spacing is smaller than the shift amount of the boundary line segments to be corrected with large first spacing, so that the material to be etched is increased for the situation that the etching rate of the adjacent area of the cutting layer pattern is higher, the pattern precision of the interconnection layer is improved, meanwhile, for the situation that the etching rate of the adjacent area of the third pattern is higher than that of the adjacent area of the second pattern, more etched material is increased for the area adjacent to the third pattern, and less etched material is increased for the area adjacent to the second pattern, and therefore, the interconnection structure with higher pattern precision and better appearance is further formed, and the performance of the semiconductor structure is improved.

Drawings

FIGS. 1 to 11 are schematic views of a semiconductor structure formed by steps of a process;

FIG. 12 is a flow chart of a method for correcting a mask layout according to an embodiment of the present invention;

fig. 13 to 17 are schematic views of the structure of each step of a mask pattern correction method according to an embodiment of the present invention;

FIG. 18 is a flow chart of a method for modifying a reticle layout according to another embodiment of the invention;

FIG. 19 is a schematic diagram showing the compensation correction process in FIG. 18;

fig. 20 to 26 are schematic views illustrating the structure of each step of a mask pattern correction method according to another embodiment of the present invention.

Detailed Description

As described in the background, the performance of existing semiconductor structures is still poor. The analysis will now be described with reference to specific examples.

Note that "surface" in this specification is used to describe a relative positional relationship in space, and is not limited to whether or not it is in direct contact.

Fig. 1 to 11 are schematic structural views of steps in a process of forming a semiconductor structure.

Referring to fig. 1 to 2, fig. 1 is a schematic top view of a semiconductor structure, and fig. 2 is a schematic cross-sectional view along a direction A1-A2 in fig. 1, wherein a substrate 10 is provided; forming a dielectric layer 11 on the surface of the substrate 10; forming a mask material layer 25 on the surface of the dielectric layer 11; a dicing layer 30 is formed on the surface of the mask material layer 25, where the dicing layer 30 includes a plurality of first stripe-shaped structures 31 and second stripe-shaped structures 32 extending along a first direction X, and in the first direction X, a length of the first stripe-shaped structures 31 is greater than a length of the second stripe-shaped structures 32.

Referring to fig. 3 to 4, fig. 3 is a schematic top view of fig. 1, fig. 4 is a schematic cross-sectional view of fig. 3 along a direction A1-A2, and passivation layers 13 are formed on the surface of the dicing layer 30 and the surface of the mask material layer 25; a photoresist layer 14 is formed on the surface of the passivation layer 13, and a plurality of openings 21 extending along the second direction Y are formed in the photoresist layer 14, and the openings 21 expose a portion of the surface of the passivation layer 13.

Referring to fig. 5 to 6, fig. 5 is a schematic top view of fig. 3, and fig. 6 is a schematic cross-sectional view of fig. 5 along a direction A1-A2, wherein the passivation layer 13 is etched by using the photoresist layer 14 as a mask until the surface of the mask material layer 25 is exposed to form an intermediate layer 40; after forming the intermediate layer 40, the photoresist layer 14 is removed.

Referring to fig. 7 to 8, fig. 7 is a schematic top view of fig. 5, fig. 8 is a schematic cross-sectional view of fig. 7 along the direction A1-A2, after removing the photoresist layer 14, etching the mask material layer 25 with the intermediate layer 40 and the dicing layer 30 as masks until the surface of the dielectric layer 11 is exposed to form a mask layer 26; after forming the mask layer 26, the intermediate layer 40 is removed.

Referring to fig. 9 to 11, fig. 9 is a schematic top view of fig. 7, fig. 10 is a schematic cross-sectional view of fig. 9 along the direction A1-A2, fig. 11 is a schematic cross-sectional view of fig. 9 along the direction B1-B2, after removing the intermediate layer 40, etching the dielectric layer 11 with the mask layer 26 and the dicing layer 30 as masks until the surface of the substrate 10 is exposed to form a plurality of interconnect openings 33 in the dielectric layer 11; after forming the interconnect openings 33, the mask layer 26 and the dicing layer 30 are removed; after removing the mask layer 26 and the dicing layer 30, an interconnect structure (not shown) is formed within the interconnect opening 33.

The interconnect openings 33 provide space and support for forming the interconnect structure.

In the above embodiment, the opening 21 is broken by the shielding of the dicing layer 30, so that a plurality of interconnect openings 33 can be formed in the dielectric layer 11.

However, during etching of the dielectric layer 11, since the region close to the pattern transferred by the dicing layer 30 is unevenly distributed with the etchant of the region distant from the pattern transferred by the dicing layer 30 due to the influence of the pattern transferred by the dicing layer 30 (whether or not the dicing layer 30 is removed during etching of the dielectric layer 11), the etching rate is high when etching the dielectric layer 11 close to the region of the pattern transferred by the dicing layer 30, particularly, the region near the sidewall surface of the pattern transferred by the dicing layer 30, resulting in that the dielectric layer 11 close to the pattern transferred by the dicing layer 30, particularly, the region near the sidewall surface of the pattern transferred by the dicing layer 30 is over-etched, and the width of the interconnect opening 33 of the region becomes large.

Moreover, when the first stripe-shaped structures 31 and the second stripe-shaped structures 32 are adjacent to each other and cross the same opening 21, and the distance between the first stripe-shaped structures 31 and the second stripe-shaped structures 32 is small in the second direction Y, the etchant distribution is also affected by the pattern transferred by the first stripe-shaped structures 31 and the pattern transferred by the second stripe-shaped structures 32 in the second direction Y due to the difference in shape between the first stripe-shaped structures 31 and the second stripe-shaped structures 32, that is, the etchant concentration distribution in the area near the pattern transferred by the first stripe-shaped structures 31 is affected by the pattern transferred by the first stripe-shaped structures 31, so that the etching rate in the vicinity of the first stripe-shaped structures 31 with a large length is affected by the etching agent concentration in the area near the second stripe-shaped structures 32, and the etching rate is not affected by the pattern transferred by the second stripe-shaped structures with a small etching rate in the vicinity of the second stripe-shaped structures 33 in the second direction Y, and the etching agent concentration in the area near the area of the second stripe-shaped structures 32 is formed.

In summary, the poor pattern accuracy of the interconnect openings 33 formed results in poor pattern accuracy of the interconnect structures formed, resulting in poor performance of the semiconductor structure.

In order to solve the problems, the technical scheme of the invention provides a correction method of a mask layout, which carries out compensation correction on a plurality of first patterns according to the second mask layout information, so that the first patterns can be corrected in advance according to the condition of uneven etchant distribution in a subsequent etching process, so as to compensate the problem of different etching rates caused by uneven etchant distribution, thereby forming an interconnection structure with high pattern precision and better morphology, and improving the performance of a semiconductor structure.

In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

FIG. 12 is a flowchart of a method for correcting a mask layout according to an embodiment of the present invention.

Referring to fig. 12, the method for correcting the mask layout includes:

step S100, forming a first mask layout, wherein the first mask layout comprises a plurality of first graphs extending along a first direction;

Step 200, obtaining second mask layout information, wherein the second mask layout information comprises a second mask layout, the second mask layout comprises a plurality of second graphs extending along a second direction, and after the first mask layout is overlapped with the second mask layout, the second graphs span more than 1 first graphs, and the second direction is mutually perpendicular to the first direction;

and step S300, compensating and correcting the first patterns according to the layout information of the second mask.

The first mask plate layout is used for forming an initial interconnection layer, the second mask plate layout is used for forming a cutting layer for cutting off the initial interconnection layer, and in the subsequent etching process, the etchant distribution is easily influenced by the geometric figure transmitted by the cutting layer. Because the first patterns are compensated and corrected according to the layout information of the second mask, the first patterns can be corrected in advance according to the condition that the geometric patterns transmitted by the cutting layer cause uneven distribution of the etching agent in the subsequent etching process, so that the interconnection structure with high pattern precision and good morphology is formed, and the performance of the semiconductor structure is improved.

The following detailed description refers to the accompanying drawings.

Fig. 13 to 17 are schematic views of the structure of each step of the mask pattern correction method according to the embodiment of the present invention.

Referring to fig. 13, a first reticle layout 100 is formed, the first reticle layout 100 including a plurality of first patterns 101 extending along a first direction X.

The first reticle layout 100 is used to form an initial interconnect layer.

In this embodiment, the method for forming the first mask layout 100 includes: a first target layout (not shown) is provided and optical proximity correction is performed on the first target layout to form the first reticle layout 100.

Fig. 13 schematically shows 2 first patterns 101, and the number of first patterns 101 does not affect the effect of the correction method of the present embodiment, and the number of first patterns 101 may be 1 or any number of 2 or more.

Referring to fig. 14 and 15, fig. 14 is a schematic structural diagram of overlapping the first mask layout and the second mask layout, and second mask layout information is obtained, where the second mask layout information includes a second mask layout 200.

The second mask layout 200 is used to form a cutting layer for breaking the initial interconnect layer, so that the pattern of the interconnect structure can be defined by the first mask layout 100 and the second mask layout 200.

The second reticle layout 200 includes a plurality of second patterns 201 extending along a second direction Y, and after the first reticle layout 100 is overlapped with the second reticle layout 200, the second patterns 201 span over 1 or more first patterns 101, and the second direction Y is perpendicular to the first direction X.

The second pattern 201 is used to form a pattern of the dicing layer.

In this embodiment, each first pattern 101 includes a plurality of first areas I and a first area to be corrected a, where the first areas I are areas of the first pattern 101 overlapping with the second pattern 201, and the first area to be corrected a is adjacent to the first areas I.

Specifically, the first area to be corrected a is an area adjacent to the first area I in the first pattern 101.

Referring to fig. 16 and 17, fig. 17 is a schematic diagram of a partial enlarged structure of a region K1 in fig. 16, and compensation correction is performed on a plurality of first patterns 101 according to the layout information of the second mask.

In this embodiment, the method for compensating correction includes: a plurality of grooves 102 are formed on the boundary of the first pattern 101 of the first region a to be corrected, and the grooves 102 are adjacent to the first region I.

Since the grooves 102 are formed on the boundary of the first pattern 101 in the first area a to be corrected, and the grooves 102 are adjacent to the first area I, in the case that the etching rate of the region near the pattern transferred by the dicing layer formed by the second pattern 201 is high due to the uneven distribution of the etchant in the region near the geometry transferred by the dicing layer, the material to be etched is increased by forming the grooves 102, thereby reducing the increase of the width of the interconnect structure, forming the interconnect structure with high pattern accuracy and good morphology, and improving the performance of the semiconductor structure.

In this embodiment, along the first direction X, each 4 grooves 102 are located at two sides of 1 first area I, and the 4 grooves 102 are arranged in a central symmetry manner, where a center of symmetry of the central symmetry manner is a center C1 of the first area I.

For the situation that the etching rate is higher near the first region I, the 4 grooves 102 are arranged on the first graph 101 around the first region I in a central symmetry manner, so that the material to be etched is uniformly increased in the region with the higher etching rate around the first region I, and therefore, an interconnection structure with higher graph precision and better morphology is formed, and the performance of the semiconductor structure is better improved.

In this embodiment, each of the grooves 102 has a groove depth D1 along the second direction Y, and the groove depth D1 is 3% to 15% of the width D2 of the first pattern 101.

The depth D1 of the groove is too large, so that excessive materials to be etched are added, and the added etched materials cannot be removed completely in the subsequent etching process, so that the formation of an interconnection structure with higher pattern accuracy and better morphology is not facilitated. The depth D1 of the groove is too small, so that the added material to be etched is too small, and the over-etching generated by the large concentration of the etchant and the high etching rate cannot be well compensated in the subsequent etching process, so that the formation of the interconnection structure with high pattern precision and good morphology is also not facilitated. Therefore, for the width D2 of the first pattern 101, a suitable groove depth D1 is selected, that is, when the groove depth D1 is 3% -15% of the width D2 of the first pattern 101, the etched material can be increased appropriately, so that an interconnection structure with higher pattern precision and better morphology is formed better, and the performance of the semiconductor structure is improved.

In the present embodiment, each of the grooves 102 has a groove width M1 along the first direction X, and the groove width M1 ranges from 0.5 nm to 3 nm.

If the width M1 of the groove is too large, the etched material is also increased in the area where the concentration of the etchant is affected less, that is, the area far away from the first area I, so that the increased etched material cannot be completely removed in the subsequent etching process, and therefore, the formation of the interconnection structure with higher pattern accuracy and better morphology is not facilitated. The too small groove width M1 may decrease the material to be etched in the area where the concentration of the etchant is affected greatly, that is, the area closer to the first area I, so that the over-etching generated by the relatively large concentration of the etchant and the relatively high etching rate cannot be well compensated in the subsequent etching process, which is also unfavorable for forming the interconnection structure with relatively high pattern accuracy and relatively good morphology. Therefore, when the groove width M1 is selected to be in a range of 0.5 nm to 3 nm, the etched material can be increased appropriately for the region where the concentration of the etching agent is greatly affected, so that an interconnection structure with higher pattern accuracy and better morphology can be formed better, and the performance of the semiconductor structure can be improved.

In this embodiment, the shape of the groove 102 is rectangular. In other embodiments, the shape of the groove may also be a smooth arc or the like.

Correspondingly, the embodiment of the invention also provides a mask layout corrected by the method for correcting the mask layout, please continue to refer to fig. 16 and 17, the mask layout includes: the first mask layout 100, wherein the first mask layout 100 comprises a plurality of first patterns 101 extending along a first direction X, each first pattern 101 comprises a first area I and a first area a to be corrected, the first area a to be corrected is adjacent to the first area I, a plurality of grooves 102 are formed in the boundary of the first pattern 101 of the first area a to be corrected, and the grooves 102 are adjacent to the first area I.

In this embodiment, in the first direction X, each 4 grooves 102 are located at two sides of 1 first area I, and the 4 grooves 102 are arranged in a central symmetry manner, where a center of symmetry of the central symmetry manner is a center C1 of the first area I.

In this embodiment, each of the grooves 102 has a groove depth D1 along the second direction Y, and the groove depth D1 is 3% -15% of the width D2 of the first pattern 101, and the second direction Y is perpendicular to the first direction X.

FIG. 18 is a flow chart of a method for modifying a reticle layout according to another embodiment of the invention.

Referring to fig. 18, the method for correcting the mask layout includes:

step S400, forming a first mask layout, wherein the first mask layout comprises a plurality of first graphs extending along a first direction;

s500, obtaining second mask layout information, wherein the second mask layout information comprises a second mask layout, the second mask layout comprises a plurality of second patterns and a plurality of third patterns, the second patterns extend along a second direction, the length of the third patterns is larger than that of the second patterns in the second direction, and after the first mask layout and the second mask layout are overlapped, the second patterns span over 1 first patterns, and the second direction is mutually perpendicular to the first direction;

and step S600, carrying out compensation correction on a plurality of first graphs according to the layout information of the second mask.

In this embodiment, the plurality of first patterns includes a plurality of first patterns to be corrected, each of the first patterns to be corrected spans the second pattern and the third pattern, and the second pattern and the third pattern are adjacent in the first direction.

Each first pattern to be corrected comprises a plurality of second areas, a third area and a second area to be corrected, the second areas are areas, overlapped with the second patterns, of the first pattern to be corrected, the third areas are areas, overlapped with the third patterns, of the first pattern to be corrected, and the second areas to be corrected are adjacent to one or all of the second areas and the third areas.

Fig. 19 is a schematic diagram showing the compensation correction flow in fig. 18.

Referring to fig. 19, the compensation correction method includes:

in step S610, a first length is acquired, where the first length is a length of a second area to be corrected located between the second area and the third area along the first direction.

When the first length is below a preset value, performing steps S620 to S622; when the first length is greater than a preset value, step S630 is performed.

Step S620, cutting a first to-be-corrected graph boundary in the second to-be-corrected region between the second region and the third region to form a plurality of to-be-corrected boundary line segments, wherein each to-be-corrected boundary line segment has a first interval, and the first interval is the minimum interval between the center of the to-be-corrected boundary line segment and the adjacent second region; and shifting the boundary line segments to be corrected towards the first graph to be corrected to form a corrected boundary line segment, wherein the shift amount of the boundary line segment to be corrected with small first spacing is smaller than that of the boundary line segment to be corrected with large first spacing.

In step S621, a plurality of grooves are formed on the boundary of the first pattern to be corrected of the second region adjacent to the second region only, and the plurality of grooves are adjacent to the second region.

In step S622, a plurality of grooves are formed on the boundary of the first pattern to be corrected of the second pattern to be corrected adjacent to the third pattern, and the plurality of grooves are adjacent to the third pattern.

In step S630, a plurality of grooves are formed on the boundary of the first pattern to be corrected in the second region to be corrected, and the plurality of grooves are adjacent to one or both of the second region and the third region.

After the execution of step S620 to step S622 or step S630, the execution of step S640 is continued.

In step S640, a plurality of grooves are formed on the boundary of the second pattern to be corrected in the third area to be corrected, and the plurality of grooves are adjacent to the fourth area.

It should be noted that, the technical effects of step S620, step S621, step S622, and step S640 are independent, and therefore, the execution sequence of step S620, step S621, step S622, and step S640 may be exchanged; also, the technical effects between step S630 and step S640 are independent from each other, and thus, the execution order between step S630 and step S640 may be exchanged.

In other embodiments, step S640 may also be performed prior to step S610.

The following detailed description refers to the accompanying drawings.

Referring to fig. 20, a first reticle layout 300 is formed, wherein the first reticle layout 300 includes a plurality of first patterns 301 extending along a first direction X.

The first reticle layout 300 is used to form an initial interconnect layer.

In this embodiment, the method for forming the first mask layout 300 includes: a first target layout (not shown) is provided and optical proximity correction is performed on the first target layout to form the first reticle layout 300.

In fig. 20, only 2 first patterns 301 are schematically shown, and the number of the first patterns 301 does not affect the effect of the correction method of the present embodiment, and the number of the first patterns 301 may be 1 or any number of 2 or more.

Referring to fig. 21 and 22, fig. 21 is a schematic structural diagram of the second mask layout in fig. 18, and fig. 22 is a schematic structural diagram of the first mask layout and the second mask layout after being overlapped, so as to obtain second mask layout information, where the second mask layout information includes a second mask layout 400.

The second mask layout 400 is used to form a cutting layer for breaking the initial interconnect layer, so that the pattern of the interconnect structure can be defined by the first mask layout 300 and the second mask layout 400.

The second reticle layout 400 includes a plurality of second patterns 401 extending along a second direction Y, and after the first reticle layout 300 is overlapped with the second reticle layout 400, the second patterns 401 span over 1 or more first patterns 301, and the second direction Y is perpendicular to the first direction X.

In this embodiment, the second reticle layout 400 further includes a plurality of third patterns 402 extending along the second direction Y, and in the second direction Y, a length T2 of the third patterns 402 is greater than a length T1 of the second patterns 401.

In the present embodiment, the plurality of first patterns 301 includes a plurality of first patterns 311 to be corrected, each of the first patterns 311 to be corrected spans the second pattern 401 and the third pattern 402, and the second pattern 401 and the third pattern 402 are adjacent in the first direction X.

Specifically, in the present embodiment, the first pattern to be corrected 311 is the first pattern 301 spanned by the second pattern 401 and the third pattern 402 at the same time, and the second pattern 401 and the third pattern 402 spanned by the first pattern 301 are adjacent to each other in the first direction X.

In this embodiment, each first pattern to be corrected 311 includes a plurality of second regions II, a third region III and a second region B to be corrected, where the second region II is a region overlapping with the second pattern 401 in the first pattern to be corrected 311, the third region III is a region overlapping with the third pattern 402 in the first pattern to be corrected 311, and the second region B to be corrected is adjacent to one or both of the second region II and the third region III.

Specifically, in this embodiment, the second region B to be corrected refers to a region other than the second region II and the third region III on the first pattern 311 to be corrected.

It should be noted that, in fig. 22, only 1 second area II and 1 third area III are schematically shown, the number of the second areas II may be more than 2, the number of the second areas II included in each of the first patterns 311 to be corrected may be determined according to the number of the second patterns 401 crossing the first patterns 311, the number of the third areas III may be more than 2, and the number of the third areas III included in each of the first patterns 311 to be corrected may be determined according to the number of the third patterns 402 crossing the first patterns 311.

In this embodiment, the third pattern 402 spans more than 2 first patterns 301, the plurality of first patterns 301 further includes a plurality of second patterns 312 to be corrected, and each of the second patterns 312 spans only the third pattern 402.

Specifically, in this embodiment, the second pattern to be corrected 312 is the first pattern 301 spanned only by the third pattern 402.

In this embodiment, each second pattern 312 to be corrected includes a plurality of fourth regions IV and a third region R to be corrected, where the fourth regions IV are regions of the second pattern 312 to be corrected that overlap the third pattern 402, and the third region R to be corrected is adjacent to the fourth regions IV.

Specifically, the third region R to be corrected is a region adjacent to the fourth region IV on the second map line 312 to be corrected.

In this embodiment, in fig. 21 and 22, the third pattern 402 spanning 2 first patterns 301 is schematically shown, the third pattern 402 may span any number of first patterns 301 greater than 2, and in fig. 22, only 1 fourth area IV is schematically shown, the number of fourth areas IV may be more than 2, and the number of fourth areas IV included in each second pattern 312 to be corrected is determined according to the number of third patterns 402 spanning the second pattern 312 to be corrected.

With continued reference to fig. 22, a first length W1 is obtained, where the first length W1 is the length of the second area B to be corrected located between the second area II and the third area III along the first direction X.

Since the shapes of the second pattern 401 and the third pattern 402 are different, when the second pattern 401 and the third pattern 402 are closer, the etchant distribution between the second pattern 401 and the third pattern 402 is also disturbed by the other pattern.

Since the first length W1 is obtained, the degree of the disturbance can be determined by the first length W1, so that it is advantageous to determine whether the etchant distribution caused by the disturbance is uneven or not in the subsequent step according to the degree of the disturbance, and to correct the first map 311 to be corrected in the second zone correction zone B located between the second zone II and the third zone III.

Subsequently, when the first length W1 is below a preset value, the steps S620 to S622 are executed, and the schematic structural diagrams of each of the steps S620 to S622 are shown in fig. 23 to 24; when the first length is greater than a preset value, the step S630 is performed, and the structural diagram of the specific step S630 is shown in fig. 25.

In this embodiment, the preset value is 30 nm at maximum.

If the preset value is too large, the distance between the second area II and the third area III may be far, that is, the interference degree may be small or the interference may not be present, so that the interference degree cannot be accurately determined according to the preset value. Therefore, when the maximum value of the preset value is selected, that is, the maximum value of the preset value is 30 nanometers, the interference degree can be accurately judged according to the preset value.

Referring to fig. 23, the boundary of the first pattern to be corrected 311 in the second region B to be corrected between the second region II and the third region III is cut to form a plurality of boundary line segments 321 to be corrected; each boundary line segment 321 to be modified has a first spacing S1, where the first spacing S1 is a minimum spacing between a center of the boundary line segment 321 to be modified and an adjacent second region II.

In fig. 23, a first spacing S1 of a boundary line segment 321 to be corrected adjoining the second region II is schematically shown.

Referring to fig. 24, the plurality of boundary line segments 321 to be corrected are shifted toward the first graph 311 to be corrected to form a corrected boundary line segment 322, and the shift amount of the boundary line segment 321 to be corrected with a small first spacing S1 is smaller than the shift amount of the boundary line segment 321 to be corrected with a large first spacing S1.

Since the boundary line segments 321 to be corrected are shifted toward the first pattern 311 when the first length W1 is less than the preset value, i.e., the interference is greater, the shift amount of the boundary line segments 321 to be corrected with a small first spacing S1 is smaller than the shift amount of the boundary line segments 321 to be corrected with a large first spacing S1. Therefore, not only for the case where the etching rate is high in the vicinity of the pattern transferred by the dicing layer, the material to be etched is increased to improve the pattern accuracy of the interconnect layer. Meanwhile, for the case that the etching rate is faster near the third pattern 402 than near the second pattern 401, more etched material is added in the area near the third pattern 402, and less etched material is added in the area near the second pattern 401, so that an interconnection structure with higher pattern precision and better morphology can be formed, and the performance of the semiconductor structure is better improved.

In this embodiment, the offset of the boundary line segment 321 to be modified adjacent to the second region II is greater than zero.

In other embodiments, the offset of the boundary line segment to be corrected adjacent to the second region is equal to zero.

In this embodiment, the plurality of correction boundary line segments 322 are arranged in an axisymmetric manner, and the axisymmetric axis of the axisymmetric arrangement is a center line CT1 of the first pattern to be corrected 311 along the first direction X.

With continued reference to fig. 24, a plurality of grooves 323 are formed on the boundary of the first pattern 311 of the second region B to be corrected adjacent to the second region II only, and the plurality of grooves 323 are adjacent to the second region II.

Since the etchant distribution in the second region B to be modified, which is adjacent to the second region II only, is not interfered with each other or is very little between the second pattern 401 and the third pattern 402, by forming the grooves 323, the etching rate can be high only for the region near the second pattern 401, and the material to be etched is increased around the second region II, so that an interconnection structure with higher pattern accuracy and better morphology is formed, and the performance of the semiconductor structure is better improved.

In this embodiment, the shape of the groove 323 is rectangular. In other embodiments, the shape of the groove may also be a smooth arc or the like.

With continued reference to fig. 24, a plurality of grooves 324 are formed on the boundary of the first pattern 311 of the second region B to be corrected adjacent to the third region III, and the plurality of grooves 324 are adjacent to the third region III.

Since the etchant distribution in the second region B to be modified, which is adjacent to the third region III only, is not interfered with each other or is minimally interfered with by the second pattern 401 and the third pattern 402, by forming the groove 324, the etching rate can be high only for the region near the third pattern 402, and the material to be etched is increased around the third region III, thereby forming an interconnection structure with higher pattern accuracy and better morphology, so as to better improve the performance of the semiconductor structure.

In this embodiment, the recess 324 is rectangular in shape. In other embodiments, the shape of the groove may also be a smooth arc or the like.

Referring to fig. 25, a plurality of grooves 325 are formed on the boundary of the first pattern 311 to be corrected in the second region B, and the plurality of grooves 325 are all adjacent to the second region II and the third region III.

When the first length W1 is greater than a preset value, that is, the interference degree is smaller or no interference occurs, by forming the groove 325, the material to be etched can be uniformly added in the surrounding areas of the second region II and the third region III only for the situation that the etching rate is higher near the second pattern II and the third pattern III, so that an interconnection structure with higher pattern precision and better morphology is formed, and the performance of the semiconductor structure is improved.

In other embodiments, the number of grooves are adjacent to one of the second region or the third region.

When the first length is greater than a preset value, that is, the interference degree is smaller or the interference is not generated, by forming the grooves, the material to be etched can be uniformly added around the second area or the third area only aiming at the etchant distribution condition near the second pattern or the third pattern respectively, so that the flexibility of groove arrangement is improved while the interconnection structure with higher pattern precision and better morphology is formed.

In this embodiment, along the first direction X, each 4 grooves 325 are located at two sides of 1 second area II, and the 4 grooves 325 are arranged in a central symmetry manner, and a center of symmetry of the central symmetry manner is a center C2 of the second area II.

In this embodiment, along the first direction X, each 4 grooves are further located at two sides of 1 third area III, and the 4 grooves 325 are arranged in a central symmetry manner, and a center of symmetry of the central symmetry manner is a center C3 of the third area III.

In this embodiment, the recess 325 is rectangular in shape. In other embodiments, the shape of the groove may also be a smooth arc or the like.

Subsequently, after step S620 to step S622 or step S630 are performed, step S640 is continued. Please refer to fig. 25 for a schematic structure of the step S640.

Referring to fig. 26, a plurality of grooves 326 are formed on the boundary of the second pattern 312 in the third region R to be corrected, and the plurality of grooves 326 are adjacent to the fourth region IV.

In this embodiment, along the first direction X, every 4 grooves 326 are located at two sides of 1 fourth area IV, and the 4 grooves 326 are arranged in a central symmetry manner, and the center of symmetry of the central symmetry manner is the center C4 of the fourth area IV.

In this embodiment, the recess 326 is rectangular in shape. In other embodiments, the shape of the groove may also be a smooth arc or the like.

Accordingly, another embodiment of the present invention further provides a mask layout, please continue to refer to fig. 24 to 26, including: and a first mask layout.

The first mask layout comprises: a plurality of first patterns 301 extending along a first direction X, the plurality of first patterns 301 including a plurality of first patterns 311 to be corrected, each first pattern 311 to be corrected including a plurality of second regions II, a third region III, and a second region B to be corrected, the second region B to be corrected being adjacent to one or all of the second region II and the third region III, and a length of the second region B to be corrected located between the second region II and the third region III in the first direction X being a first length W1.

Referring to fig. 24, when the first length W1 (as shown in fig. 22) is below a preset value, the boundary of the first pattern 311 to be corrected in the second area B to be corrected has a plurality of corrected boundary line segments 322, in the second area B to be corrected, the distance between each adjacent corrected boundary line segments 322 along the second direction Y is smaller than or equal to the width of the first pattern 311 to be corrected, and the distance between each adjacent corrected boundary line segment 322 along the second direction Y is reduced from the adjacent second area II to the adjacent third area III, and the first direction X and the second direction Y are perpendicular to each other.

The plurality of correction boundary line segments 322 are arranged in an axisymmetric manner, and the axisymmetric axis of the axisymmetric arrangement is a center line CT1 of the first pattern 311 to be corrected along the first direction.

With continued reference to fig. 24, when the first length W1 is below a preset value, a plurality of grooves 323 are formed on the boundary of the first pattern 311 of the second region B to be corrected, which is adjacent to the second region II only, and the plurality of grooves 323 are adjacent to the second region II.

With continued reference to fig. 24, when the first length W1 is below a preset value, a plurality of grooves 324 are formed on the boundary of the first pattern 311 of the second region B to be corrected adjacent to the third region III, and the plurality of grooves 324 are adjacent to the third region III.

Referring to fig. 25, when the first length W1 (as shown in fig. 22) is greater than a preset value, a plurality of grooves 326 are formed on the boundary of the first pattern 311 of the second area B to be corrected, and the plurality of grooves 326 are adjacent to one or both of the second area II and the third area III.

Referring to fig. 26, the first patterns 301 further include second patterns 312 to be corrected, each second pattern 312 to be corrected includes a fourth region IV and a third region R to be corrected, the third region R to be corrected is adjacent to the fourth region IV, and a plurality of grooves 326 are formed on the boundary of the second patterns 312 of the third region R to be corrected, and the plurality of grooves 326 are adjacent to the fourth region IV.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A mask layout correction method is characterized by comprising the following steps:

forming a first mask layout, wherein the first mask layout comprises a plurality of first graphs extending along a first direction;

Acquiring second mask layout information, wherein the second mask layout information comprises a second mask layout, the second mask layout comprises a plurality of second graphs extending along a second direction, and after the first mask layout is overlapped with the second mask layout, the second graphs span over 1 first graph, and the second direction is mutually perpendicular to the first direction;

and compensating and correcting the first patterns according to the layout information of the second mask.

2. The method for correcting a mask layout according to claim 1, wherein each first pattern comprises a plurality of first areas and first areas to be corrected, the first areas are areas overlapping with the second patterns in the first patterns, and the first areas to be corrected are adjacent to the first areas.

3. The method for correcting a mask layout according to claim 2, wherein the method for compensating correction comprises: and forming a plurality of grooves on the first pattern boundary of the first area to be corrected, wherein the grooves are adjacent to the first area.

4. A method of modifying a reticle layout according to claim 3, wherein each 4 grooves are located on two sides of 1 first region in the first direction, and the 4 grooves are arranged in a central symmetry, and a center of symmetry of the central symmetry is a center of the first region.

5. A method of modifying a reticle layout according to claim 3, wherein each of the grooves has a groove depth in the second direction, and the groove depth is 3% to 15% of the width of the first pattern.

6. A method of modifying a reticle layout according to claim 3, wherein each of the grooves has a groove width in the first direction, and the groove width is in the range of 0.5 nm to 3 nm.

7. The method for modifying a reticle layout according to claim 1, wherein the second reticle layout further comprises a plurality of third patterns extending in a second direction, and wherein in the second direction, a length of the third patterns is greater than a length of the second patterns.

8. The method for correcting a reticle layout according to claim 7, wherein the plurality of first patterns includes a plurality of first patterns to be corrected, each of the first patterns to be corrected spans the second pattern and the third pattern, and the second pattern and the third pattern are adjacent in the first direction.

9. The method for correcting a mask layout according to claim 8, wherein each first pattern to be corrected comprises a plurality of second regions, a third region and a second region to be corrected, the second regions are regions overlapping with the second patterns in the first pattern to be corrected, the third regions are regions overlapping with the third patterns in the first pattern to be corrected, and the second regions to be corrected are adjacent to one or both of the second regions and the third regions.

10. The method for correcting a reticle layout according to claim 9, wherein the method for compensating correction comprises: acquiring a first length, wherein the first length is the length of a second area to be corrected, which is positioned between the second area and the third area along a first direction; when the first length is below a preset value, cutting a first to-be-corrected graph boundary in the second to-be-corrected region between the second region and the third region to form a plurality of to-be-corrected boundary line segments, wherein each to-be-corrected boundary line segment is provided with a first interval, and the first interval is the minimum interval between the center of the to-be-corrected boundary line segment and an adjacent second region; and shifting the boundary line segments to be corrected towards the first graph to be corrected to form a corrected boundary line segment, wherein the shift amount of the boundary line segment to be corrected with small first spacing is smaller than that of the boundary line segment to be corrected with large first spacing.

11. The method for correcting a reticle layout according to claim 10, wherein an offset of a boundary line segment to be corrected adjacent to the second region is greater than or equal to zero.

12. The method for correcting a reticle layout according to claim 10, wherein the preset value is 30 nm at maximum.

13. The method for correcting a mask layout according to claim 10, wherein the plurality of correction boundary line segments are arranged in an axisymmetric manner, and a symmetry axis of the axisymmetric arrangement is a center line of the first pattern to be corrected along the first direction.

14. The method for correcting a reticle layout according to claim 10, wherein the method for compensating correction further comprises: and forming a plurality of grooves on the boundary of the first pattern to be corrected of the second area to be corrected, which is adjacent to the second area only.

15. The method for correcting a reticle layout according to claim 10, wherein the method for compensating correction further comprises: and when the first length is below a preset value, forming a plurality of grooves on the boundary of the first pattern to be corrected of the second area to be corrected, which is adjacent to the third area only, and the grooves are adjacent to the third area.

16. The method for correcting a reticle layout according to claim 10, wherein the method for compensating correction further comprises: and when the first length is larger than a preset value, forming a plurality of grooves on the boundary of the first pattern to be corrected of the second area to be corrected, wherein the grooves are adjacent to one or all of the second area and the third area.

17. The method for correcting a mask layout according to claim 16, wherein each 4 grooves are located at two sides of 1 second area along the first direction, the 4 grooves are arranged in a central symmetry manner, and a symmetry center of the central symmetry arrangement is a center of the second area.

18. The method for correcting a mask layout according to claim 16, wherein each 4 grooves are located at two sides of 1 third region along the first direction, and the 4 grooves are arranged in a central symmetry manner, and a symmetry center of the central symmetry arrangement is a center of the third region.

19. The method for correcting a mask layout according to claim 10, wherein the third pattern spans more than 2 first patterns, the plurality of first patterns further comprise a plurality of second patterns to be corrected, and each second pattern to be corrected spans only the third pattern.

20. The method for correcting a mask layout according to claim 19, wherein each second pattern to be corrected comprises a plurality of fourth areas and third areas to be corrected, the fourth areas are areas overlapping with the third pattern in the second pattern to be corrected, and the third areas to be corrected are adjacent to the fourth areas.

21. The method for correcting a reticle layout according to claim 20, wherein the method for compensating correction further comprises: and forming a plurality of grooves on the boundary of the second pattern to be corrected of the third area to be corrected, wherein the grooves are adjacent to the fourth area.

22. The method for correcting a mask layout according to claim 21, wherein each 4 grooves are located at two sides of 1 fourth region along the first direction, and the 4 grooves are arranged in a central symmetry manner, and a symmetry center of the central symmetry arrangement is a center of the fourth region.

23. The method of modifying a reticle layout according to claim 1, wherein the method of forming the first reticle layout comprises: providing a first target layout, and performing optical proximity correction on the first target layout to form the mask layout.

24. A reticle layout, comprising:

the first mask layout comprises a plurality of first patterns extending along a first direction, each first pattern comprises a first area and a first area to be corrected, the first area to be corrected is adjacent to the first area, a plurality of grooves are formed in the first pattern boundary of the first area to be corrected, and the grooves are adjacent to the first area.

25. The reticle layout of claim 24, wherein each 4 grooves are located on two sides of 1 first region along the first direction, and the 4 grooves are arranged in a central symmetry, and a center of symmetry of the central symmetry is a center of the first region.

26. The reticle layout of claim 25, wherein each groove has a groove depth in a second direction, and wherein the groove depth is 3% to 15% of the width of the first pattern, and wherein the second direction is perpendicular to the first direction.

27. The reticle layout of claim 26, wherein each of the grooves has a groove width in the first direction, and the groove width ranges from 0.5 nm to 3 nm.

28. A reticle layout, comprising:

the first mask layout comprises: a plurality of first patterns extending along a first direction, the plurality of first patterns including a plurality of first patterns to be corrected, each first pattern to be corrected including a plurality of second regions, a third region, and a second region to be corrected, the second region to be corrected being adjacent to one or both of the second region and the third region, and a length of the second region to be corrected between the second region and the third region in the first direction being a first length; when the first length is below a preset value, the boundary of the first pattern to be corrected in the second area to be corrected is provided with a plurality of correction boundary line segments, in the second area to be corrected, the distance between every two adjacent correction boundary line segments along the second direction is smaller than or equal to the width of the first pattern to be corrected, the distance between every two adjacent correction boundary line segments along the second direction is reduced from the adjacent second area to the adjacent third area, and the first direction and the second direction are mutually perpendicular.

29. The reticle layout of claim 28, wherein the plurality of correction boundary line segments are axisymmetrically arranged, and wherein an axis of symmetry of the axisymmetrically arranged is a center line of the first pattern to be corrected along the first direction.

30. The reticle layout of claim 28, wherein when the first length is below a preset value, there are a number of grooves on a first pattern boundary of a second region to be corrected adjacent to only the second region, and the number of grooves are adjacent to the second region.

31. The reticle layout of claim 28, wherein when the first length is below a preset value, there are a number of grooves on a first pattern boundary of a second pattern to be corrected adjacent to only the third region, and the number of grooves are adjacent to the third region.

32. The reticle layout of claim 28, wherein when the first length is greater than a predetermined value, a plurality of grooves are provided on a first pattern boundary of the second region to be corrected, the plurality of grooves being adjacent to one or both of the second region and the third region.

33. The reticle layout of claim 28, wherein the plurality of first patterns further comprises a plurality of second patterns to be corrected, each second pattern to be corrected comprising a plurality of fourth regions and a third region to be corrected, the third region to be corrected being adjacent to the fourth regions, the third region to be corrected having a plurality of grooves on a boundary of the second pattern to be corrected, the plurality of grooves being adjacent to the fourth regions.