CN117252142A - Design method of photomask layout structure and photomask layout structure - Google Patents
Design method of photomask layout structure and photomask layout structure Download PDFInfo
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- CN117252142A CN117252142A CN202210653558.4A CN202210653558A CN117252142A CN 117252142 A CN117252142 A CN 117252142A CN 202210653558 A CN202210653558 A CN 202210653558A CN 117252142 A CN117252142 A CN 117252142A
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 238000013461 design Methods 0.000 title claims abstract description 15
- 230000003287 optical effect Effects 0.000 claims abstract description 45
- 238000012937 correction Methods 0.000 claims abstract description 41
- 238000012545 processing Methods 0.000 claims abstract description 34
- 230000000694 effects Effects 0.000 claims abstract description 24
- 230000002093 peripheral effect Effects 0.000 claims abstract description 16
- 230000008569 process Effects 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000004590 computer program Methods 0.000 claims description 7
- 238000002834 transmittance Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 11
- 230000007547 defect Effects 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000010894 electron beam technology Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000003550 marker Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
- G03F1/76—Patterning of masks by imaging
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]
Abstract
The embodiment of the disclosure provides a design method of a photomask layout structure and the photomask layout structure, wherein the design method comprises the following steps: acquiring an original layout of a photomask, wherein the original layout comprises at least one first graph, and the first graph comprises a graph area and a peripheral area surrounding the graph area; marking a marking area, wherein orthographic projection of the marking area on the original layout at least covers part of the outline of the first graph; and defining the mark area as an area which is not subjected to optical proximity effect correction processing.
Description
Technical Field
The present disclosure relates to the field of integrated circuits, and more particularly, to a photomask layout structure and a method for designing the same.
Background
With the continuous development of semiconductor technology, the design size of semiconductor devices is continuously reduced, and the design size is more and more close to the limit of a photoetching imaging system, so that optical proximity effect (OPE, optical Proximity Effect) is easily generated, the quality of patterns is affected, and defects such as corner rounding, line tail shortening, line width increasing or shrinking and the like occur. Therefore, how to optimize the quality defect of the integrated circuit pattern caused by the optical proximity effect is a problem to be solved.
Disclosure of Invention
The embodiment of the disclosure provides a design method of a photomask layout structure, which comprises the following steps: acquiring an original layout of a photomask, wherein the original layout comprises at least one first graph, and the first graph comprises a graph area and a peripheral area surrounding the graph area; marking a marking area, wherein orthographic projection of the marking area on the original layout at least covers part of the outline of the first graph; and defining the mark area as an area which is not subjected to optical proximity effect correction processing.
In some embodiments, after marking the marked area, the method further comprises: and performing optical proximity effect correction processing on a part, which is not overlapped with the mark region, of the first graph.
In some embodiments, marking a marking area, an orthographic projection of the marking area on the original layout covers at least a part of an outer contour of the first graph, including: providing a reference layer, wherein the reference layer comprises a reference graph, and defining the marking area according to the reference graph.
In some embodiments, a reference layer is provided, the reference layer including a reference pattern from which the marking area is defined, including: providing a first reference layer, wherein the first reference layer comprises a first reference graph, and the orthographic projection of the first reference graph on the original layout surrounds the graph area and is surrounded by the outline of the first graph; providing a second reference layer, wherein the second reference layer comprises a second reference graph, and the orthographic projection of the second reference graph on the original layout surrounds the first graph; and defining a part, which is not overlapped with the area surrounded by the orthographic projection of the first reference graph on the original layout and the area surrounded by the orthographic projection of the second reference graph on the original layout, as a marked area.
In some embodiments, a reference layer is provided, the reference layer including a reference pattern from which the marking area is defined, including: providing a first reference layer, wherein the first reference layer comprises a first reference graph, and the orthographic projection of the first reference graph on the original layout surrounds the graph area and is surrounded by the outline of the first graph; and defining a part, which is not overlapped with the area surrounded by the orthographic projection of the first graph and the first reference graph on the original layout, as a marked area.
In some embodiments, performing optical proximity effect correction processing on a portion of the first pattern that does not overlap the mark region includes: defining a first graph as a first operation object; defining orthographic projection of the marking area on the original layout as a second operation object; subtracting the overlapped part of the first operation object and the second operation object from the first operation object by using Boolean operation to obtain a third operation object; the third operand is defined as an area where optical proximity correction processing is required.
The embodiment of the disclosure also provides a photomask layout structure, which comprises: an original layout, wherein the original layout comprises at least one first graph, and the first graph comprises a graph area and a peripheral area surrounding the graph area; the reference layer comprises a reference graph, the reference graph defines a marking area, and orthographic projection of the marking area on the original layout at least covers part of the outline of the first graph; wherein the mark region is a region where no optical proximity correction process is performed.
In some embodiments, the transmittance of the graphic region and the peripheral region is different.
In some embodiments, the reference layers include a first reference layer and a second reference layer; the first reference layer comprises a first reference pattern, and orthographic projection of the first reference pattern on the original layout surrounds the pattern area and is surrounded by the outline of the first pattern; the second reference layer comprises a second reference pattern, and orthographic projection of the second reference pattern on the original layout surrounds the first pattern; and a part, which is not overlapped with the area surrounded by the orthographic projection of the first reference graph on the original layout, and the area surrounded by the orthographic projection of the second reference graph on the original layout is a marking area.
In some embodiments, the first reference pattern and the first pattern have the same shape, and the distance between the outline of the orthographic projection of the first reference pattern on the original layout and the outline of the first pattern is equal everywhere; the second reference graph and the first graph have the same shape, and the distance between the outline of the orthographic projection of the second reference graph on the original layout and the outline of the first graph is equal everywhere.
In some embodiments, the distance between the outline of the orthographic projection of the second reference pattern on the original layout and the outer outline of the first pattern is 5nm-20nm; the distance between the outline of the orthographic projection of the first reference pattern on the original layout and the outline of the orthographic projection of the second reference pattern on the original layout is 50nm-150nm.
In some embodiments, the reference layer comprises a first reference layer comprising a first reference pattern, an orthographic projection of the first reference pattern on the original layout surrounding the pattern area and being surrounded by an outer contour of the first pattern; and defining a part, which is not overlapped with the area surrounded by the orthographic projection of the first graph and the first reference graph on the original layout, as a marked area.
In some embodiments, the first reference pattern and the first pattern have the same shape, and the distance between the outline of the orthographic projection of the first reference pattern on the original layout and the outline of the first pattern is equal everywhere; the distance between the outline of the orthographic projection of the first reference pattern on the original layout and the outline of the first pattern is 70nm-130nm.
The embodiment of the disclosure also provides a semiconductor structure, which comprises a semiconductor structure obtained by using the photomask prepared by the photomask layout structure.
The embodiment of the disclosure also provides a design device of the integrated circuit, which comprises: at least one memory and at least one processor, and a computer program stored on the memory and capable of running on the processor, the processor for invoking the computer program to perform the method of any of the above.
The embodiment of the disclosure provides a design method of a photomask layout structure and the photomask layout structure, wherein the design method comprises the following steps: acquiring an original layout of a photomask, wherein the original layout comprises at least one first graph, and the first graph comprises a graph area and a peripheral area surrounding the graph area; marking a marking area, wherein orthographic projection of the marking area on the original layout at least covers part of the outline of the first graph; and defining the mark area as an area which is not subjected to optical proximity effect correction processing. In the embodiment of the disclosure, in the process of performing optical proximity effect correction processing on the original layout, a marking area covering part of the outer contour of the first graph is added, and the marking area is limited without performing optical proximity effect correction processing. Therefore, the problem of uneven edges of the partial outer contour of the first graph after the optical proximity effect correction processing is avoided. Meanwhile, the contour of the first pattern is not required to be flattened manually, and the optical proximity effect correction operation time, the production period and the error rate are reduced.
The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the disclosure will be apparent from the description and drawings, and from the claims.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.
FIG. 1 is a block flow diagram of a method for designing a photomask layout structure according to an embodiment of the present disclosure;
fig. 2a to 2d are schematic layout views of each step in a method for designing a photomask layout structure according to an embodiment of the present disclosure, where the I diagram is a schematic structural diagram, and the II diagram is a schematic plan view;
fig. 3a to 3b are schematic views of steps in another method for designing a photomask layout structure according to an embodiment of the present disclosure, where the I-diagram is a schematic structural diagram and the II-diagram is a schematic plan view;
FIGS. 4a to 4c are schematic views illustrating steps in another method for designing a photomask layout structure according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a design apparatus according to an embodiment of the present disclosure.
Reference numerals:
21-original layout; 22-a first graphic; 221-a graphic area; 222-peripheral area; 2221-outer contour of the first graphic; 23-a marker region; 24-reference layer; 241-a first reference layer; 242-a second reference layer; 25-reference pattern; 251-a first reference pattern; 2511—an outline of the orthographic projection of the first reference pattern on the original layout; 252-a second reference pattern; 2521-the outline of the orthographic projection of the second reference pattern on the original layout;
51-designing a device; 52-a memory; 53-a computer program; 54-processor.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without one or more of these details. In other instances, well-known features have not been described in detail so as not to obscure the invention; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.
In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present.
Spatially relative terms, such as "under … …," "under … …," "below," "under … …," "above … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
The industry typically uses optical proximity correction (OPC, optical Proximity Correction) to correct the original layout pattern to reduce the lithography defects caused by the optical proximity effect. However, in the related art, after the original layout is corrected using the optical proximity correction, the corrected original layout pattern still has quality defects, and at this time, manual (manual) optimization of the defects is often required, which increases time cost and error rate.
Based on this, the embodiment of the disclosure provides a method for designing a photomask layout structure, referring specifically to fig. 1, as shown in the figure, the method includes the following steps:
step 101: acquiring an original layout of a photomask, wherein the original layout comprises at least one first graph, and the first graph comprises a graph area and a peripheral area surrounding the graph area;
step 102: marking a marking area, wherein orthographic projection of the marking area on the original layout at least covers part of the outline of the first graph;
step 103: the mark area is defined as an area where no optical proximity correction process is performed.
In the embodiment of the disclosure, in the process of performing optical proximity effect correction processing on the original layout, a marking area covering part of the outer contour of the first graph is added, and the marking area is limited without performing optical proximity effect correction processing. Therefore, the problem of uneven edges of the partial outer contour of the first graph after the optical proximity effect correction processing is avoided. Meanwhile, the contour of the first pattern is not required to be flattened manually, and the optical proximity effect correction operation time, the production period and the error rate are reduced.
Fig. 2a to 2d are schematic layout views of each step in a method for designing a photomask layout structure according to an embodiment of the present disclosure, where the I-diagram is a schematic structural diagram, and the II-diagram is a schematic plan view; the method for designing a photomask layout structure according to the embodiments of the present disclosure is described in further detail below with reference to fig. 2a to 2 d. In describing the embodiments of the present disclosure, the schematic drawings are not to scale in order to facilitate explanation, and the schematic drawings are merely examples, which should not limit the scope of protection of the present application.
First, referring to fig. 2a, step 101 is performed to obtain an original layout 21 of a photomask, wherein the original layout 21 includes at least one first pattern 22, and the first pattern 22 includes a pattern area 221 and a peripheral area 222 surrounding the pattern area 221. Here, the original layout 21 may be, for example, an original reticle layout file, such as GDS data. The original layout may be used as a mask and the first pattern 22 may be, for example, a Mark (Mark) on the mask, including but not limited to an alignment Mark (alignment Mark), an overlay Mark (overlay Mark). In other embodiments, the first pattern 22 may be a scribe line pattern or a Chip boundary (Chip boundary).
In some embodiments, the transmittance of the graphic region and the peripheral region is different. In practical operation, taking Positive PR (PPR)/negative tone (negative tone develop, NTD) as an example, the pattern region may be an opaque region, and the peripheral region may be a transparent region, for example. The stage of the exposure process may be, for example, a wafer level electron beam exposure system (MEBES, manufacturing Electron Beam Engraving System).
Next, referring to fig. 2b to 2d, step 102 is performed to mark the mark area 23, and the orthographic projection of the mark area 23 on the original layout 21 covers at least a part of the outer contour of the first pattern 22.
In some embodiments, referring to fig. 2b-2d, a mark region 23 is marked, and an orthographic projection of the mark region 23 on the original layout 21 covers at least a part of an outer contour of the first pattern 22, including: a reference layer 24 is provided, which comprises a reference pattern 25, from which reference pattern 25 a marking area 23 is defined.
In some embodiments, referring to fig. 2b-2d, a reference layer 24 is provided, the reference layer 24 including a reference pattern 25, a mark region 23 defined according to the reference pattern 25, comprising: providing a first reference layer 241, wherein the first reference layer 241 comprises a first reference pattern 251, wherein the orthographic projection of the first reference pattern 251 on the original layout 21 surrounds the pattern area 221 and is surrounded by the outer contour 2221 of the first pattern; providing a second reference layer 242, the second reference layer 242 comprising a second reference pattern 252, the orthographic projection of the second reference pattern 252 onto the original layout 21 surrounding the first pattern 22; a portion where the region surrounded by the orthographic projection of the first reference pattern 251 on the original layout 21 does not overlap with the region surrounded by the orthographic projection of the second reference pattern 252 on the original layout 21 is defined as a mark region 23.
Specifically, referring to fig. 2b, first, a first reference layer 241 is provided, where the first reference layer 241 includes a first reference pattern 251, and an orthographic projection of the first reference pattern 251 on the original layout 21 encloses the pattern area 221 and is enclosed by an outer contour 2221 of the first pattern.
In some embodiments, the first reference pattern 241 and the first pattern 22 are identical in shape, with the distance between the orthographic outline 2511 of the first reference pattern on the original layout and the outer outline 2221 of the first pattern being equal everywhere. In a specific embodiment, the outline 2511 of the orthographic projection of the first reference pattern on the original layout and the outline 2221 of the first pattern may be rectangular, and in actual operation, the symmetry axes of the two rectangles may coincide. In other embodiments, the outline 2511 of the orthographic projection of the first reference pattern on the original layout and the outer outline 2221 of the first pattern may be identical circles, and in actual operation, the two circles may form a concentric circle structure.
Next, referring to fig. 2c, a second reference layer 242 is provided, the second reference layer 242 comprising a second reference pattern 252, the orthographic projection of the second reference pattern 252 onto the original layout 21 surrounding the first pattern 22.
In some embodiments, the second reference pattern 242 and the first pattern 22 are the same shape, and the distance between the outline 2521 of the orthographic projection of the second reference pattern on the original layout and the outline 2221 of the first pattern is equal everywhere. In a specific embodiment, the outline 2521 of the orthographic projection of the second reference pattern on the original layout and the outline 2221 of the first pattern may be rectangular, and in actual operation, the symmetry axes of the two rectangles may coincide. In other embodiments, the outline 2521 of the orthographic projection of the second reference pattern on the original layout and the outline 2221 of the first pattern may be identical circles, and in actual operation, the two circles may form a concentric circle structure.
The first reference pattern and the second reference pattern adopt relatively regular patterns, so that the reference pattern layer can be conveniently identified and processed, the distance between the first reference pattern and the first pattern and the distance between the second reference pattern and the first pattern can be conveniently controlled and adjusted, and meanwhile, the complexity of subsequent Boolean (Boolean) operation is reduced.
In some embodiments, the distance between the outline 2521 of the orthographic projection of the second reference feature on the original layout and the outer outline 2221 of the first feature is 5nm-20nm. Illustratively, the distance between the outline 2521 of the orthographic projection of the second reference pattern on the original layout and the outer outline 2221 of the first pattern may be 7nm-15nm, such as 8nm, 10nm or 13nm. The appropriate distance facilitates the identification and processing of the reference layer, as well as the definition of the marking area.
In some embodiments, the distance between the orthographic profile 2511 of the first reference pattern on the original layout and the orthographic profile 2521 of the second reference pattern on the original layout is 50nm-150nm. Illustratively, the distance between the orthographic profile 2511 of the first reference pattern on the original layout and the orthographic profile 2521 of the second reference pattern on the original layout may be 70nm-130nm, such as 78nm, 100nm or 128nm. Too large a distance may affect Optical Proximity Correction (OPC) of the pattern areas within the first pattern and too small a distance may increase difficulty in reference layer identification and processing.
Then, referring to fig. 2d, a portion where the region surrounded by the orthographic projection of the first reference pattern 251 on the original layout 21 does not overlap with the region surrounded by the orthographic projection of the second reference pattern 252 on the original layout 21 is defined as a mark region 23.
In the above scheme, by setting the first reference layer and the second reference layer, the area surrounded by the orthographic projection of the first reference pattern 251 on the original layout 21 and the area surrounded by the orthographic projection of the second reference pattern 252 on the original layout 21 are defined as the mark area, so that the uneven area of the outer contour of the first pattern is avoided due to unnecessary OPC processing. It should be understood that the scheme of defining the mark area is not limited thereto, and in other embodiments, referring to fig. 3a to 3b, a reference layer is provided, the reference layer including a reference pattern, the mark area being defined according to the reference pattern, including: providing a first reference layer 241, wherein the first reference layer 241 comprises a first reference pattern 251, wherein the orthographic projection of the first reference pattern 241 on the original layout 21 surrounds the pattern area 221 and is surrounded by the outer contour 2221 of the first pattern; the portion of the first pattern 22 that does not overlap with the area surrounded by the orthographic projection of the first reference pattern 251 on the original layout 21 is defined as a mark area 23.
Specifically, referring to fig. 3a, first, a first reference layer 241 is provided, where the first reference layer 241 includes a first reference pattern 251, and an orthographic projection of the first reference pattern 241 on the original layout 21 encloses the pattern area 221 and is enclosed by an outer contour 2221 of the first pattern.
In some embodiments, referring to FIG. 3a, the first reference pattern 241 and the first pattern 22 are identical in shape, with the distance between the orthographic outline 2511 of the first reference pattern 241 and the outer outline 2221 of the first pattern being equal throughout the original layout 21. In a specific embodiment, the outline 2511 of the orthographic projection of the first reference pattern 241 on the original layout 21 and the outer outline 2221 of the first pattern may be rectangular, and in actual operation, the symmetry axes of the two rectangles may coincide. In other embodiments, the outline 2511 of the orthographic projection of the first reference pattern 241 on the original layout 21 and the outer outline 2221 of the first pattern may be identical circles, and in actual practice, the two circles may form a concentric circle structure.
In some embodiments, referring to FIG. 3a, the distance between the orthographic outline 2511 of the first reference pattern on the original layout and the outer outline 2221 of the first pattern is 70nm-130nm. Illustratively, the distance between the orthographic outline 2511 of the first reference pattern on the original layout and the outer outline 2221 of the first pattern may be 80nm-120nm, such as 85nm, 100nm or 112nm. Too large a distance may affect Optical Proximity Correction (OPC) of the pattern areas within the first pattern and too small a distance may increase difficulty in reference layer identification and processing.
Next, referring to fig. 3b, a portion of the first pattern 22 that does not overlap with the area surrounded by the orthographic projection of the first reference pattern 251 on the original layout 21 is defined as a mark area 23.
Therefore, only a single reference layer is arranged to mark the marking area, and the implementation method for defining the marking area is simplified. However, the method is not limited thereto, and in actual operation, a plurality of reference layers may be provided to mark the marking area, so as to improve the accuracy of the marking area.
It should be understood that in the above embodiment, the front projection of the mark area on the original layout completely covers the outer contour of the first pattern, so as to avoid uneven areas on the boundary of the first pattern after OPC processing. In other embodiments, the orthographic projection of the mark region onto the original layout covers a portion of the outer contour of the first graphic. Thus, the region where the optical proximity correction process is not performed is defined in a targeted manner, and the degree of freedom and operability can be increased.
Then, step 103 is performed to define the mark area as an area where the optical proximity correction process is not performed.
In some embodiments, after marking the marked area, the method further comprises: an optical proximity effect correction (OPC) process is performed on a portion of the first pattern which does not overlap with the mark region. Thus, OPC processing can be avoided on the outer contour of the first pattern, the expected pattern, namely the first pattern with a flat boundary, is obtained, and the outer contour of the first pattern is prevented from being flattened manually.
In some embodiments, referring to fig. 4 a-4 c, performing optical proximity correction processing on a portion of the first pattern that does not overlap with the mark region, includes: defining a first graph 22 as a first operand A; defining the orthographic projection of the mark region 23 on the original layout 21 as a second operation object B; a Boolean (boolean) operation is adopted, and a part of the first operation object A overlapped with the second operation object B is subtracted from the first operation object A to obtain a third operation object C; the third operand C is defined as a region where optical proximity correction processing is required.
Specifically, referring first to fig. 4a, a first graph 22 is defined as a first operand a.
Next, referring to fig. 4B, an orthographic projection of the mark region 23 on the original layout 21 is defined as a second operand B.
Next, referring to fig. 4C, a boolean (boolean) operation is adopted to subtract the overlapping portion of the first operand a and the second operand B from the first operand a, so as to obtain a third operand C; the third operand C is defined as a region where optical proximity correction processing is required. Here, boolean operations include, but are not limited to, union (Union), intersection (Intersection), difference (sub), cut (Cut), refine (Split), split (Split), remove internal (Remove instrument), remove external (Remove out), or a combination thereof.
The embodiment of the disclosure also provides a photomask layout structure, referring to fig. 2d, the photomask layout structure includes: an original layout 21, the original layout 21 comprising at least one first graphic 22, the first graphic 22 comprising a graphic area 221 and a peripheral area 222 surrounding the graphic area; referring to layer 24, reference layer 24 includes reference pattern 25, reference pattern 25 defining a mark region 23, and the orthographic projection of mark region 23 on original layout 21 covers at least part of outer contour 2221 of the first pattern; the mark region 23 is a region where Optical Proximity Correction (OPC) is not performed.
Here, the original layout 21 may be, for example, an original reticle layout file, such as a GDS layout. The original layout may be used as a mask and the first pattern 22 may be, for example, a Mark (Mark) on the mask, including but not limited to an alignment Mark (alignment Mark), an overlay Mark (overlay Mark). In other embodiments, the first pattern 22 may be a scribe line pattern or a Chip boundary (Chip boundary).
In some embodiments, the transmittance of the graphic region 221 and the peripheral region 222 is different. In practical operation, taking Positive PR (PPR)/negative tone (negative tone develop, NTD) as an example, the pattern region may be an opaque region, and the peripheral region may be a transparent region, for example. The stage of the exposure process may be, for example, a wafer level electron beam exposure system (MEBES, manufacturing Electron Beam Engraving System).
In some embodiments, referring to fig. 2d, reference layer 24 includes a first reference layer 241 and a second reference layer 242; the first reference layer 241 includes a first reference pattern 251, and an orthographic projection of the first reference pattern 251 on the original layout 21 encloses the pattern area 221 and is enclosed by an outer contour 2221 of the first pattern; the second reference layer 242 includes a second reference pattern 252, and an orthographic projection of the second reference pattern 252 on the original layout 21 encloses the first pattern 22; the portion where the region surrounded by the orthographic projection of the first reference pattern 251 on the original layout 21 does not overlap with the region surrounded by the orthographic projection of the second reference pattern 252 on the original layout 21 is the mark region 23. In this way, by providing the first reference layer and the second reference layer, a portion where the area surrounded by the orthographic projection of the first reference pattern 251 on the original layout 21 and the area surrounded by the orthographic projection of the second reference pattern 252 on the original layout 21 do not overlap is defined as a mark area, thereby avoiding uneven areas in the outer contour of the first pattern from being subjected to unnecessary OPC processing.
In some embodiments, the first reference pattern 241 and the first pattern 22 are identical in shape, with the distance between the orthographic outline 2511 of the first reference pattern 241 and the outer outline 2221 of the first pattern being equal everywhere on the original layout 21; the second reference pattern 242 is identical in shape to the first pattern 22, and the distance between the orthographic outline 2521 of the second reference pattern on the original layout and the outer outline 2221 of the first pattern is equal everywhere. In a specific embodiment, the outline 2511 of the orthographic projection of the first reference pattern 241 on the original layout 21 and the outer outline 2221 of the first pattern may be rectangular, and in actual operation, the symmetry axes of the two rectangles may coincide. The outline 2521 of the orthographic projection of the second reference pattern 242 on the original layout and the outline 2221 of the first pattern may be rectangular, and in actual operation, symmetry axes of the two rectangles may coincide. In other embodiments, the outline 2511 of the orthographic projection of the first reference pattern 241 on the original layout 21 and the outer outline 2221 of the first pattern may, in actual operation, form a concentric circle structure. The outline 2521 of the orthographic projection of the second reference pattern on the original layout and the outline 2221 of the first pattern may be both circles, and in actual operation, the two circles may form a concentric circle structure.
The first reference pattern and the second reference pattern adopt relatively regular patterns, so that the reference pattern layer can be conveniently identified and processed, the distance between the first reference pattern and the first pattern and the distance between the second reference pattern and the first pattern can be conveniently controlled and adjusted, and meanwhile, the complexity of subsequent Boolean (Boolean) operation is reduced.
In some embodiments, the distance between the outline 2521 of the orthographic projection of the second reference feature on the original layout and the outer outline 2221 of the first feature is 5nm-20nm. Illustratively, the distance between the outline 2521 of the orthographic projection of the second reference pattern on the original layout and the outer outline 2221 of the first pattern may be 7nm-15nm, such as 8nm, 10nm or 13nm. The appropriate distance facilitates the identification and processing of the reference layer, as well as the definition of the marking area.
In some embodiments, the distance between the orthographic profile 2511 of the first reference pattern on the original layout and the orthographic profile 2511 of the second reference pattern on the original layout is 50nm-150nm. Illustratively, the distance between the orthographic profile 2511 of the first reference pattern on the original layout and the orthographic profile 2511 of the second reference pattern on the original layout may be 70nm-130nm, such as 78nm, 100nm or 128nm. Too large a distance may affect Optical Proximity Correction (OPC) of the pattern areas within the first pattern and too small a distance may increase difficulty in reference layer identification and processing.
In some embodiments, referring to FIG. 3b, reference layer 24 includes a first reference layer 241, first reference layer 25 includes a first reference pattern 251, an orthographic projection of first reference pattern 251 on the original layout encloses pattern region 221, and is enclosed by an outer contour 2221 of the first pattern; the portion of the first pattern 22 that does not overlap with the area surrounded by the orthographic projection of the first reference pattern 251 on the original layout 21 is defined as a mark area 23. Therefore, only a single reference layer is arranged to mark the marking area, and the implementation method for defining the marking area is simplified. However, the method is not limited thereto, and in actual operation, a plurality of reference layers may be provided to mark the marking area, so as to improve the accuracy of the marking area.
In some embodiments, the first reference pattern 241 and the first pattern 22 are identical in shape, and the distance between the outline of the orthographic projection of the first reference pattern 241 on the original layout 21 and the outer outline 2221 of the first pattern is everywhere equal. In a specific embodiment, the outline 2511 of the orthographic projection of the first reference pattern 241 on the original layout 21 and the outer outline 2221 of the first pattern may be rectangular, and in actual operation, the symmetry axes of the two rectangles may coincide. In other embodiments, the outline 2521 of the orthographic projection of the second reference pattern on the original layout and the outline 2221 of the first pattern may be identical circles, and in actual operation, the two circles may form a concentric circle structure. The first reference pattern 241 and the first pattern 22 have the same shape, which facilitates the identification and processing of the reference pattern layer, and also facilitates the control and adjustment of the distance between the first reference pattern and the first pattern, while reducing the complexity of the subsequent boolean (boolean) operation.
In some embodiments, the distance between the orthographic outline 2511 of the first reference pattern on the original layout and the outer outline 2221 of the first pattern is 70nm-130nm. Illustratively, the distance between the orthographic outline 2511 of the first reference pattern on the original layout and the outer outline 2221 of the first pattern may be 80nm-120nm, such as 85nm, 100nm or 112nm. Too large a distance may affect Optical Proximity Correction (OPC) of the pattern areas within the first pattern and too small a distance may increase difficulty in reference layer identification and processing.
In summary, in the embodiment of the disclosure, in the process of performing optical proximity correction processing on the original layout, the marking area covering part of the outer contour of the first pattern is increased, and the marking area is defined without performing optical proximity correction processing. Therefore, the problem of uneven edges of part of the outer contour of the first graph after the optical proximity effect correction processing is avoided. Meanwhile, the outline of the first pattern is not required to be flattened manually, and the optical proximity effect correction operation time, the production period and the error rate are reduced.
The embodiment of the disclosure also provides a semiconductor structure, which comprises a semiconductor structure obtained by using the photomask prepared by the photomask layout structure. The photomask layout structure provided by the disclosure adds the reference layer to define the mark area, and the mark area is defined without optical proximity effect correction processing. The occurrence of an edge uneven area due to the boundary of the first pattern in the photomask layout structure is avoided, the uneven area is easy to be an area generating defects (defects) in the subsequent process, for example, tiny lines are formed on a wafer, so that bridging is caused, reliability is affected, and the like. Thus, the optimized photomask layout structure is used for manufacturing the photomask, and the photomask can be used for subsequent process alignment, measurement, exposure and the like. The structural performance and yield of the semiconductor prepared by the method are improved.
The disclosed embodiment also provides a design apparatus 51 of an integrated circuit, referring to fig. 5, the design apparatus includes: at least one memory 52 and at least one processor 54, and a computer program 53 stored on the memory 52 and capable of running on the processor 54, the processor 54 for invoking the computer program 53 to perform the method of any of the above, such as: acquiring an original layout of a photomask, wherein the original layout comprises at least one first graph, and the first graph comprises a graph area and a peripheral area surrounding the graph area; marking a marking area, wherein orthographic projection of the marking area on the original layout at least covers part of the outline of the first graph; the mark area is defined as an area where no optical proximity correction process is performed.
The technical features of the embodiments described in the present invention may be combined arbitrarily without any conflict. Those skilled in the art can change the order of the steps of the forming method without departing from the scope of the disclosure, and in the embodiments of the disclosure, some steps may be performed simultaneously or may be performed sequentially without conflict.
The foregoing description of the preferred embodiments of the present disclosure is provided for the purpose of illustration only, and is not intended to limit the scope of the present disclosure, as any modification, equivalent replacement, improvement or the like that comes within the spirit and principles of the present disclosure should be included in the scope of the present disclosure.
Claims (15)
1. The design method of the photomask layout structure is characterized by comprising the following steps of:
acquiring an original layout of a photomask, wherein the original layout comprises at least one first graph, and the first graph comprises a graph area and a peripheral area surrounding the graph area;
marking a marking area, wherein orthographic projection of the marking area on the original layout at least covers part of the outline of the first graph;
and defining the mark area as an area which is not subjected to optical proximity effect correction processing.
2. The method of claim 1, wherein after marking the marked area, the method further comprises:
and performing optical proximity effect correction processing on a part, which is not overlapped with the mark region, of the first graph.
3. The method according to claim 1, wherein marking a marking area, an orthographic projection of the marking area on the original layout covers at least a part of an outer contour of the first graphic, comprises:
providing a reference layer, wherein the reference layer comprises a reference graph, and defining the marking area according to the reference graph.
4. A method according to claim 3, wherein providing a reference layer comprising a reference pattern from which the marking area is defined comprises:
providing a first reference layer, wherein the first reference layer comprises a first reference graph, and the orthographic projection of the first reference graph on the original layout surrounds the graph area and is surrounded by the outline of the first graph;
providing a second reference layer, wherein the second reference layer comprises a second reference graph, and the orthographic projection of the second reference graph on the original layout surrounds the first graph;
and defining a part, which is not overlapped with the area surrounded by the orthographic projection of the first reference graph on the original layout and the area surrounded by the orthographic projection of the second reference graph on the original layout, as a marked area.
5. A method according to claim 3, wherein providing a reference layer comprising a reference pattern from which the marking area is defined comprises:
providing a first reference layer, wherein the first reference layer comprises a first reference graph, and the orthographic projection of the first reference graph on the original layout surrounds the graph area and is surrounded by the outline of the first graph;
and defining a part, which is not overlapped with the area surrounded by the orthographic projection of the first graph and the first reference graph on the original layout, as a marked area.
6. The method according to claim 2, wherein performing optical proximity effect correction processing on a portion of the first pattern that does not overlap the mark region includes:
defining a first graph as a first operation object;
defining orthographic projection of the marking area on the original layout as a second operation object;
subtracting the overlapped part of the first operation object and the second operation object from the first operation object by using Boolean operation to obtain a third operation object;
the third operand is defined as an area where optical proximity correction processing is required.
7. A photomask layout structure, comprising:
an original layout, wherein the original layout comprises at least one first graph, and the first graph comprises a graph area and a peripheral area surrounding the graph area;
the reference layer comprises a reference graph, the reference graph defines a marking area, and orthographic projection of the marking area on the original layout at least covers part of the outline of the first graph; wherein the mark region is a region where no optical proximity correction process is performed.
8. The photomask layout structure of claim 7, wherein,
the transmittance of the graphic region and the peripheral region is different.
9. The photomask layout structure of claim 7, wherein,
the reference layers comprise a first reference layer and a second reference layer; wherein,
the first reference layer comprises a first reference pattern, and orthographic projection of the first reference pattern on the original layout surrounds the pattern area and is surrounded by the outline of the first pattern;
the second reference layer comprises a second reference pattern, and orthographic projection of the second reference pattern on the original layout surrounds the first pattern;
and a part, which is not overlapped with the area surrounded by the orthographic projection of the first reference graph on the original layout, and the area surrounded by the orthographic projection of the second reference graph on the original layout is a marking area.
10. The photomask layout structure of claim 9, wherein,
the first reference graph and the first graph have the same shape, and the distance between the outline of orthographic projection of the first reference graph on the original layout and the outline of the first graph is equal everywhere;
the second reference graph and the first graph have the same shape, and the distance between the outline of the orthographic projection of the second reference graph on the original layout and the outline of the first graph is equal everywhere.
11. The photomask layout structure of claim 10, wherein,
the distance between the outline of the orthographic projection of the second reference pattern on the original layout and the outline of the first pattern is 5nm-20nm;
the distance between the outline of the orthographic projection of the first reference pattern on the original layout and the outline of the orthographic projection of the second reference pattern on the original layout is 50nm-150nm.
12. The photomask layout structure of claim 7, wherein,
the reference layer comprises a first reference layer, the first reference layer comprises a first reference pattern, and the orthographic projection of the first reference pattern on the original layout surrounds the pattern area and is surrounded by the outer contour of the first pattern;
and defining a part, which is not overlapped with the area surrounded by the orthographic projection of the first graph and the first reference graph on the original layout, as a marked area.
13. The photomask layout structure of claim 12 wherein,
the first reference graph and the first graph have the same shape, and the distance between the outline of orthographic projection of the first reference graph on the original layout and the outline of the first graph is equal everywhere;
the distance between the outline of the orthographic projection of the first reference pattern on the original layout and the outline of the first pattern is 70nm-130nm.
14. A semiconductor structure comprising a semiconductor structure obtained using a photomask prepared by the photomask layout structure of any of claims 7-13.
15. An integrated circuit design apparatus, comprising:
at least one memory and at least one processor, and a computer program stored on the memory and capable of running on the processor,
the processor is configured to invoke the computer program to perform the method of any of claims 1-6.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210653558.4A CN117252142A (en) | 2022-06-09 | 2022-06-09 | Design method of photomask layout structure and photomask layout structure |
| PCT/CN2022/101510 WO2023236271A1 (en) | 2022-06-09 | 2022-06-27 | Photomask layout structure design method and photomask layout structure |
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| CN202210653558.4A CN117252142A (en) | 2022-06-09 | 2022-06-09 | Design method of photomask layout structure and photomask layout structure |
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| JP2005062601A (en) * | 2003-08-18 | 2005-03-10 | Matsushita Electric Ind Co Ltd | Verification and correction method for photomask pattern |
| CN101498893B (en) * | 2008-01-31 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | OPC method for mask preparation course in semiconductor manufacturing process |
| CN102411259A (en) * | 2011-11-28 | 2012-04-11 | 上海华力微电子有限公司 | Method and device for performing optical proximity correction on photomask design layout |
| CN103744267B (en) * | 2013-11-28 | 2015-07-08 | 上海华力微电子有限公司 | Layout design photoetching technology friendliness detection method based on regular figure filtering |
| KR102343850B1 (en) * | 2015-05-06 | 2021-12-28 | 삼성전자주식회사 | Method of producing mask with using common bias value in optical proximity correction |
| CN109270785A (en) * | 2018-08-15 | 2019-01-25 | 上海华力集成电路制造有限公司 | Well layer lithography layout, its forming method and its Optical Proximity Correction processing method |
| CN112241102A (en) * | 2019-07-19 | 2021-01-19 | 中芯国际集成电路制造(上海)有限公司 | Optical proximity correction, photomask manufacturing and imaging method |
| CN113517180B (en) * | 2020-04-10 | 2023-08-18 | 中芯国际集成电路制造(上海)有限公司 | Mask layout correction method and mask layout |
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