CN113517177A - Manufacturing method of electron beam lithography auxiliary process - Google Patents
Manufacturing method of electron beam lithography auxiliary process Download PDFInfo
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- CN113517177A CN113517177A CN202110466453.3A CN202110466453A CN113517177A CN 113517177 A CN113517177 A CN 113517177A CN 202110466453 A CN202110466453 A CN 202110466453A CN 113517177 A CN113517177 A CN 113517177A
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- 238000000034 method Methods 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 238000000609 electron-beam lithography Methods 0.000 title claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 48
- 239000002184 metal Substances 0.000 claims abstract description 38
- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 238000003475 lamination Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000010894 electron beam technology Methods 0.000 claims abstract description 5
- 239000010931 gold Substances 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008020 evaporation Effects 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 238000004140 cleaning Methods 0.000 claims 1
- 238000001465 metallisation Methods 0.000 abstract description 5
- 238000001259 photo etching Methods 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000635 electron micrograph Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001883 metal evaporation Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0277—Electrolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
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Abstract
The invention discloses a manufacturing method of an electron beam lithography auxiliary process, which is to form a lamination of a first photoresist layer and a second photoresist layer on a semiconductor substrate, carry out electron beam exposure and development on the photoresist lamination to obtain a T-shaped pattern and auxiliary patterns positioned at two sides of the T-shaped pattern, wherein the exposure depth of the T-shaped pattern is the thickness of the first photoresist layer and the second photoresist layer, the exposure depth of the auxiliary patterns is the thickness of the second photoresist layer, and then deposit metal and strip the photoresist to obtain T-shaped gate metal. According to the invention, through the arrangement of the auxiliary pattern, the deformation amount of the light resistor around the T-shaped pattern in the metal deposition process is reduced, the influence on the T-shaped gate shape caused by the deformation of the light resistor is reduced, and the stability of the T-shaped gate metal shape is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of an electron beam lithography auxiliary process.
Background
In the process of manufacturing a T-shaped gate of a semiconductor device, two layers of light resistors are generally adopted to achieve different photoetching areas so as to obtain a T-shaped gate pattern, then metal is deposited to form a T-shaped gate metal structure in the T-shaped gate pattern, and then the light resistors are stripped. However, during the metal deposition process, the photoresist deforms due to the stress effect, so that the shape of the T-shaped gate pattern changes, which causes the shape of the finally deposited metal to be very unstable, and the finally deposited metal is prone to collapse after being stripped, thereby affecting the performance and production yield of the final device.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a manufacturing method of an electron beam lithography auxiliary process.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
the invention relates to a manufacturing method of an electron beam lithography auxiliary process, which comprises the following steps:
1) forming a light resistance lamination layer on a semiconductor substrate, wherein the light resistance lamination layer comprises a first light resistance layer and a second light resistance layer which are formed in sequence;
2) carrying out electron beam exposure and development on the light resistance lamination to obtain a T-shaped graph and auxiliary graphs positioned on two sides of the T-shaped graph, wherein the exposure depth of the T-shaped graph is the thickness of the first light resistance layer and the second light resistance layer, and the exposure depth of the auxiliary graphs is the thickness of the second light resistance layer;
3) depositing metal, wherein T-shaped gate metal which is in contact with the semiconductor substrate is formed in the T-shaped pattern, and auxiliary metal which is not in contact with the semiconductor substrate is formed in the auxiliary pattern;
4) and removing the photoresist lamination layer and remaining the T-shaped gate metal.
Optionally, when the T-shaped pattern is formed, calculating an exposure dose of the first photoresist layer as a first exposure dose, calculating an exposure dose of the second photoresist layer as a second exposure dose, exposing the photoresist lamination by using the first exposure dose and the second exposure dose, obtaining a window of a line width of the gate root on the first photoresist layer after the development, obtaining a window of a line width of the gate cap on the second photoresist layer, and the line width of the gate cap being greater than the line width of the gate root.
Optionally, the line width of the auxiliary pattern is 0.5 to 2 times of the line width of the gate cap.
Optionally, the auxiliary pattern is exposed by using the second exposure dose, and the optimal line width of the auxiliary pattern is equal to the line width of the gate cap.
Optionally, the photoresist stack layer has a pattern region formed by a plurality of T-shaped patterns arranged at intervals, and the auxiliary patterns are located on two outer sides of the pattern region.
Optionally, a distance between the auxiliary pattern and the T-shaped patterns arranged on the outermost side is 0.5 to 2 times a distance between the T-shaped patterns.
Optionally, in step 3), the metal is deposited by an evaporation process, and the metal is a Pt/Ti/Pt/Au/Ti laminated layer, a Ti/Al/Ti laminated layer, or a Ni/Pt/Au/Ti laminated layer, and has a thickness range of 300-600 nm.
Optionally, in the step 4), attaching a UV film to the surface of the structure formed in the step 3) to perform metal gold tearing, and then stripping the photoresist.
Optionally, between the steps 2) and 3), a step of etching the surface of the semiconductor substrate in the T-shaped pattern is further included.
The invention has the beneficial effects that:
the auxiliary patterns are arranged on the two sides of the T-shaped pattern of the light resistance lamination, when metal is deposited, the metal is deposited in the auxiliary patterns at the same time, so that the deformation quantity of the light resistance around the T-shaped pattern in the metal deposition process is reduced, the influence on the T-shaped gate appearance caused by light resistance deformation is reduced, the stability of the T-shaped gate metal appearance is improved, the problems of T-shaped gate collapse and the like after the light resistance is stripped are effectively avoided, and the process yield and the performance stability of devices are improved.
Drawings
FIG. 1 is a process flow diagram of an embodiment of a method of electron beam lithography assisted process fabrication;
FIG. 2 is a top view showing a positional relationship between a T-shaped pattern and an assist pattern in the method of manufacturing an electron beam lithography assist process according to the embodiment;
FIG. 3 is an electron micrograph of a T-shaped gate obtained by the electron beam lithography assisting process manufacturing method of the embodiment;
fig. 4 is an electron micrograph of a T-shaped grid obtained by the manufacturing method of the comparative example.
Detailed Description
The invention is further explained below with reference to the figures and the specific embodiments. The drawings are only schematic and can be easily understood, and the specific proportion can be adjusted according to design requirements. The definitions of the top and bottom relationships of the relative elements and the front and back sides of the figures described herein are understood by those skilled in the art to refer to the relative positions of the components and thus all of the components may be flipped to present the same components and still fall within the scope of the present disclosure.
Referring to fig. 1, specific steps of an e-beam lithography assisted process manufacturing method according to an embodiment are described below.
Referring to fig. 1A, a first photoresist layer 21 and a second photoresist layer 22 are sequentially coated on a semiconductor substrate 1 to form a photoresist stack 2, and the thicknesses of the first photoresist layer 21 and the second photoresist layer 22 are selected according to the structure of a T-shaped gate to be formed.
Referring to fig. 1B, the resist stack 2 is subjected to electron beam exposure and development to obtain a T-shaped pattern 2a and auxiliary patterns 2B on both sides of the T-shaped pattern 2 a. The formation of the T-shaped pattern can refer to the prior art, firstly, the exposure dose of the first photoresist layer 21 is calculated as a first exposure dose, the exposure dose of the second photoresist layer 22 is calculated as a second exposure dose, then, the photoresist lamination is exposed by adopting the first exposure dose and the second exposure dose in an electron beam direct writing mode, different photoetching areas of the two photoresist layers are formed by adjusting the photoetching doses, a window of the line width of a grid root is obtained on the first photoresist layer 21 after development, a window of the line width of a grid cap is obtained on the second photoresist layer 22, and the line width of the grid cap is larger than the line width of the grid root, so that a window with a T-shaped section is obtained, and the window exposes the surface of the semiconductor substrate 1. When the auxiliary pattern 2b is formed, the second photoresist layer 22 is exposed with a second exposure dose, the exposure depth is the thickness of the second photoresist layer 22, and the first photoresist layer 21 is not exposed, so as to obtain an opening of the second photoresist layer 22, and the opening exposes the surface of the first photoresist layer 21. Of auxiliary patterns 2b obtained by the above-mentioned methodThe line width is the same as the line width of the gate cap, and in addition, when the auxiliary pattern 2b is formed, other exposure energy may be used to expose the second photoresist layer 22, so that the line width range of the auxiliary pattern 2b is within 0.5 to 2 times of the line width of the gate cap. Further, referring to fig. 2, according to the device design, a plurality of T-shaped patterns are simultaneously formed, the photoresist stack 2 is formed with a pattern region (a region of a frame S in the figure) formed by a plurality of T-shaped patterns 2a arranged at intervals, and the auxiliary patterns 2b are located at two outer sides of the pattern region S, where the two outer sides refer to the left and right sides in the extending direction (length direction) of the T-shaped patterns 2a, that is, the two sides in the arrangement direction of the source electrode, the gate electrode, and the drain electrode; the auxiliary pattern 2b may be a linear groove arranged in parallel with the T-shaped pattern 2a, and the length thereof is not less than that of the T-shaped pattern 2 a; the distance between the auxiliary patterns 2b and the outermost T-shaped patterns 2a is L1Then L is1＝0.5～2L。
The surface of the semiconductor substrate 1 within the T-shaped pattern 2a may be selectively etched as required.
Referring to fig. 1C, a metal 3 is deposited by an evaporation process, a T-shaped gate metal 31 contacting the semiconductor substrate 1 is formed in the T-shaped pattern 2a, and an auxiliary metal 32 on the first photoresist layer 21 is formed in the auxiliary pattern 2 b; the conventional grid metal can be applied to the invention, such as a Pt/Ti/Pt/Au/Ti or Ti/Al/Ti or Ni/Pt/Au/Ti laminated layer, and the thickness range is 300-600 nm. Because the photoresist is deformed due to the stress effect on the photoresist in the metal evaporation process, the photoresist has a deformation coefficient equal to the product of the deformation coefficient and the continuous length of the photoresist, and through the arrangement of the auxiliary pattern 2b, deposited within the auxiliary pattern 2b at the time of metal deposition, thereby blocking the amount of the photoresist deformation outside the patterns of the pattern regions S and 2b from being transferred into the pattern regions S, the amount of the photoresist deformation outside the outermost T-shaped pattern 2a being only the distance between the outermost T-shaped pattern 2a and the auxiliary pattern 2b, but the distance from the non-outermost T-shaped pattern 2a to the edge of the semiconductor substrate 1 greatly improves the influence of the photoresist deformation on the appearance of the T-shaped pattern 2a, thereby improving the influence of the morphology of the T-shaped gate metal 31 formed in the T-shaped pattern 2a, and improving the stability of the morphology of the T-shaped gate metal 31.
Referring to fig. 1D, a UV film is attached to the surface of the structure after metal deposition and then torn off, a metal gold tearing process is performed, metal on the photoresist is stripped when metal is torn off, then the photoresist lamination 2 and the auxiliary metal 32 are stripped off by means of spray washing, soaking of a photoresist removing solution, and the T-shaped gate metal 31 is remained.
The subsequent process refers to a conventional process and comprises the steps of forming a dielectric layer and the like.
Referring to fig. 3, after the subsequent process is performed, the T-shaped gate metal 31 has a stable shape and a complete appearance, and does not collapse.
As a comparative example, no auxiliary pattern was formed, and the rest was the same as in the above example. Referring to fig. 4, since the deformation amount of the photoresist on the outer side of the outermost T-shaped pattern is the product of the distance from the outermost T-shaped pattern to the edge of the semiconductor substrate 1 and the deformation coefficient, the deformation amount is large, which causes the T-shaped pattern to deform, and after the subsequent processes are performed, the T-shaped gate metal has problems of collapse, black edges, adhesion with the outer layer metal, and the like.
The above embodiments are only used to further illustrate the electron beam lithography assisted process manufacturing method of the present invention, but the present invention is not limited to the embodiments, and any simple modification, equivalent change and modification made to the above embodiments according to the technical spirit of the present invention fall within the protection scope of the technical solution of the present invention.
Claims (9)
1. A manufacturing method of electron beam lithography auxiliary process is characterized by comprising the following steps:
1) forming a light resistance lamination layer on a semiconductor substrate, wherein the light resistance lamination layer comprises a first light resistance layer and a second light resistance layer which are formed in sequence;
2) carrying out electron beam exposure and development on the light resistance lamination to obtain a T-shaped graph and auxiliary graphs positioned on two sides of the T-shaped graph, wherein the exposure depth of the T-shaped graph is the thickness of the first light resistance layer and the second light resistance layer, and the exposure depth of the auxiliary graphs is the thickness of the second light resistance layer;
3) depositing metal, wherein T-shaped gate metal which is in contact with the semiconductor substrate is formed in the T-shaped pattern, and auxiliary metal which is not in contact with the semiconductor substrate is formed in the auxiliary pattern;
4) and removing the photoresist lamination layer and remaining the T-shaped gate metal.
2. The electron beam lithography aided process manufacturing method according to claim 1, characterized in that: and when the T-shaped graph is formed, calculating the exposure dose of the first light resistance layer as a first exposure dose, calculating the exposure dose of the second light resistance layer as a second exposure dose, adopting the first exposure dose and the second exposure dose to expose the light resistance laminated layer, obtaining a window of the line width of the grid root on the first light resistance layer after development, obtaining a window of the line width of the grid cap on the second light resistance layer, and enabling the line width of the grid cap to be larger than the line width of the grid root.
3. The electron beam lithography aided process manufacturing method according to claim 2, wherein: the line width of the auxiliary pattern is 0.5-2 times of the line width of the gate cap.
4. The electron beam lithography aided process manufacturing method according to claim 3, wherein: and the auxiliary pattern is exposed by adopting the second exposure dose, and the line width of the auxiliary pattern is equal to the line width of the gate cap.
5. The electron beam lithography aided process manufacturing method according to claim 1, characterized in that: the light resistance lamination layer is provided with a pattern area formed by a plurality of T-shaped patterns which are arranged at intervals, and the auxiliary patterns are positioned at two outer sides of the pattern area.
6. The electron beam lithography aided process manufacturing method according to claim 5, wherein: the distance between the auxiliary pattern and the T-shaped patterns arranged on the outermost side is 0.5-2 times of the distance between the T-shaped patterns.
7. The electron beam lithography aided process manufacturing method according to claim 1, characterized in that: and 3) depositing the metal by adopting an evaporation process, wherein the metal is a Pt/Ti/Pt/Au/Ti laminated layer, a Ti/Al/Ti laminated layer or a Ni/Pt/Au/Ti laminated layer, and the thickness range is 300-600 nm.
8. The electron beam lithography aided process manufacturing method according to claim 1, characterized in that: in the step 4), a UV film is attached to the surface of the structure formed in the step 3) to perform metal gold tearing, and then the photoresist is stripped.
9. The electron beam lithography aided process manufacturing method according to claim 1, characterized in that: between the steps 2) and 3), the steps of cleaning and etching the surface of the semiconductor substrate in the T-shaped pattern are also included.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110466453.3A CN113517177B (en) | 2021-04-27 | 2021-04-27 | Manufacturing method of electron beam lithography auxiliary process |
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| CN202110466453.3A CN113517177B (en) | 2021-04-27 | 2021-04-27 | Manufacturing method of electron beam lithography auxiliary process |
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| CN113517177A true CN113517177A (en) | 2021-10-19 |
| CN113517177B CN113517177B (en) | 2023-03-21 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0774186A (en) * | 1993-09-03 | 1995-03-17 | Nec Corp | Manufactuee of semiconductor device |
| JPH10144582A (en) * | 1996-11-07 | 1998-05-29 | Denso Corp | Manufacture of semiconductor device |
| CN107863291A (en) * | 2017-11-08 | 2018-03-30 | 西安电子科技大学 | A kind of electronic beam photetching process for making T-shaped grid structure |
| JP2019067902A (en) * | 2017-09-29 | 2019-04-25 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method |
| CN110808207A (en) * | 2019-11-13 | 2020-02-18 | 中国电子科技集团公司第十三研究所 | T-shaped nano gate and preparation method thereof |
-
2021
- 2021-04-27 CN CN202110466453.3A patent/CN113517177B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0774186A (en) * | 1993-09-03 | 1995-03-17 | Nec Corp | Manufactuee of semiconductor device |
| JPH10144582A (en) * | 1996-11-07 | 1998-05-29 | Denso Corp | Manufacture of semiconductor device |
| JP2019067902A (en) * | 2017-09-29 | 2019-04-25 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method |
| CN107863291A (en) * | 2017-11-08 | 2018-03-30 | 西安电子科技大学 | A kind of electronic beam photetching process for making T-shaped grid structure |
| CN110808207A (en) * | 2019-11-13 | 2020-02-18 | 中国电子科技集团公司第十三研究所 | T-shaped nano gate and preparation method thereof |
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