CN113507305B

CN113507305B - Digital array beam forming device

Info

Publication number: CN113507305B
Application number: CN202110877456.6A
Authority: CN
Inventors: 唐洪军; 张晓波; 邵永杰; 胡洪
Original assignee: Southwest Electronic Technology Institute No 10 Institute of Cetc
Current assignee: Southwest Electronic Technology Institute No 10 Institute of Cetc
Priority date: 2021-07-31
Filing date: 2021-07-31
Publication date: 2023-06-23
Anticipated expiration: 2041-07-31
Also published as: CN113507305A

Abstract

The digital array beam forming device disclosed by the invention has the advantages of low cost and high reliability. The invention is realized by the following technical scheme: the clock management unit comprising a local crystal oscillator is adopted, the obtained clock, synchronous signals and local oscillation signals are sent to a plurality of digital TR components and a high-speed signal preprocessing unit at the front end in a branching way through a clock distribution network, and the signals are sent to an analog optical module to realize the wave division multiplexing; the main control unit divides the multipath sampling data into two groups and sends the two groups to the high-speed signal preprocessing unit, after beam data are formed, the beam data are transmitted through a high-speed interface between two FPGAs, independent multi-beam data are formed in the FPGAs, a time-frequency distribution circuit and a local oscillator and a clock which are realized by processing the beam data are synchronously distributed to the rear-stage two digital optical modules and then to the baseband signal processing module, and the network switch is matched to complete the program dynamic update of a plurality of array control modules, so that the baseband data transmission of the dual redundancy backup of the beam data is realized.

Description

Digital array beam forming device

Technical Field

The invention relates to the field of array signal processing such as measurement and control, communication and the like, in particular to a low-cost digital phased array beam forming device.

Background

The antenna array is a directional array composed of directional antenna units, and in general, the digital array of the all-digital array antenna is divided into antenna units, digital TR modules, a beam forming device, baseband signal processing and the like. The all-digital array antenna digital array element realizes the broadband all-digital array receiving and transmitting beam in an all-digital mode, although the beam forming is flexible. However, each channel needs to be sampled independently and beam synthesis is realized at a later stage, so that the system scale is very huge, and the optical fiber is adopted to transmit mass data between the digital TR and the beam forming DBF processing module, the optical modules are added at the receiving and transmitting ends, the use quantity of the optical modules is large, the material cost is high, and the use range of a large-scale digital array is limited. The use of conventional narrowband beamforming for wideband digital arrays can result in directional shifts in the pattern and main lobe distortions. For the phenomenon that the microstrip calibration network has larger radiation and can have adverse effect on the receiving component, when the number of beams to be formed is large, hardware becomes complex and difficult to test and adjust, and a plurality of receiving beams with low side lobes are more difficult to form. Especially, the group delay at each frequency point in the frequency band is inconsistent under the influence of factors such as a filter, an amplifier, an impedance matching network and the like, fluctuation is generated, and the in-band group delay fluctuation of the digital array receiving channel analog-digital mixing system and the in-band group delay fluctuation of the frequency conversion system are difficult to directly measure; therefore, the alignment error must be corrected before the delay measurement. Modern time delay measurement includes vernier method, tap delay line method, differential delay line method, etc. Due to device manufacturing tolerances, temperature and environmental characteristics differences between the digital array T/R components, the amount of time delay between the components is inconsistent, requiring measurement of the amount of relative time delay between the components for correction. In practice, the array typically contains tens or hundreds of components, so that it is preferable to obtain the relative delay of multiple components in one measurement process. In order to obtain high measurement accuracy, interpolation processing, nonlinear correction, a DLL method, a PLL method, or the like may also be performed. These methods require special chips or equipment, are complex and are not suitable for time delay measurement of multi-component large-time-band-product LFM pulse signals in principle.

Disclosure of Invention

In view of the above, the present invention provides a digital array beam forming device with high integration, low cost, high reliability, full module electromagnetic shielding and remote updating functions. The invention further aims to provide a digital array delay measuring method with simple total group delay fluctuation measuring method, reliable test result and high test efficiency based on the digital array beam forming device.

The above object of the present invention can be achieved by a digital array beam forming apparatus comprising: the high-speed signal preprocessing unit based on a plurality of digital TR components of a high-speed differential cable interconnection front stage synchronously receives a time-frequency distribution circuit and a beam data processing circuit of sampling data of a plurality of digital TR component channels, is connected with a clock management unit and a main control unit of the high-speed signal preprocessing unit, is connected with baseband processing equipment of at least two digital optical modules, and is provided with a power management unit of a power supply, and is characterized in that: the clock management unit comprising a local crystal oscillator is used for realizing internal and external clock switching through a clock distribution network, amplifying the obtained clock, synchronizing signals and local oscillation signals by an amplifying circuit and a single-pole double-throw switch, and then sending the internal and external clocks to a plurality of digital TR components at the front end and a local FPGA of a high-speed signal preprocessing unit in a branching way for use, and simultaneously sending the clock, synchronizing signals and local oscillation signals to an analog optical module through a single optical fiber to realize wave division multiplexing; the multi-path sampling data generated by the main control unit are divided into two groups and respectively sent to the high-speed signal preprocessing unit, after beam data are formed, 32 paths of beam data are transmitted through a high-speed interface between two FPGAs, finally independent multi-beam data are formed in the respective FPGAs, a time-frequency distribution circuit and a local oscillator and a clock realized by beam data processing are synchronously distributed to two digital optical modules at the later stage communicated with the time-frequency distribution circuit and the local oscillator and clock, the digital optical modules are sent to the baseband signal processing module, and a network switch is matched to complete the program dynamic update of a plurality of array control modules, so that the high-speed baseband data transmission of the dual redundancy backup of the beam data is realized.

The method for realizing digital array time delay measurement by using the digital beam forming device has the following technical characteristics: the method comprises the steps that electric signal transmission is used between a digital TR component and a beam forming module, a reference clock generated by a clock source is fed into a time-frequency system, the time-frequency system generates multiple paths of sampling clocks and synchronous Signals (SYNC) generated after distributing sampling according to functional requirements, the multiple paths of sampling clocks and the synchronous signals are distributed to delay measuring modules of different subarrays of a digital array system respectively, and phase relation detection is carried out through the delay measuring modules at synchronous triggering moments among the subarrays to obtain output signals of all channels; the delay measurement module collects two-stage clocks of an excitation channel from a reference signal needing a delay measurement point and each subarray, simultaneously sends the two-stage clocks into a field programmable gate array FPGA, measures the relative delay between a plurality of channels, compares the phase difference of rising edges of two paths of signals in real time, continuously adjusts the delay of a synchronous signal in the process, records the current delay value if the FPGA detects the change of the phase value of the transmission delay of each array element of a digital array in real time, carries out difference frequency processing on the reference signal and linear frequency modulation signals LFM of different delay times, operates a delay algorithm after the difference frequency, carries out delay operation on single-frequency signals related to the measured frequency domain position and the delay time, obtains the relative delay value between the channel to be measured and the reference channel, and calculates the delay time.

Compared with the prior art, the invention has the beneficial effects that:

the integration level is high, and the cost is low. The invention is based on a high-speed signal preprocessing unit of a plurality of digital TR components of a high-speed differential cable interconnection front stage, a time-frequency distribution circuit and a beam data processing circuit for synchronously receiving sampling data of channels of the plurality of digital TR components, a clock management unit and a main control unit which are connected with the high-speed signal preprocessing unit, a baseband processing device which is connected with at least two digital optical modules, a power management unit for providing power, an integrated time-frequency distribution function and high integration level. Through the integrated design of the time-frequency distribution circuit and the beam data processing circuit. The synchronous distribution of the local oscillator and the clock is realized, and the sampling data of 64 channels in total can be synchronously received by 16 digital TR components. The cost of the device can be reduced by 30%, and the device has dual redundancy backup of beam data. Compared with the traditional digital array in which the digital TR component and the DBF processing module adopt optical fiber transmission, the method for adding the optical module at the receiving and transmitting end has low cost. And electric signal transmission is used between the digital TR component and the beam forming module, so that the system cost is greatly reduced.

The real-time performance is good. The invention adopts a clock management unit comprising a local crystal oscillator to realize internal and external clock switching through a clock distribution network, the obtained clock, synchronous signal and local oscillation signal are amplified by an amplifying circuit and a single-pole double-throw switch, and then the internal and external clocks are sent to a plurality of digital TR components at the front end and a local FPGA of a high-speed signal preprocessing unit in a branching way for use, and simultaneously the clock, the synchronous signal and the local oscillation signal are sent to an analog optical module through a single optical fiber to realize wave division multiplexing; the method realizes the synchronous transmission of data of 640Gbps in total for 64 nodes, wherein each node is 10 Gbps. The real-time performance is good.

The reliability is high. The invention adopts the multi-path sampling data generated by the main control unit to be divided into two groups and respectively sent to the high-speed signal preprocessing unit, after beam data are formed, 32 paths of beam data are transmitted by the high-speed interface intersection between two FPGAs, finally independent multi-beam data are formed in the respective FPGAs, a time-frequency distribution circuit and a local oscillator and a clock realized by beam data processing are synchronously distributed to two digital optical modules at the later stage communicated with the time-frequency distribution circuit and the local oscillator and the clock, and the digital optical modules are sent to the baseband signal processing module, and the program dynamic update of a plurality of array control modules is completed by matching with a network switch, so that the high-speed baseband data transmission is realized. The transmission data quantity is large, the transmission distance is the longest and is close to 2m, the single-channel data rate reaches 9.6Gbps, the number of single array channels of the digital array can reach 64 paths, 64 paths of sampling data are divided into two groups and are respectively sent to the FPGA1 and the FPGA2, the FPGA1 and the FPGA2 are mutually transmitted through a high-speed interface between two FPGAs after forming beam data, 32 paths of beam data are formed in the respective FPGAs, and finally independent multi-beam data are formed in the respective FPGAs and are sent to a baseband signal processing module through a rear-stage optical module, so that the two groups of beam data can realize 1:1 beam data double redundancy and complete backup. By adopting the long-distance electric signal transmission technology based on high-speed differential cable interconnection, the problems of long-distance transmission high-frequency signal attenuation are overcome, the problem of coupling interference between transmission channels is solved, and the link transmission quality is improved. High reliability.

The measuring method is simple. The invention adopts a reference clock generated by a clock source to be sent into a time-frequency system, the time-frequency system generates a plurality of sampling clocks according to functional requirements and distributes synchronization Signals (SYNC) generated after sampling to be distributed to delay measurement modules of different subarrays of a digital array system respectively, and the phase relation detection is carried out through the delay measurement modules at synchronous triggering moments among the subarrays to obtain output signals of all channels; the link does not need to be disconnected and an additional test port is led out, so that the group delay fluctuation index can be measured online at any time; the group delay fluctuation index of all the receiving channels of the digital array can be measured at the same time, so that the method has good real-time performance. The measuring method is simple.

The test result is reliable. The invention adopts a delay measurement module to collect two-stage clocks of an excitation channel and a reference signal of a time delay measurement point and each subarray, and simultaneously sends the two-stage clocks into a field programmable gate array FPGA (field programmable gate array), the relative time delay between a plurality of channels is measured, the phase difference of rising edges of two paths of signals is compared in real time, the time delay of a synchronous signal is continuously adjusted in the process, if the FPGA detects that the phase value of the transmission time delay of each array element of a digital array changes in real time, the current time delay value is recorded, the reference signal and linear frequency modulation signals LFM of different delay times are processed in a difference frequency manner, a time delay algorithm is operated after the difference frequency, the measured frequency domain position and a single-frequency signal related to the delay time are subjected to time delay operation, the relative time delay value between the channel to be measured and the reference channel is obtained, and the delay time is calculated. The method can directly measure the total group delay fluctuation of the digital array receiving channel including the variable frequency receiving channel and the ADC, has reliable test result and high test efficiency, and the measured group delay fluctuation data is obtained by multipoint fitting, so that the measurement accuracy is high.

The test efficiency is high. In order to avoid using an emulator to update programs in an external field environment, the invention adopts the FPGA1 and FPGA2 program dynamic update flow, the board level supporting unit is used for controlling the FPGA to process, and a network port is additionally provided for dynamically updating the programs in the module. The updated program data is received through the network port input board level support unit, the system can be matched with a network switch, and program updating of a plurality of array control modules is conveniently completed. After updating, starting a program solidification flow, storing data into a FLASH, after finishing, reading back the data in the FLASH, checking that the solidified data is correct, reloading the FPGA according to the needs of a user, checking the data according to frames or after all the data are received, ensuring that the received data are correct, storing the received data into an off-chip DDR memory, realizing remote updating and state monitoring functions through a main control, and improving the program updating efficiency.

The invention is applicable to digital array systems with baseband numerical control rate not exceeding 240MHz and signal bandwidth not exceeding 200M.

Drawings

This patent is further described below with reference to the drawings and examples.

Fig. 1 is a front view of a digital array beamforming apparatus of the present invention;

FIG. 2 is a bottom view of FIG. 1;

FIG. 3 is a partial side perspective view of the front side panel of FIG. 1;

fig. 4 is a schematic circuit diagram of the PCB sub-board of the printed circuit board of fig. 3;

FIG. 5 is a diagram of the clock distribution network of FIG. 4;

FIG. 6 is a flowchart of the power-on operation of FIG. 4;

FIG. 7 is a power supply topology of the power management unit of FIG. 4;

FIG. 8 is a flow chart of the present invention for implementing digital array delay measurement using FIG. 1;

in the figure: 1. the high-speed connector shielding armor, an aluminum alloy structural member, a box cavity heat conduction shielding cover plate and a heat conduction copper bar.

The technical scheme of the invention is further described in detail below with reference to the accompanying drawings.

Detailed Description

See fig. 1-4. In a preferred embodiment described below, a digital array beamforming apparatus comprises: the high-speed signal preprocessing unit based on a plurality of digital TR components of a high-speed differential cable interconnection front stage synchronously receives a time-frequency distribution circuit and a beam data processing circuit of sampling data of a plurality of digital TR component channels, is connected with a clock management unit and a main control unit of the high-speed signal preprocessing unit, is connected with baseband processing equipment of at least two digital optical modules, and provides a power supply management unit of a power supply, wherein: the clock management unit comprising a local crystal oscillator is used for realizing internal and external clock switching through a clock distribution network, amplifying the obtained clock, synchronizing signals and local oscillation signals by an amplifying circuit and a single-pole double-throw switch, and then sending the internal and external clocks to a plurality of digital TR components at the front end and a local FPGA of a high-speed signal preprocessing unit in a branching way for use, and simultaneously sending the clock, synchronizing signals and local oscillation signals to an analog optical module through a single optical fiber to realize wave division multiplexing; the multi-path sampling data generated by the main control unit are divided into two groups and respectively sent to the high-speed signal preprocessing unit, after beam data are formed, 32 paths of beam data are transmitted through a high-speed interface between two FPGAs, finally independent multi-beam data are formed in the respective FPGAs, a time-frequency distribution circuit and a local oscillator and a clock realized by beam data processing are synchronously distributed to two digital optical modules at the later stage communicated with the time-frequency distribution circuit and the local oscillator and clock, the digital optical modules are sent to the baseband signal processing module, and a network switch is matched to complete the program dynamic update of a plurality of array surface control modules, so that the high-speed baseband data transmission is realized.

The rectangular box body of the digital array beam forming device is an aluminum alloy structural member 2, rectangular connectors for connecting digital TR assemblies are assembled on two sides of a front end panel of the box body, two high-speed connector shielding armors 1 which are sequentially arranged are arranged between the rectangular connectors on two sides, the high-speed connector shielding armors 1 are installed on the panel of the box body from outside to inside through screws, the box body extends out from inside to outside, the rectangular connectors are pressed on a PCB (printed circuit board) daughter board through a panel back end connecting socket, and a conductive sealing rubber shielding pad is embedded in a groove between the heat conduction shielding cover plates 3 of the box body cavity to be screwed from inside to outside, so that the plug and socket pair connection can be fully contacted through the conductive sealing rubber shielding pad, and a shielding cavity is formed together with the metal box body, thereby realizing the built-in full-module electromagnetic shielding of the box body. The full electromagnetic shielding of the device is realized through the matching design of the shielding groove, the metal armor and the conductive sealing ring.

In an alternative embodiment, unlike the traditional heat dissipation mode from liquid cooling to the module, the heat conduction bottom plate arranged at the bottom of the box body is at least embedded with two heat conduction copper bars 4 which are arranged in parallel and have the same heat dissipation effect as the liquid cooling to the module, and the heat conduction copper bars can rapidly conduct heat generated by the device to the bottom of the built-in module and dissipate heat through the system cold plate. The heat conducting copper bar 4 avoids the use of a liquid cooling head and a complex liquid cooling plate processing flow, and saves the cost. LTM4630 provides 36A without an external heat sink at up to 60 ℃ with no air flow ambient temperatures 65 ℃ (200 LFM) and 69 ℃ (400 LFM). If an external heat sink is used, the high operating environment temperature may be raised by about 10 ℃.

Full electromagnetic shielding: the electromagnetic shielding of the whole module is realized in the following three modes, namely, the electromagnetic shielding of the cavity is realized by embedding a conductive sealing adhesive tape in a groove between the cavity of the module and the cover plate. 2. The rectangular connector is screwed in the direction from inside to outside, and a conductive sealing adhesive tape is added at the edge of the flange plate to carry out electromagnetic shielding. 3. The high-speed connector is provided with the metal armor at the position of the module opening, so that electromagnetic shielding of the module opening is realized, and the shielding pad is arranged on the connector plug to enable the connector plug to be in close contact with the connector plug in the opposite inserting state.

The high-speed signal preprocessing unit includes: 2V 7 FPGAs connected in series through a GTX/GTH high-speed serial interface, each V7FPGA has 32 groups of GTH high-speed interfaces with a front-end TR assembly, 12 groups of GTH high-speed interfaces with a rear-end CXP, and 5 groups of GTH high-speed interfaces are arranged between the two FPGAs. The time-frequency distribution circuit and the beam data processing circuit are connected through a GTH4X high-speed interface, the time-frequency distribution circuit and the beam data processing circuit synchronously receive 64 channels of sampling data generated by 16 digital TR components, the 64 channels of sampling data are divided into two groups and are respectively sent to the FPGA1 and the FPGA2, synchronous distribution of local oscillators and clocks is achieved, after the FPGA1 and the FPGA2 form beam data, the high-speed interfaces between the two FPGAs are used for mutually transmitting 32 channels of beam data, independent multi-beam data are formed in the FPGAs respectively, and after 1:1 of the two groups of beam data are completely backed up, the two groups of beam data are sent to the baseband signal processing module through the rear-stage optical module. The 64-way high-speed signal preprocessing hardware module can be composed of 2 pieces of XC7V690T and 1 piece of XC7Z045-2FFG 676I. The board level support unit is used as a central node of all FPGAs and FLASH to manage the loading of all FPGAs. The FPGA loads in an active synchronous BPI mode, and the board level support unit controls PROG pins of the FPGA and controls loading time sequence. The FPGA programs are respectively stored in NORFLASH with a BPI interface; when the system is powered on, the board-level support unit starts a program loading flow; firstly, providing a low pulse for a PROGRAM_B pin of the FPGA, starting a loading flow of the FPGA, and loading the FPGA still according to a parallel active loading mode.

The main control unit adopts 1 piece ZynqFPGA, generates a beam control code through an in-board reset circuit, controls the function of the front-end TR component, loads programs of all the pieces of FPGA and dynamically updates the programs. After the program is dynamically updated, the main control unit maintains self-checking to complete comprehensive detection of the hardware functions of the modules such as the working states of the FPGA1 and the FPGA2 chips, the working states of the interfaces, the working voltage and the like, and detects the working states, the working temperatures and the working voltage of the chips in two modes of periodic self-checking and maintenance self-checking, and the periodic self-checking is used for completing real-time detection of the hardware functions of the modules, and the detection results are reported.

See fig. 5. The clock distribution network includes: the system comprises a demultiplexing circuit which realizes demultiplexing by sending a single optical fiber to an optical module, wherein the demultiplexing circuit sends radio frequency signals RF1, RF2, a clock CLK, a synchronization SYNC and a local oscillator signal to a clock management unit, the clock management unit obtains the clock CLK, the synchronization SYNC and the local oscillator signal which are amplified by an amplifier, the signals are split into 16 paths of reference clocks and 16 paths of synchronization signals by a splitter, and the 16 paths of reference clocks are sent to a clock synthesis/distributor by splitting a local crystal oscillator and distributed to 16 digital TR components and a local FPGA1 at the front end; meanwhile, 16 paths of synchronous signals split by the splitter are distributed to the FPGA2 through the distributor to realize reliable backup of the local clock, and internal and external clock switching can be realized through a single-pole double-throw switch, so that the local FPGA can work normally when the external clock is unstable.

See fig. 6. In one mode of self-checking and maintenance self-checking, after the beam forming device is powered on, in a normal operation mode of the module, the main control unit autonomously loads a program, waits for a maintenance self-checking instruction, receives the instruction, controls the FPGA1 and the FPGA2 to load basic version programs according to the self-checking instruction received by the FPGA3, judges whether the FPGA1 and the FPGA1 programs are loaded successfully, otherwise returns to load the basic version programs, if so, after the FPGA1 and the FPGA1 programs are loaded successfully, the automatic detection timer and interruption, the FPGA1 state, the FPGA2 state and the DCM state are monitored in the FPGA1, the detection of an asynchronous serial bus, a synchronous serial bus, a DDR3, a FLASH and a GTH communication interface and the detection of voltage are reported according to the self-checking instruction received by the FPGA3, and the program is finished. And the main control unit judges whether the FPGA1 and the FPGA1 programs are successfully loaded, if not, the main control unit returns to the loading of the basic version programs, if so, the main control unit independently detects FLASH, the asynchronous serial bus, DCM, DDR3 and GTH interfaces respectively after the FPGA1 and the FPGA1 are successfully loaded, the working state, the working temperature and the working voltage of the detection chip are detected in two modes of periodic self-detection and maintenance self-detection, the real-time detection of the hardware functions of the modules is completed through the periodic self-detection, and the detection result is reported.

In one mode of self-checking and maintenance self-checking, after the beam forming device is powered on, the main control unit autonomously loads programs to control the FPGA2 and the FPGA1 to load application version programs, after the FPGA1 program is loaded successfully, the FPGA1 operates a normal preprocessing function, after the FPGA2 program is loaded successfully, the FPGA2 operates a normal preprocessing function, if the main control unit receives a periodic self-checking instruction, the self-checking result of the last period is immediately returned, after the self-checking is completed, the self-checking temperature value, the voltage value and other results of the current period are acquired, the self-checking result of the next period is buffered and used as the self-checking result of the next period, in order to improve the real-time performance of the self-checking return of the period, the self-checking return result of the current period is the self-checking result of the last period, and so on.

The front stage of the digital beam forming device is connected with the digital TR components 1-16, and provides DC28V power supply, SYNC synchronous signal, 240MHz clock signal, 2550MHz, local oscillation signal, RS422 control signal and RESET RESET signal for the 16 digital TR components respectively. The latter stage is connected with the baseband signal processing device, and high-speed baseband data transmission is realized by the two 12 pairs of high-speed serial interfaces GTH and the baseband signal processing device.

The module needs to provide DC28V power supply and CLK and SYNC signals externally. The power management unit includes: through TR subassembly, time-frequency module, established ties surge suppressor and model for CDM24AP120M switching power supply through the EMI wave filter, input power supply voltage is +28V's power topology module, because voltage and the inside voltage differential that needs of power topology module are great, power management unit adopts two-stage voltage conversion scheme, and power topology module first level changes +28V +12V, and the second level changes 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, 1.0V that each passageway needs from +12V. The power management unit adopts a power management chip to control the power-on sequence of each power supply in the second-stage power conversion circuit and monitor the output of each power supply. The rated output current of each power conversion chip and the actual current of the internal devices in the power topology module are smaller than the rated current of the power chip, and the actual maximum use current is 7.8A so as to meet the use requirement, and the rated output current of the power conversion chip is 18A so as to meet the derating requirement. The power topology module controls the power-ON and power-OFF time sequence of the miniature module voltage-reduction type voltage stabilizer LTM4630 respectively through a power monitor and a sequence controller ispPAC-POWR1014 power management chip and through a DC/DC voltage stabilizer system formed by a parallel connected switch ON/OFF and the miniature module voltage-reduction type voltage stabilizer LTM4630, and sequentially controls the voltages of VCCINT, MGTACTT, VCCALXT, VCCO, MGTACCC and DDR3 of the FPGA1 and the FPGA2 according to the power-ON sequences of 1.0V, 1.2V, 1.5V, 1.8V, 2.5V and 3.3V, wherein the power-OFF sequences of the modules are opposite to the power-ON sequences, and the power-ON sequences are as follows: 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, 1.0V. The power supply monitor and the sequence controller output control signals by using programmable power supply monitors, a reset generator and the sequence controller programmable currents and voltages, and simultaneously monitor the ascending/descending output of the power supply slope of the miniature module buck voltage stabilizer, sequentially control the power supply in a wide power supply voltage range, monitor the power supply by using an analog input channel and control DC-DC conversion.

The LTM4630 of the DC/DC voltage regulator system includes an inductor, MOSFETs, a DC/DC controller and a compensation circuit, which uses highly sophisticated analog and LGA flat packages without changing the printed circuit board layout, realizing 4 pin compatibility for different power levels and a more densely arranged circuit board. LTM4630 operates in 180 deg.c opposite phase to minimize output ripple and input ripple, convert 12VIN into high power (up to 144A) load point voltage as low as 0.6V, and the internal remote sense amplifier can ensure the accuracy of providing +/over the whole temperature, voltage and load range by sensing the voltage at the load end and compensating the voltage drop caused by the printed circuit board wiring impedance 1.5% output regulation provides fast short-circuit protection, minimizes IOUT, resumes operation once the short-circuit condition is eliminated, protects the load and upstream power supply, and achieves high efficiency and low thermal package impedance. The heat dissipation device has excellent heat dissipation, expandability and high output power capability, and occupies a small surface.

See fig. 8. According to the invention, electric signal transmission is used between a digital TR component and a beam forming module, a reference clock generated by a clock source is sent to a time-frequency system, the time-frequency system generates multiple sampling clocks and synchronous Signals (SYNC) generated after distributing and sampling according to functional requirements, the synchronous signals are distributed to delay measuring modules of different subarrays of a digital array system respectively, and at synchronous triggering time among subarrays, phase relation detection is carried out through the delay measuring modules, so that output signals of all channels are obtained; the delay measurement module collects two-stage clocks of an excitation channel from a reference signal needing a delay measurement point and each subarray, simultaneously sends the two-stage clocks into a field programmable gate array FPGA, measures the relative delay between a plurality of channels, compares the phase difference of rising edges of two paths of signals in real time, continuously adjusts the delay of a synchronous signal in the process, records the current delay value if the FPGA detects the change of the phase value of the transmission delay of each array element of a digital array in real time, carries out difference frequency processing on the reference signal and linear frequency modulation signals LFM of different delay times, operates a delay algorithm after the difference frequency, carries out delay operation on single-frequency signals related to the measured frequency domain position and the delay time, obtains the relative delay value between the channel to be measured and the reference channel, and calculates the delay time.

The invention is not described in detail in part as being common general knowledge to a person skilled in the art. Those of ordinary skill in the art will appreciate that the foregoing embodiments are provided to aid the reader in understanding the principles of the present invention, and that the scope of the invention is not limited to such specific statements and embodiments. Various modifications and variations of the present invention will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A digital array beamforming apparatus comprising: the high-speed signal preprocessing unit based on a plurality of digital TR components of a high-speed differential cable interconnection front stage synchronously receives a time-frequency distribution circuit and a beam data processing circuit of sampling data of a plurality of digital TR component channels, is connected with a clock management unit and a main control unit of the high-speed signal preprocessing unit, is connected with baseband processing equipment of at least two digital optical modules, and is provided with a power management unit of a power supply, and is characterized in that: the clock management unit comprising a local crystal oscillator is used for realizing internal and external clock switching through a clock distribution network, amplifying the obtained clock, synchronizing signals and local oscillation signals by an amplifying circuit and a single-pole double-throw switch, and then sending the internal and external clocks to a plurality of digital TR components at the front end and a local FPGA of a high-speed signal preprocessing unit in a branching way for use, and simultaneously sending the clock, synchronizing signals and local oscillation signals to an analog optical module through a single optical fiber to realize wave division multiplexing; the multi-path sampling data generated by the main control unit are divided into two groups and are respectively sent to the high-speed signal preprocessing unit, after beam data are formed, 32 paths of beam data are transmitted through a high-speed interface between two FPGAs in a crossing way, finally independent multi-beam data are formed in the respective FPGAs, a time-frequency distribution circuit and a local oscillator and a clock realized by beam data processing are synchronously distributed to two digital optical modules at the later stage communicated with the time-frequency distribution circuit and the local oscillator and clock, and are sent to the baseband signal processing module, and a network switch is matched to complete the program dynamic update of a plurality of array surface control modules, so that the high-speed baseband data transmission of dual redundancy backup of the beam data is realized;

the high-speed signal preprocessing unit comprises: 2V 7 FPGAs connected in series through a GTX/GTH high-speed serial interface, wherein each V7FPGA is provided with 32 groups of GTH high-speed interfaces with a front-end TR assembly, 12 groups of GTH high-speed interfaces with a rear-end CXP, and 5 groups of GTH high-speed interfaces are arranged between the two FPGAs;

the main control unit adopts 1 ZynqFPGA, generates a beam control code through an in-board reset circuit, controls the function of a front-end TR component, loads programs of the FPGAs, and dynamically updates the programs;

the clock distribution network comprises: the system comprises a demultiplexing circuit which realizes demultiplexing by sending a single optical fiber to an optical module, wherein the demultiplexing circuit sends radio frequency signals RF1, RF2, a clock CLK, a synchronization SYNC and a local oscillator signal to a clock management unit, the clock management unit obtains the clock CLK, the synchronization SYNC and the local oscillator signal which are amplified by an amplifier, the signals are split into 16 paths of reference clocks and 16 paths of synchronization signals by a splitter, and the 16 paths of reference clocks are sent to a clock synthesis/distributor by splitting a local crystal oscillator and distributed to 16 digital TR components and a local FPGA1 at the front end; meanwhile, 16 paths of synchronous signals split by the splitter are distributed to the FPGA2 through the distributor to realize reliable backup of the local clock, and the internal and external clocks are switched through the single-pole double-throw switch to ensure the normal operation of the local FPGA when the external clock is unstable.

2. The digital array beamforming apparatus of claim 1, wherein: the rectangular box body of the digital array beam forming device is an aluminum alloy structural member (2), rectangular connectors for connecting digital TR components are assembled on two sides of a front end panel of the box body, two high-speed connector shielding armors (1) which are sequentially arranged are arranged between the rectangular connectors on two sides, the high-speed connector shielding armors (1) are installed on the panel of the box body from outside to inside through screws, the rectangular connectors are crimped on a PCB (printed circuit board) through a connecting socket at the back end of the panel, and a conductive sealing rubber shielding pad is embedded in a groove between plates of a heat conducting shielding cover plate (3) of the box body to be screwed from inside to outside, so that the plug and the socket are connected with each other through the conductive sealing rubber shielding pad to form a shielding cavity together with the metal box body, and the electromagnetic shielding of the whole module arranged in the box body is realized through the matching design of shielding grooves, the metal armors and the conductive sealing rings.

3. The digital array beamforming apparatus of claim 2, wherein: the heat conduction bottom plate that is equipped with in the bottom half has two parallel arrangement's and just with liquid cooling to module radiating effect equivalent heat conduction copper bar (4) at least on heat conduction bottom plate, and the heat conduction copper bar can be fast with the device conduction of generating heat to built-in module bottom, dispel the heat through the system cold plate.

4. The digital array beamforming apparatus of claim 1, wherein: in the high-speed signal preprocessing unit: the time-frequency distribution circuit and the beam data processing circuit are connected through a GTH4X high-speed interface, the time-frequency distribution circuit and the beam data processing circuit synchronously receive 64 channels of sampling data generated by 16 digital TR components, the 64 channels of sampling data are divided into two groups and are respectively sent to the FPGA1 and the FPGA2, synchronous distribution of local oscillators and clocks is achieved, after the FPGA1 and the FPGA2 form beam data, the high-speed interfaces between the two FPGAs are used for mutually transmitting 32 channels of beam data, independent multi-beam data are formed in the FPGAs respectively, and after 1:1 of the two groups of beam data are completely backed up, the two groups of beam data are sent to the baseband signal processing module through the rear-stage optical module.

5. The digital array beamforming apparatus of claim 4, wherein: the 64-path high-speed signal preprocessing hardware module consists of 2 XC7V690T and 1 XC7Z045-2FFG 676I; the board level support unit is used as a central node of all FPGAs and FLASH to manage the loading of all FPGAs; the FPGA loads in an active synchronous BPI mode, and the board level support unit controls PROG pins of the FPGA and controls loading time sequence; the FPGA programs are respectively stored in NORFLASH with a BPI interface; when the system is powered on, the board-level support unit starts a program loading flow; firstly, providing a low pulse for a PROGRAM_B pin of the FPGA, starting a loading flow of the FPGA, and loading the FPGA to load the PROGRAM according to a parallel active loading mode.

6. The digital array beamforming apparatus of claim 1, wherein: after the program is dynamically updated, the main control unit maintains self-checking to complete comprehensive detection of the working states of the FPGA1 and FPGA2 chips, the working states of the interfaces and the hardware functions of the working voltage modules, and detects the working states, the working temperatures and the working voltages of the chips in two modes of periodic self-checking and maintenance self-checking, and the periodic self-checking is used for completing real-time detection of the hardware functions of the modules, and the detection results are reported.

7. The digital array beamforming apparatus of claim 1, wherein: and the main control unit judges whether the FPGA1 and the FPGA1 programs are successfully loaded, if not, the main control unit returns to the loading of the basic version programs, if so, the main control unit independently detects FLASH, the asynchronous serial bus, DCM, DDR3 and GTH interfaces respectively after the FPGA1 and the FPGA1 are successfully loaded, the working state, the working temperature and the working voltage of the detection chip are detected in two modes of periodic self-detection and maintenance self-detection, the real-time detection of the hardware functions of the modules is completed through the periodic self-detection, and the detection result is reported.

8. The digital array beamforming apparatus of claim 7, wherein: in one mode of self-checking and maintenance self-checking, after the beam forming device is powered on, the main control unit autonomously loads programs to control the FPGA2 and the FPGA1 to load application version programs, after the FPGA1 program is loaded successfully, the FPGA1 operates a normal preprocessing function, after the FPGA2 program is loaded successfully, the FPGA2 operates a normal preprocessing function, if the main control unit receives a periodic self-checking instruction, the self-checking result of the last period is immediately returned, after the self-checking is completed, the self-checking temperature value, the voltage value and other results of the current period are acquired, the self-checking result of the next period is buffered and used as the self-checking result of the next period, in order to improve the real-time performance of the self-checking return of the period, the self-checking return result of the current period is the self-checking result of the last period, and so on.

9. A method for implementing digital array delay measurement using the digital array beam forming device of claim 1, comprising the following technical features: the method comprises the steps that electric signal transmission is used between a digital TR component and a beam forming module, a reference clock generated by a clock source is fed into a time-frequency system, the time-frequency system generates multiple paths of sampling clocks and synchronous Signals (SYNC) generated after distributing sampling according to functional requirements, the multiple paths of sampling clocks and the synchronous signals are distributed to delay measuring modules of different subarrays of a digital array system respectively, and phase relation detection is carried out through the delay measuring modules at synchronous triggering moments among the subarrays to obtain output signals of all channels; the delay measurement module collects two-stage clocks of an excitation channel from a reference signal needing a delay measurement point and each subarray, simultaneously sends the two-stage clocks into a field programmable gate array FPGA, measures the relative delay between a plurality of channels, compares the phase difference of rising edges of two paths of signals in real time, continuously adjusts the delay of a synchronous signal in the process, records the current delay value if the FPGA detects the change of the phase value of the transmission delay of each array element of a digital array in real time, carries out difference frequency processing on the reference signal and linear frequency modulation signals LFM of different delay times, operates a delay algorithm after the difference frequency, carries out delay operation on single-frequency signals related to the measured frequency domain position and the delay time, obtains the relative delay value between the channel to be measured and the reference channel, and calculates the delay time.