CN113506746B - 解决超级结工艺打标区域高台阶差的方法 - Google Patents

解决超级结工艺打标区域高台阶差的方法 Download PDF

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CN113506746B
CN113506746B CN202110718854.3A CN202110718854A CN113506746B CN 113506746 B CN113506746 B CN 113506746B CN 202110718854 A CN202110718854 A CN 202110718854A CN 113506746 B CN113506746 B CN 113506746B
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王绪根
李玉华
谷云鹏
吴长明
姚振海
陈骆
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Hua Hong Semiconductor Wuxi Co Ltd
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures

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Abstract

本发明涉及解决超级结工艺打标区域高台阶差的方法,涉及半导体集成电路技术,包括在超级结深沟槽打标区域进行扫描曝光以及晶片边缘曝光两种曝光工艺,由于在超级结深沟槽打标区域采用scanner和WEE联合曝光,打标位置光刻胶充分曝光,显影后光刻胶完整保留下来,因此在深沟槽刻蚀后不会产生高台阶,打标识别和减薄撕膜也不会出现异常。

Description

解决超级结工艺打标区域高台阶差的方法
技术领域
本发明涉及半导体集成电路技术,尤其涉及一种解决超级结工艺打标区域高台阶差的方法。
背景技术
采用超级结(super junction)结构的MOS器件,由于其构造特殊,可以实现高电压(BV)下的低阻抗(Rdson),同时低的阻抗也意味着低的发热,因此Super junction MOS又称为COOLMOS。
目前现有的超级结的制造方法,容易有硅草(silicon grass)缺陷出现,尤其是晶圆边缘(wafer edge)。目前,为了防止晶圆边缘刻蚀后产生硅草缺陷,光刻工艺时选用负性光刻胶。然,在超级结的形成过程中仍会有较多的难点,比如laser mark(打标)处的两个难题:1)光刻层次Laser mark处曝光,laser mark上有图形会导致晶背减薄(BGBM)处无法读取laser mark,如图1所示现有技术的Laser mark处有图形无法读取示意图;2)光刻层次Laser mark处不曝光,沟槽刻蚀后会留下几十微米的高台阶,如图2所示现有技术的Lasermark处贴膜后撕膜残留示意图。后段晶背减薄(BGBM)贴膜后,撕膜不净,有胶膜残留,会污染后续的制程机台。
发明内容
本发明在于提供一种解决超级结工艺打标区域高台阶差的方法,包括:在超级结深沟槽打标区域进行扫描曝光以及晶片边缘曝光两种曝光工艺。
更进一步的,在超级结深沟槽打标区域进行扫描曝光为:在超级结深沟槽打标区域进行扫描曝光,其余光刻层次的打标区域全不曝光。
更进一步的,在超级结深沟槽打标区域进行扫描曝光以及晶片边缘曝光两种曝光工艺为:先在超级结深沟槽打标区域进行扫描曝光,然后在超级结深沟槽打标区域进行晶片边缘曝光。
更进一步的,晶片边缘为半径从140mm至147mm的区域。
更进一步的,在超级结深沟槽打标区域进行扫描曝光以及晶片边缘曝光两种曝光工艺之前还包括:确认打标区域处撕膜不净的原因和读取失败的原因。
更进一步的,在超级结深沟槽打标区域进行扫描曝光以及晶片边缘曝光两种曝光工艺之后还包括:确认超级结产品在深沟槽光刻ADI后保证打标区域光刻胶全保留。
更进一步的,在超级结深沟槽打标区域进行扫描曝光以及晶片边缘曝光两种曝光工艺之后还包括:进一步保持到BGBM确认无读取失败和撕膜胶残留
附图说明
图1为现有技术的Laser mark处有图形无法读取示意图。
图2为现有技术的Laser mark处贴膜后撕膜残留示意图。
图3为采用本发明的解决超级结工艺打标区域高台阶差的方法的效果示意图。
具体实施方式
下面将结合附图,对本发明中的技术方案进行清楚、完整的描述,显然,所描述的实施例是本发明的一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在不做出创造性劳动的前提下所获得的所有其它实施例,都属于本发明保护的范围。
应当理解,本发明能够以不同形式实施,而不应当解释为局限于这里提出的实施例。相反地,提供这些实施例将使公开彻底和完全,并且将本发明的范围完全地传递给本领域技术人员。在附图中,为了清楚,层和区的尺寸以及相对尺寸可能被夸大,自始至终相同附图标记表示相同的元件。应当明白,当元件或层被称为“在…上”、“与…相邻”、“连接到”或“耦合到”其它元件或层时,其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层,或者可以存在居间的元件或层。相反,当元件被称为“直接在…上”、“与…直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时,则不存在居间的元件或层。应当明白,尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分,这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此,在不脱离本发明教导之下,下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在…下”、“在…下面”、“下面的”、“在…之下”、“在…之上”、“上面的”等,在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白,除了图中所示的取向以外,空间关系术语意图还包括使用和操作中的器件的不同取向。例如,如果附图中的器件翻转,然后,描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此,示例性术语“在…下面”和“在…下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时,单数形式的“一”、“一个”和“所述/该”也意图包括复数形式,除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”,当在该说明书中使用时,确定所述特征、整数、步骤、操作、元件和/或部件的存在,但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时,术语“和/或”包括相关所列项目的任何及所有组合。
本发明一实施例中,在于提供一种解决超级结工艺打标区域高台阶差的方法,具体的,该方法包括:在超级结深沟槽打标区域(SJ deep trench laser mark shot)进行扫描(scanner)曝光以及晶片边缘曝光(WEE)两种曝光工艺。
一实施例中,在超级结深沟槽打标区域(SJ deep trench laser mark shot)进行扫描(scanner)曝光,更具体的为:在超级结深沟槽打标区域(SJ deep trench laser markshot)进行扫描(scanner)曝光,其余光刻层次的打标区域全不曝光。
一实施例中,在超级结深沟槽打标区域(SJ deep trench laser mark shot)进行扫描(scanner)曝光以及晶片边缘曝光(WEE)两种曝光工艺,更具体的为:先在超级结深沟槽打标区域(SJ deep trench laser mark shot)进行扫描(scanner)曝光,然后在超级结深沟槽打标区域(SJ deep trench laser mark shot)进行晶片边缘曝光(WEE)。一实施例中,晶片边缘为半径从140mm至147mm的区域。
如此,由于在超级结深沟槽打标区域采用scanner和WEE联合曝光,打标位置光刻胶充分曝光,显影后光刻胶完整保留下来,因此在深沟槽(deep trench)刻蚀后不会产生高台阶,打标识别和减薄撕膜也不会出现异常。如图3所示为采用本发明的解决超级结工艺打标区域高台阶差的方法的效果示意图,从图3可知,无读取失败和撕膜胶残留。
更进一步的,本发明的解决超级结工艺打标区域高台阶差的方法,在超级结深沟槽打标区域(SJ deep trench laser mark shot)进行扫描(scanner)曝光以及晶片边缘曝光(WEE)两种曝光工艺之前还包括:确认打标区域处撕膜不净的原因和读取失败的原因。
更进一步的,本发明的解决超级结工艺打标区域高台阶差的方法,在超级结深沟槽打标区域(SJ deep trench laser mark shot)进行扫描(scanner)曝光以及晶片边缘曝光(WEE)两种曝光工艺之后还包括:确认超级结产品在深沟槽光刻ADI(显影后检测)后保证打标区域光刻胶全保留。
更进一步的,本发明的解决超级结工艺打标区域高台阶差的方法,在超级结深沟槽打标区域(SJ deep trench laser mark shot)进行扫描(scanner)曝光以及晶片边缘曝光(WEE)两种曝光工艺之后还包括:进一步保持到BGBM确认无读取失败和撕膜胶残留。
最后应说明的是:以上各实施例仅用以说明本发明的技术方案,而非对其限制;尽管参照前述各实施例对本发明进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分或者全部技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (5)

1.一种解决超级结工艺打标区域高台阶差的方法,其特征在于,包括:先在超级结深沟槽打标区域进行扫描曝光,且其余光刻层次的打标区域全不曝光,然后在超级结深沟槽打标区域进行晶片边缘曝光,以使得打标区域光刻胶充分曝光并在显影后完整保留下来。
2.根据权利要求1所述的解决超级结工艺打标区域高台阶差的方法,其特征在于,晶片边缘为半径从140mm至147mm的区域。
3.根据权利要求1所述的解决超级结工艺打标区域高台阶差的方法,其特征在于,在超级结深沟槽打标区域进行扫描曝光以及晶片边缘曝光两种曝光工艺之前还包括:确认打标区域处撕膜不净的原因和读取失败的原因。
4.根据权利要求1所述的解决超级结工艺打标区域高台阶差的方法,其特征在于,在超级结深沟槽打标区域进行扫描曝光以及晶片边缘曝光两种曝光工艺之后还包括:确认超级结产品在深沟槽光刻ADI后保证打标区域光刻胶全保留。
5.根据权利要求1所述的解决超级结工艺打标区域高台阶差的方法,其特征在于,在超级结深沟槽打标区域进行扫描曝光以及晶片边缘曝光两种曝光工艺之后还包括:进一步保持到BGBM确认无读取失败和撕膜胶残留。
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CN102446701A (zh) * 2010-10-12 2012-05-09 上海华虹Nec电子有限公司 改善深沟槽刻蚀后硅片边缘硅尖刺缺陷的方法
CN102608861A (zh) * 2011-01-19 2012-07-25 上海华虹Nec电子有限公司 一种改善硅片周边光刻胶形貌的方法
CN105988311A (zh) * 2015-03-03 2016-10-05 中芯国际集成电路制造(上海)有限公司 一种对准图形及其制作方法
CN106158598A (zh) * 2015-05-14 2016-11-23 瑞萨电子株式会社 半导体器件的制造方法
CN110320760A (zh) * 2019-05-29 2019-10-11 宁波芯健半导体有限公司 一种通过多次曝光保证Wafer ID可识别的曝光方法

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