CN113506549A - Thin film transistor liquid crystal display device operable at a wide range of frame rates - Google Patents
Thin film transistor liquid crystal display device operable at a wide range of frame rates Download PDFInfo
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- 239000011521 glass Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
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- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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Abstract
A thin film transistor liquid crystal display device operable at a wide range of frame rates includes an array of pixels organized in N rows and M columns. Each pixel includes: the first switch transistor, the first storage capacitor, and the storage capacitor adjusting circuit. The storage capacitance of the pixel can be dynamically adjusted by applying a storage capacitance control signal to the pixel to be controlled through the storage capacitance control line. The present invention may allow a device to adjust a display frame rate in real time according to display contents to optimize a balance between display quality and power consumption.
Description
Technical Field
The present invention relates generally to Thin Film Transistor (TFT) Liquid Crystal Display (LCD) devices. More particularly, the present invention relates to a TFT-LCD device operable at a wide range of frame rates and a driving method thereof.
Background
A TFT-LCD device is an active matrix display device comprising a matrix of liquid crystal display pixels individually controlled by an array of TFTs. In a typical TFT-LCD pixel, a layer of liquid crystal is sandwiched between two glass substrates, a pair of electrodes (common electrode and display electrode) is formed on the glass substrates, and an electrostatic field is applied to the liquid crystal with a thin transparent metal such as Indium Tin Oxide (ITO) to manipulate a backlight polarization source. Fig. 1 shows an equivalent circuit of a typical TFT-LCD pixel. A pair of ITO electrodes sandwiching the liquid crystal forms a liquid crystal parallel plate capacitor Clc. Each pixel also includes a TFT which serves as a switching element for actively addressing the pixel and a storage capacitor Cs which serves as a storage element to help maintain the state of the pixel.
Fig. 2 shows a simplified block diagram of a typical TFT-LCD device. To display a video frame, pixels are addressed line by a plurality of gate lines (G1.,. G N) connected to gate terminals of the respective TFTs, and the pixels of the addressed line are driven one by a plurality of data lines (S1.,. S M) connected to source terminals of the respective TFTs, thereby applying an electric field to the liquid crystal of each pixel. The electric field applied to the liquid crystal is maintained by the respective storage capacitor until the next frame.
In general, the display quality of the TFT-LCD display at a certain frame frequency depends on the capacitance of the storage capacitor Cs. If the capacitance of the storage capacitor Cs is not sufficient to hold charge to maintain a stable voltage level, the accuracy of the gray scale of the pixel is affected and flicker may occur. If the capacitance of the storage capacitor Cs is too large, the response speed of the display is limited, and motion blur may occur. For example, for a typical frame rate (e.g., 60Hz), a reservoir capacitor of about 0.5pF may be added to help stabilize the voltage until the next frame period.
In order to achieve a good balance between display quality and power consumption, it is necessary to operate the display device at different frame rates for different display contents. While a low frame rate (e.g., 1Hz) may be sufficient to display still images, it may be beneficial to save power, a high frame rate (e.g., 60Hz or 120Hz) is necessary to display motion video, but results in high power consumption. Therefore, there is a great need for TFT-LCD display designs that can operate over a wide range of frame rates (e.g., from 1Hz to 60/120 Hz).
Disclosure of Invention
An object of the present invention is to provide a TFT-LCD device operable at a wide range of frame rates and a driving method thereof. The present invention may allow a device to adjust a display frame rate in real time according to display contents to optimize a balance between display quality and power consumption.
According to an aspect of the present invention, there is provided a TFT-LCD display device including a pixel array organized in N rows and M columns, the N rows of pixels being divided into K groups; a gate driver configured to select rows of pixels line by line through N scan lines electrically connected to the pixels of the rows; and a source driver configured to control each pixel of the selected pixel row by M data lines electrically connected to the respective columns of pixels. Each pixel includes: a display electrode and a common electrode for applying an electrostatic field to the liquid crystal layer sandwiched therebetween to manipulate transmittance of the liquid crystal layer; a liquid crystal parallel plate capacitor formed by the display electrode and the common electrode; a first switching transistor configured for actively addressing the pixel and having a gate terminal connected to a respective scan line, a source terminal connected to a respective data line, and a drain terminal connected to a display electrode; a first storage capacitor configured to provide a first storage capacitance value to maintain a state of the pixel when the display device operates at a first frame rate, and having a first terminal connected to the display electrode and a second terminal connected to the common electrode; and a storage capacitance adjusting circuit configured to dynamically adjust a storage capacitance of the pixel to provide a second storage capacitance value to maintain a state of the pixel when the display device operates at the second frame rate. The gate driver is further configured to apply storage capacitance control signals to the controlled pixels through the K storage capacitance control lines, respectively, to dynamically adjust the storage capacitances of the pixels.
Drawings
Embodiments of the invention are described in more detail below with reference to the drawings, in which:
FIG. 1 shows an equivalent circuit of a typical TFT-LCD pixel;
FIG. 2 shows a simplified schematic diagram of a typical TFT-LCD device;
FIG. 3 depicts a simplified schematic diagram of a TFT-LCD device according to an embodiment of the invention;
FIG. 4 depicts a detailed circuit diagram of a pixel of the TFT-LCD device shown in FIG. 3;
FIG. 5 illustrates exemplary waveforms of control signals for adjusting the storage capacitance of the TFT-LCD device shown in FIG. 3;
FIG. 6 depicts a simplified schematic diagram of a TFT-LCD device according to another embodiment of the invention;
fig. 7 illustrates an exemplary waveform diagram of a control signal for adjusting a storage capacitor of the TFT-LCD device shown in fig. 6;
FIG. 8 depicts a simplified schematic diagram of a TFT-LCD device according to another embodiment of the invention;
fig. 9 illustrates an exemplary waveform diagram of a control signal for adjusting a storage capacitor of the TFT-LCD device shown in fig. 8;
FIG. 10 depicts a simplified schematic diagram of a TFT-LCD device according to another embodiment of the invention; and
fig. 11 illustrates an exemplary waveform diagram of a control signal for adjusting a storage capacitor of the TFT-LCD device shown in fig. 10.
Detailed Description
In the following description, a TFT-LCD device operable at a wide range of frame rates and a driving method thereof are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions, may be made without departing from the scope and spirit of the invention. Specific details may be omitted so as not to obscure the invention; however, the disclosure is written to enable one of ordinary skill in the art to practice the teachings herein without undue experimentation.
FIG. 3 depicts a simplified schematic diagram of a TFT-LCD device according to an embodiment of the present invention. Fig. 4 depicts a detailed circuit diagram of a pixel of a TFT-LCD device.
See fig. 3 and 4. A TFT-LCD device may include a display panel that includes a two-dimensional array of TFT-LCD pixels organized in N rows and M columns. The TFT-LCD device may further include a gate driver configured to select the pixels line by line through N scan lines (G1, …, G N) electrically connected to the pixels of each row; and a source driver configured to control each pixel of the selected row by M data lines (S [1], …, S [ M ]) electrically connected to the respective columns of pixels.
Alternatively, the gate driver is configured to perform scanning of the pixel rows in a double scanning manner. For example, the display panel may be divided into an odd portion and an even portion, the odd portion includes scan lines G [1], G [3], … G [ N-1], the even portion includes scan lines G [2], G [4], … G [ N ], and the gate driver may scan pixels row by row at both the odd portion and the even portion. That is, the gate driver may simultaneously select the scan lines G1, G3, … G N-1 and then simultaneously select the scan lines G2, G4, … G N during a period of one image frame. The gate driver can also scan G1, … G N line by line.
The gate driver may be further configured to apply control signals to the pixels through N storage capacitance control lines (Ts _ G [1],. Ts _ G [ N ]) electrically connecting the N rows of pixels, respectively, to dynamically adjust the storage capacitances of the pixels. Alternatively, the TFT-LCD device may further include a Gate Array (GOA) -based storage capacitor controller (not shown) configured to apply a control signal to the pixels through N storage capacitor control lines (Ts _ G [1],. Ts _ G [ N ]) electrically connecting the N rows of pixels, respectively, to dynamically adjust the storage capacitors of the pixels.
Each TFT-LCD pixel may include a display electrode and a common electrode for applying an electrostatic field to the liquid crystal layer interposed therebetween to manipulate the transmittance of the liquid crystal layer. The display electrode and the common electrode form a liquid crystal parallel plate capacitor Clc.
The TFT-LCD pixel may also include a first Thin Film Transistor (TFT) T1 for actively addressing the pixel; a first storage capacitor Cs1 for providing a first storage capacitance value to maintain the pixel state when the TFT-LCD device is operated at the first frame rate; and the storage capacitor adjusting circuit is used for dynamically adjusting the storage capacitor of the pixel to provide a second storage capacitor value to maintain the pixel state when the TFT-LCD device operates at a second frame rate.
The TFT Tl may have a gate terminal connected to a corresponding scan line, a source terminal connected to a corresponding data line, and a drain terminal connected to a display electrode. The first storage capacitor Cs1 may have a first terminal connected to the display electrode and a second terminal connected to the common electrode.
Preferably, the storage capacitance adjusting circuit may include a second storage capacitor Cs2 and a switching element, for example, a second switching transistor Ts. The second storage capacitor Cs2 may have a first terminal connected to the source terminal of the second switching transistor Ts and a second terminal connected to the common electrode. The second switching transistor Ts may have a gate terminal connected to a corresponding storage capacitance control line, a source terminal connected to the second storage capacitance Cs2, and a drain terminal connected to the display electrode.
When a low-level voltage is applied to the gate terminal of the transistor Ts, the transistor Ts is turned off, disconnecting the second storage capacitor Cs2 from the display electrode, so that the equivalent storage capacitance of the pixel is equal to the sum of the capacitance values of the liquid crystal parallel plate capacitor Clc and the first storage capacitor Cs1, i.e., Clc + Cs 1. When a high-level voltage is applied to the gate terminal of the transistor Ts, the transistor Ts is turned on to connect the second storage capacitor Cs2 to the display electrode, so that the equivalent storage capacitance of the pixel is equal to the liquid crystal parallel plate capacitor Clc, the sum of the capacitance values of the first storage capacitor Cs1 and the second storage capacitor Cs2, i.e., Clc + Cs1+ Cs 2.
Typically, the liquid crystal parallel plate capacitance Clc can have a capacitance value of 0.1 pF. First reservoir capacitor Cs1 may be selected to have a capacitance of 0.5pF and second reservoir capacitor Cs2 may be selected to have a capacitance of approximately 1 pF. By controlling the transistor Ts to be turned on or off, the TFT-LCD pixel can operate at a low frame rate (e.g., 1Hz) with an equivalent storage capacitance equal to about 1.6 pF; or equivalent reservoir capacitance equal to 0.6pF, operates at high frame rates (e.g., 60 Hz).
Fig. 5 illustrates an exemplary waveform diagram of a control signal for adjusting a storage capacitor of the TFT-LCD device shown in fig. 3. For simplicity, it is assumed that the TFT-LCD device has only 8 rows of pixels, which are scanned through 8 gate lines (G1, …, G8), respectively, and thus has 8 storage capacitor control signals Ts _ G1, Ts _ G2, Ts _.
Refer to fig. 5. When the TFT-LCD apparatus operates at a high frame rate in frame 1, frame 2, and frames 5 to 8, each of the 8 storage capacitance control lines is applied with a control signal voltage of a low level. When the TFT-LCD apparatus operates at a low frame rate in frames 3 to 4, each of the 8 storage capacitor control lines is applied with a control signal voltage of a high level.
Preferably, when the TFT-LCD device operates at a high frame rate, a first common electrode voltage signal Vcom1 may be applied to each common electrode; when the TFT-LCD device operates at a low frame rate, a second common electrode voltage signal Vcom2 may be applied to each common electrode, and the second common electrode voltage signal Vcom2 may have different signal levels from the first common electrode voltage signal Vcom 1.
Preferably, the transition of the control signal of the storage capacitance control line between a low level and a high level is triggered by an event of the corresponding scan signal in an initial frame of the frame sequence of the same frame rate. For example, a transition of the control signal of the storage capacitance control line from a low level to a high level may be triggered by a rising edge of the corresponding scan signal in an initial frame of a sequence of frames at a low frame rate. The transition from high to low may be triggered by a rising edge of a corresponding scan signal in an initial frame of a sequence of frames at a high frame rate. As shown in FIG. 5, the transition of the control signal (Ts _ G1, Ts _ G2, …, Ts _ G8) of the control line from low to high is triggered by the rising edge of the scanning signal applied to the scanning line (G1, G2, …, G8) in frame 3 (i.e., the frame sequence of low frame rate (frame 3 to the initial frame of frame 4)), respectively; the transition of the control signal (Ts _ G1, Ts _ G2, …, Ts _ G8) of the control line from high to low is triggered by a rising edge of a scanning signal applied to the scanning line (G1, G2, …, G8) in frame 5, i.e. the frame sequence of high frame rates (the initial frame of frames 5 to 8), respectively. Alternatively, the transition from high to low may be triggered by the falling edge of the last scan signal in the last frame of the low frame rate. For example, the transition of the control signal (Ts _ G1, Ts _ G2, …, Ts _ G8) of the control line from high to low may be triggered by the falling edge of the scan signal applied to the scan line (G8) in frame 4, respectively.
The N storage capacitor control lines may be divided into K groups, each group sharing a common control signal Ts _ G [ K ], where K is 1, N/K +1, 2N/K +1, … …, (K-1) N/K + 1. In the embodiment shown in FIG. 3, N storage capacitor control lines can be considered as being divided into N groups, i.e., K is equal to N, so that there are N storage capacitor control lines (Ts _ G [1], Ts _ G [2], Ts _ G [ N ]) for respectively controlling the storage capacitors of the pixels in the corresponding row, and the transition of the control signals of the storage capacitor control lines between low level and high level can be considered as being triggered by an event of the scanning signals in the corresponding same group in the initial frame of the frame sequence of the same frame rate.
Fig. 6 depicts a simplified schematic diagram of a TFT-LCD device according to another embodiment of the present invention. The embodiment of FIG. 6 is similar to the embodiment of FIG. 3, except that the N storage capacitor control lines are divided into N/2 groups. That is, K is equal to N/2, i.e., there are N/2 storage capacitor control signals (Ts _ G [1], Ts _ G [3],. Ts _ G [ N-1]), each for controlling the storage capacitors of two rows of pixels. For example, the control signal Ts _ G [1] is used to control the storage capacitance of two rows of pixels (G [1] and G [2]), the control signal Ts _ G [3] is used to control the storage capacitance of two rows of pixels (G [3] and G [4 ]).
Fig. 7 illustrates an exemplary waveform diagram of a control signal for adjusting a storage capacitor of the TFT-LCD device shown in fig. 6. For simplicity, it is assumed that the TFT-LCD device has only 8 rows of pixels, which are scanned by 8 gate lines (G1, …, G8), respectively; and there are 4(K ═ N/2 ═ 8/2) storage capacitor control signals Ts _ G [1], Ts _ G [3], Ts _ G [5], and Ts _ G [7 ].
Refer to fig. 7. When the TFT-LCD apparatus operates at a high frame rate in frames 1 to 2 and frames 5 to 8, a control signal voltage of a low level is applied to each of the 4 storage capacitance control lines. When the TFT-LCD apparatus operates at a low frame rate in frames 3 to 4, each of the 4 storage capacitor control lines is applied with a control signal voltage of a high level.
Similarly, the transition of the control signal of the storage capacitance control line between a low level and a high level is triggered by an event of any one of the scan signals in the corresponding same group in the initial frame of the frame sequence of the same frame rate. For example, a transition of the control signal of the storage capacitance control line from a low level to a high level may be triggered by a rising edge of the corresponding scan signal in an initial frame of a sequence of frames at a low frame rate. The transition from high to low may be triggered by a rising edge of any of the scan signals in a corresponding same group in an initial frame of the sequence of frames at the high frame rate. As shown in FIG. 7, the transition of the control signals (Ts _ G1, Ts _ G3, Ts _ G5, and Ts _ G7) of the control lines from low to high is triggered by the rising edge of the scan signal applied to the scan lines (G1, G3, G5, and G7) in frame 3 (i.e., the frame sequence of low frame rate (the initial frame of frame 3 to frame 4)), respectively; the transition of the control signal (Ts _ G1, Ts _ G3, Ts _ G5 and Ts _ G7) of the control lines from high to low is triggered by a rising edge of any scan signal applied to a scan line (G1 or G2, G3 or G4, G5 or G6 and G7 or G8), respectively, in frame 5, i.e. a frame sequence of high frame rates (the initial frame of frames 5 to 8). Alternatively, the transition from high to low may be triggered by the falling edge of the last scan signal in the last frame of the low frame rate. For example, the transition of the control signals (Ts _ G [1], Ts _ G [3], Ts _ G [5], and Ts _ G [7]) of the control lines from high level to low level may be triggered by the falling edge of the scan signal applied to the scan line (G [8]) in frame 4, respectively.
Fig. 8 depicts a simplified schematic diagram of a TFT-LCD device according to another embodiment of the present invention. The embodiment of FIG. 8 is similar to the embodiment of FIG. 3, except that the N storage capacitor control lines are divided into N/4 groups. That is, K is equal to N/4, i.e., there are N/4 storage capacitor control signals (Ts _ G [1], Ts _ G [5],. Ts _ G [ N-3]), each for controlling four rows of pixels. For example, the control signal Ts _ G1 is used to control the storage capacitance of four rows of pixels (G1-G4), the control signal Ts _ G5 is used to control the storage capacitance of four rows of pixels (G5-G8), and the control signal Ts _ G N-3 is used to control the storage capacitance of four rows of pixels (G N-3-G N).
Fig. 9 illustrates an exemplary waveform diagram of a control signal for adjusting a storage capacitor of the TFT-LCD device shown in fig. 8. For simplicity, it is assumed that the TFT-LCD device has only 8 rows of pixels, which are scanned by 8 gate line signals (G [1], …, G [8]), and 2(K ═ N/4 ═ 8/4) storage capacitor control signals Ts _ G [1] and Ts _ G [5], respectively.
Refer to fig. 9. When the TFT-LCD apparatus operates at a high frame rate in frames 1 to 2 and 5 to 8, each of the 2 storage capacitance control lines is applied with a control signal voltage of a low level. When the TFT-LCD apparatus operates at a low frame rate in frames 3 to 4, each of the 2 storage capacitor control lines is applied with a high level control signal voltage.
Similarly, the transition of the control signal of the storage capacitance control line between a low level and a high level is triggered by an event of any one of the scan signals in the corresponding same group in the initial frame of the frame sequence of the same frame rate. For example, a transition of the control signal of the storage capacitance control line from a low level to a high level may be triggered by a rising edge of the corresponding scan signal in an initial frame of a sequence of frames at a low frame rate. The transition from high to low may be triggered by a rising edge of any of the scan signals in a corresponding same group in an initial frame of the sequence of frames at the high frame rate. As shown in FIG. 9, the transition of the control signals (Ts _ G1 and Ts _ G5) of the control lines from low level to high level is triggered by the rising edge of the scan signal applied to the scan lines (G1 and G5) in frame 3 (i.e., the frame sequence of low frame rate (the initial frame of frame 3 to frame 4)), respectively; the transition of the control signal (Ts _ G1 and Ts _ G5) of the control line from a high level to a low level is triggered by a rising edge of any scan signal applied to the scan line (G1, …, or G4 and G5, …, or G8), respectively, in frame 5 (i.e., the frame sequence of high frame rates (the initial frame of frames 5 to 8)). Alternatively, the transition from high to low may be triggered by the falling edge of the last scan signal in the last frame of the low frame rate. For example, the transition of the control signals (Ts _ G1 and Ts _ G5) of the control lines from a high level to a low level may be triggered by the falling edge of the scan signal applied to the scan line (G8) in frame 4, respectively.
Fig. 10 depicts a simplified schematic diagram of a TFT-LCD device according to another embodiment of the present invention. The N storage capacitor control lines are all controlled by Ts _ G [1], and the embodiment of FIG. 10 is similar to the embodiment of FIG. 3. That is, K is equal to 1, i.e., there are 1 storage capacitor control signals (Ts _ G [1 ]). That is, the storage capacitance control signal (Ts _ G1) is used as a total storage capacitance control signal for controlling the storage capacitances of all the pixels of the TFT-LCD device.
Fig. 11 illustrates an exemplary waveform diagram of a control signal for adjusting a storage capacitor of the TFT-LCD device shown in fig. 10. For simplicity, it is assumed that the TFT-LCD device has only 8 rows of pixels, which are scanned by 8 gate line signals (G [1], …, G [8]), and 1(K ═ N/8 ═ 8/8) storage capacitor control signals Ts _ G [1 ].
Refer to fig. 11. When the TFT-LCD apparatus operates at a high frame rate in frames 1 to 2 and 5 to 8, the storage capacitor control line is applied with a control signal voltage of a low level. When the TFT-LCD apparatus operates at a low frame rate in frames 3 to 4, the storage capacitor control line is applied with a high-level control signal voltage.
Similarly, the transition of the control signal of the storage capacitance control line between a low level and a high level is triggered by an event of any one of the scan signals in the corresponding same group in the initial frame of the frame sequence of the same frame rate. For example, a transition of the control signal of the storage capacitance control line from a low level to a high level may be triggered by a rising edge of the corresponding scan signal in an initial frame of a sequence of frames at a low frame rate. The transition from high to low may be triggered by a rising edge of any of the scan signals in a corresponding same group in an initial frame of the sequence of frames at the high frame rate. As shown in FIG. 11, the transition of the control signal (Ts _ G1) of the control line from low level to high level is triggered by the rising edge of the scan signal applied to the scan line (G1) in frame 3 (i.e., the frame sequence of low frame rate (the initial frame of frame 3 to frame 4)); the transition of the control signal (Ts _ G1) for the control line from a high level to a low level is triggered by the rising edge of any scan signal applied to the scan line (G1, …, or G8) in frame 5 (i.e., the frame sequence for the high frame rate (the initial frame of frames 5 to 8)). Alternatively, the transition from high to low may be triggered by the falling edge of the last scan signal in the last frame of the low frame rate. For example, the transition of the control signal (Ts _ G1) of the control line from a high level to a low level may be triggered by the falling edge of the scan signal applied to the scan line G8) in frame 4.
The embodiments disclosed herein may be implemented using general purpose or special purpose computing devices, computer processors, or electronic circuitry, including but not limited to Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), and other programmable logic devices configured or programmed according to the teachings of the present disclosure. Computer instructions or software code running in a general purpose or special purpose computing device, computer processor, or programmable logic device may be readily made by a practitioner of software or electronics based on the teachings of the present disclosure.
In some embodiments, the invention includes a computer storage medium having stored therein computer instructions or software code that can be used to program a computer or microprocessor to perform any of the processes of the invention. The storage medium may include, but is not limited to, ROM, RAM, flash memory devices, or any type of medium or device suitable for storing instructions, code, and/or data.
It will be understood by those skilled in the art that the foregoing examples are for the purpose of illustrating the principles of operation of the present invention, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use contemplated. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations will be apparent to practitioners skilled in the art.
Claims (11)
1. A thin film transistor liquid crystal display device operable at a wide range of frame rates, comprising:
an array of pixels organized in N rows and M columns, the N rows of pixels being divided into K groups;
a gate driver configured to select rows of pixels line by line through N scan lines electrically connected to the pixels of the rows; and
a source driver configured to control each pixel of the selected pixel row by M data lines electrically connected to the respective columns of pixels;
wherein each of the pixels includes:
a display electrode and a common electrode for applying an electrostatic field to a liquid crystal layer sandwiched therebetween to manipulate transmittance of the liquid crystal layer;
a liquid crystal parallel plate capacitor formed by the display electrode and the common electrode;
a first switching transistor configured for actively addressing the pixel and having a gate terminal connected to a respective scan line, a source terminal connected to a respective data line, and a drain terminal connected to the display electrode;
a first storage capacitor configured to provide a first storage capacitance value to maintain a state of the pixel when the display device operates at a first frame rate, and having a first terminal connected to the display electrode and a second terminal connected to the common electrode; and
a storage capacitance adjustment circuit configured to dynamically adjust a storage capacitance of the pixel to provide a second storage capacitance value to maintain a state of the pixel when the display device is operating at a second frame rate; and
wherein the gate driver is further configured to apply storage capacitance control signals to the controlled pixels through the K storage capacitance control lines, respectively, to dynamically adjust the storage capacitances of the pixels.
2. The display device according to claim 1, wherein the first frame rate is higher than the second frame rate; and the first storage capacitance is less than the second storage capacitance.
3. The display device according to claim 2, wherein the storage capacitance adjusting circuit includes a second storage capacitor and a second switching transistor;
the second switching transistor has a gate terminal connected to a corresponding storage capacitance control line, a source terminal connected to the second storage capacitance, and a drain terminal connected to the display electrode; and
the second storage capacitor has a first terminal connected to a source terminal of the second switching transistor and a second terminal connected to the common electrode.
4. The display device of claim 3, wherein the gate driver is further configured to:
applying a low level control signal to each of the storage capacitance control lines to turn off the second switching transistor so that the equivalent storage capacitance of the pixel is equal to the sum of the capacitance value of the liquid crystal parallel plate capacitor and the capacitance value of the first storage capacitor when the display device is operated at the first frame rate; and
when the display device operates at the second frame rate, applying a high-level control signal to each storage capacitance control line to turn on the second switching transistor so that the equivalent storage capacitance of the pixel is equal to the capacitance value of the liquid crystal parallel plate capacitor, and the capacitance value of the first storage capacitor is the sum of the capacitance values of the second storage capacitors.
5. The display device according to claim 4, wherein the transition of the control signal applied to each of said storage capacitance control lines between said low and high level control signals is triggered by an event of a scanning signal in a corresponding same group in an initial frame of a frame sequence of the same frame rate.
6. The display device according to claim 5, the event of the scan signal in the respective same group being a rising edge of the scan signal in the respective same group.
7. The display device of claim 6, wherein the gate driver is further configured to:
applying a first common electrode voltage signal to each of the common electrodes when the display device is operating at the first frame rate;
when the display device operates at the second frame rate, a second common electrode voltage signal is applied to each common electrode, and the second common electrode voltage signal may be different from the first common electrode voltage signal.
8. A display device according to any one of claims 1 to 7, wherein K is equal to N.
9. Display device according to any one of claims 1 to 7, wherein K is equal to N/2.
10. Display device according to any one of claims 1 to 7, wherein K is equal to N/4.
11. A display device according to any one of claims 1 to 7, wherein K is equal to 1.
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