CN108986755B - Time schedule controller and display device - Google Patents
Time schedule controller and display device Download PDFInfo
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- CN108986755B CN108986755B CN201810779259.9A CN201810779259A CN108986755B CN 108986755 B CN108986755 B CN 108986755B CN 201810779259 A CN201810779259 A CN 201810779259A CN 108986755 B CN108986755 B CN 108986755B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
Abstract
The invention provides a time schedule controller and a display device. The time schedule controller comprises a storage module, an enabling signal regeneration module and a selection output module. The input enabling signal is detected by the enabling signal regenerating module, the waveform burr-free conversion enabling signal is generated to serve as the reading enabling of the storage module, the display picture abnormity caused by the burr existing in the input enabling signal can be eliminated, meanwhile, if no effective video input exists within a preset time period, the enabling signal regenerating module controls the selection output module to output null data, and the display picture abnormity caused by sudden disappearance of video data can be eliminated.
Description
Technical Field
The invention relates to the technical field of display, in particular to a time schedule controller and a display device.
Background
With the development of Display technology, flat panel Display devices such as Liquid Crystal Displays (LCDs) have advantages of high image quality, power saving, thin body, and wide application range, and thus are widely used in various consumer electronics products such as mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, and desktop computers, and become the mainstream of Display devices.
Most of the existing liquid crystal displays in the market are backlight type liquid crystal displays (lcds) including a liquid crystal panel and a backlight module (backlight module). The liquid crystal panel operates on the principle that liquid crystal molecules are filled between a Thin film transistor Array Substrate (TFT Array Substrate) and a Color Filter Substrate (Color Filter, CF), and driving voltages are applied to the two substrates to control the rotation direction of the liquid crystal molecules, so that light rays of the backlight module are refracted out to generate a picture.
In the active liquid crystal display, each pixel is electrically connected with a Thin Film Transistor (TFT), a Gate (Gate) of the TFT is connected to a horizontal scanning line, a Source (Source) is connected to a data line in a vertical direction, and a Drain (Drain) is connected to a pixel electrode. Applying sufficient voltage to the horizontal scanning lines can turn on all TFTs electrically connected to the horizontal scanning lines, so that signal voltage on the data lines can be written into the pixels, and the transmittance of different liquid crystals can be controlled, thereby achieving the effect of controlling color and brightness.
In order to drive the lcd panel to emit light, a Timing Controller (TCON) electrically connected to the lcd panel is generally disposed in the prior art, and the TCON is used for receiving video data and generating a specific timing sequence to control charging and discharging of pixels of the lcd panel and display corresponding video data.
In the actual use process of the liquid crystal display device, various interferences exist, so that the video data signals transmitted to the time schedule controller have burrs, or the video data disappear suddenly, which causes abnormal display of the liquid crystal display device. The existing time schedule controller has limited capability of processing video data abnormity, and the quality of products is lower.
Disclosure of Invention
The invention aims to provide a time schedule controller which can eliminate the display picture abnormity caused by the burr of an input enabling signal and the sudden disappearance of video data.
It is another object of the present invention to provide a display device capable of eliminating display screen abnormalities caused by glitches in input enable signals and sudden disappearance of video data.
In order to achieve the above object, the present invention provides a timing controller, including a memory module, an enable signal regeneration module electrically connected to the memory module, and a selection output module electrically connected to both the memory module and the enable signal regeneration module;
the storage module is accessed to input enabling signals and video data; the enabling signal regenerating module is connected with an input enabling signal, outputs a conversion enabling signal to the storage module and outputs a control signal to the selection output module; the selection output module accesses null data;
when the rising edge of the input enabling signal arrives and the time length of keeping the low potential of the input enabling signal before the rising edge arrives is greater than or equal to a preset first time length, the enabling signal regenerating module judges the potential of the conversion enabling signal at the moment when a preset second time length passes after the rising edge moment, if the conversion enabling signal is the low potential, the enabling signal regenerating module enables the conversion enabling signal to be the high potential and to be the low potential after maintaining a preset third time length, and enables the control signal to be the first potential, otherwise, the enabling signal regenerating module keeps the current potentials of the conversion enabling signal and the control signal; when the duration of keeping the low potential of the input enabling signal is longer than the preset fourth duration, the enabling signal regenerating module enables the control signal to be the second potential and enables the conversion enabling signal to be the high potential and maintains the third duration; the fourth duration is greater than the first duration and less than the sum of the first duration and the third duration;
the storage module stores video data when the input enabling signal is at a high potential, and outputs the stored video data to the selection output module when the input enabling signal is at the high potential;
the selective output module outputs video data transmitted by the storage module when the control signal is at a first potential, and outputs null data when the control signal is at a second potential.
The enabling signal regenerating module judges whether the input enabling signal has a rising edge when the control signal is at the second potential and the conversion enabling signal is at the high potential, if so, the enabling signal regenerating module changes the conversion enabling signal into the low potential and changes the control signal into the first potential after the control signal is at the second potential and the conversion enabling signal is at the high potential and maintains the third time length, and if not, the enabling signal regenerating module continues to change the control signal into the second potential and continues to change the conversion enabling signal into the high potential and maintains the third time length after the control signal is at the second potential and the conversion enabling signal is at the high potential and maintains the third time length.
The second duration is greater than 0 and less than the sum of the first duration and the third duration.
The first potential is a low potential and the second potential is a high potential.
The time schedule controller also comprises a write address generating module electrically connected with the enabling signal regenerating module and the storage module and a read address generating module electrically connected with the enabling signal regenerating module and the storage module;
the write address generation module is accessed to an input enabling signal; the enabling signal regenerating module outputs a conversion enabling signal to the storage module and also outputs the conversion enabling signal to the read address generating module.
The storage module is provided with a plurality of storage units which are arranged in sequence;
when a rising edge of an input enabling signal arrives and the duration of keeping a low potential of the input enabling signal before the rising edge arrives is greater than or equal to a preset first duration, in a stage that the duration after the rising edge moment is a third duration, a writing address generating module sequentially transmits a plurality of writing addresses corresponding to a plurality of storage units to a storage module, and the storage module correspondingly stores video data into the plurality of storage units according to the plurality of writing addresses transmitted by the writing address generating module when the input enabling signal is at a high potential;
in a stage that the time length is a third time length after the rising edge time of the conversion enabling signal, the reading address generating module sequentially transmits a plurality of reading addresses corresponding to the plurality of storage units to the storage module, so that the storage module sequentially reads video data stored in the plurality of storage units and transmits the video data to the selection output module when the conversion enabling signal is at a high potential.
The empty data is video data corresponding to a black picture.
The video data corresponding to the black frame is the video data of which the gray scales of the red sub-pixel, the green sub-pixel and the blue sub-pixel are all 0.
The storage module is a random access memory.
The invention also provides a display device which comprises the time sequence controller.
The invention has the beneficial effects that: the time schedule controller comprises a storage module, an enabling signal regeneration module and a selection output module. The input enabling signal is detected by the enabling signal regenerating module, the waveform burr-free conversion enabling signal is generated to serve as the reading enabling of the storage module, the display picture abnormity caused by the burr existing in the input enabling signal can be eliminated, meanwhile, if no effective video input exists within a preset time period, the enabling signal regenerating module controls the selection output module to output null data, and the display picture abnormity caused by sudden disappearance of video data can be eliminated. The display device of the invention can eliminate the display picture abnormity caused by the burr of the input enabling signal and the sudden disappearance of the video data.
Drawings
For a better understanding of the nature and technical aspects of the present invention, reference should be made to the following detailed description of the invention, taken in conjunction with the accompanying drawings, which are provided for purposes of illustration and description and are not intended to limit the invention.
In the drawings, there is shown in the drawings,
FIG. 1 is a schematic diagram of a timing controller according to the present invention;
FIG. 2 is a timing diagram of the timing controller according to the present invention when the input enable signal has glitches;
FIG. 3 is a timing diagram of the timing controller according to the present invention when the input enable signal suddenly disappears.
Detailed Description
To further illustrate the technical means and effects of the present invention, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Referring to fig. 1 to 3, the present invention provides a timing controller, which includes a memory module 10, an enable signal regeneration module 20 electrically connected to the memory module 10, and a selection output module 30 electrically connected to both the memory module 10 and the enable signal regeneration module 20.
The memory module 10 accesses the input enable signal de1 and the video data. The enable signal regeneration module 20 receives the input enable signal de1, and outputs a conversion enable signal de2 to the memory module 10 and a control signal ctrl to the selection output module 30. The selection output module 30 accesses the dummy data 0.
Referring to fig. 2 and 3, when the rising edge of the input enable signal de1 arrives and the duration of the input enable signal de1 keeping the low potential is greater than or equal to the preset first duration before the rising edge arrives, at the time when the preset second duration passes after the rising edge time, the enable signal regeneration module 20 determines the potential of the conversion enable signal de2, and if the conversion enable signal de2 is the low potential as shown in fig. 2, the enable signal regeneration module 20 makes the conversion enable signal de2 be the high potential and change to the low potential after keeping the preset third duration, and makes the control signal ctrl be the first potential, otherwise, as shown in fig. 3, the enable signal regeneration module 20 keeps the current potentials of the conversion enable signal de2 and the control signal ctrl. As shown in fig. 3, when the duration that the input enable signal de1 remains low is longer than the preset fourth duration, which indicates that there is a sudden disappearance of the input enable signal de1, the enable signal regenerating module 20 makes the control signal ctrl at the second potential and makes the transition enable signal de2 at high and maintains the third duration. The fourth duration is greater than the first duration and less than a sum of the first duration and the third duration.
The memory module 10 stores the video data when the input enable signal de1 is at a high voltage level, and outputs the stored video data to the selection output module 30 when the conversion enable signal de2 is at a high voltage level.
The selection output module 30 outputs the video data transmitted by the memory module 10 when the control signal ctrl is at the first voltage level, and outputs the dummy data0 when the control signal ctrl is at the second voltage level.
Specifically, referring to fig. 3, the enable signal regenerating module 20 determines whether the input enable signal de1 has a rising edge when the control signal ctrl is at the second potential and the conversion enable signal de2 is at the high potential, if so, the input enable signal de1 has recovered to be normal, as shown in fig. 3, the enable signal regenerating module 20 changes the conversion enable signal de2 to the low potential and the control signal ctrl to the first potential after the control signal ctrl is at the second potential and the conversion enable signal de2 is at the high potential and maintains the third time period, and if not, the input enable signal de1 still disappears, the enable signal regenerating module 20 continues to make the control signal ctrl at the second potential and continue to make the conversion enable signal de2 at the high potential and maintains the third time period after the control signal ctrl is at the second potential and the conversion enable signal de2 is at the high potential, the above steps are repeated until the input enable signal de1 generates a rising edge when the control signal ctrl is at the second potential and the conversion enable signal de2 is at the high potential.
Specifically, the second duration is greater than 0 and less than the sum of the first duration and the third duration.
Preferably, the first potential is a low potential and the second potential is a high potential.
Specifically, referring to fig. 2, the timing controller further includes a write address generating module 40 electrically connected to the enable signal regenerating module 20 and the memory module 10, and a read address generating module 50 electrically connected to the enable signal regenerating module 20 and the memory module 10.
The write address generation module 40 accesses the input enable signal de 1. The enable signal regeneration module 20 outputs the conversion enable signal de2 to the memory module 10 and also outputs the conversion enable signal de2 to the read address generation module 50.
Further, the memory module 10 has a plurality of memory cells arranged in sequence.
When the rising edge of the input enable signal de1 arrives and the duration of the input enable signal de1 keeping the low voltage is greater than or equal to the preset first duration before the rising edge arrives, in a stage that the duration after the rising edge is the third duration, the write address generation module 40 sequentially transmits a plurality of write addresses corresponding to the plurality of storage units to the storage module 10, and the storage module 10 correspondingly stores the video data into the plurality of storage units according to the plurality of write addresses transmitted by the write address generation module 40 when the input enable signal de1 is at the high voltage. In a stage that the time length after the rising edge of the conversion enable signal de2 is the third time length, the read address generating module 50 sequentially transmits a plurality of read addresses corresponding to the plurality of memory cells to the memory module 10, so that the memory module 10 sequentially reads the video data stored in the plurality of memory cells and transmits the video data to the selection output module 30 when the conversion enable signal de2 is at a high potential.
Preferably, the blank data0 is video data corresponding to a black frame. The video data corresponding to the black frame is the video data of which the gray scales of the red sub-pixel, the green sub-pixel and the blue sub-pixel are all 0.
Preferably, the memory module 10 is a Random Access Memory (RAM).
Preferably, the memory module 10, the enable signal regeneration module 20, the write address generation module 40, and the read address generation module 50 are all further connected to clock signals, the clock signals are pulse signals, the first duration is K times the period of the clock signals, the second duration is L times the period of the clock signals, the third duration is M times the period of the clock signals, and the fourth duration is N times the period of the clock signals, where K is greater than 0, L is greater than or equal to 0, M is greater than 0, and N is greater than 0.
It should be noted that the timing controller of the present invention utilizes the input enable signal de1 as the write enable of the memory module 10 to control the memory module 10 to buffer the video data, and utilizes the enable signal regeneration module 20 to detect the input enable signal de1, if there is no situation where the input enable signal de1 disappears, no matter whether the enable signal de1 has glitch, the enable signal regeneration module 20 will enable the conversion enable signal de2 to generate a high level pulse with a third duration at a time interval of a second duration after the rising edge time of the input enable signal de1 to be used as the read enable of the memory module 10, control the memory module 10 to read the video data stored therein and transmit the video data to the selection output module 30, and enable the enable signal regeneration module 20 further makes the control signal ctrl be the first potential, the selection output module 30 outputs the video data transmitted by the memory module 10 under the control of the first potential ctrl, therefore, the display screen abnormity generated due to the burr of the input enable signal de1 can be eliminated. If the duration of keeping the low voltage of the input enable signal de1 is longer than the preset fourth duration, which indicates that the input enable signal de1 disappears, at this time, the enable signal regeneration module 20 makes the control signal ctrl at the second voltage level and makes the conversion enable signal de2 at the high voltage level and maintains the third duration, and the selection output module 30 outputs the empty data0 under the control of the control signal ctrl at the second voltage level, so that the timing controller can output the empty data after the input enable signal de1 disappears suddenly, and the abnormal display picture caused by the sudden disappearance of the video data can be eliminated. Further, the enable signal regenerating module 20 determines whether the input enable signal de1 has a rising edge when the control signal ctrl is at the second potential and the conversion enable signal de2 is at the high potential, that is, whether the input enable signal de1 returns to normal, if so, it indicates that the input enable signal de1 has returned to normal, the enable signal regenerating module 20 changes the conversion enable signal de2 to a low potential and the control signal ctrl to a first potential after the control signal ctrl is at the second potential and the conversion enable signal de2 is at the high potential and maintains a third time period, if not, it indicates that the input enable signal de1 still disappears, the enable signal regenerating module 20 continues to make the control signal ctrl at the second potential and continue to make the conversion enable signal 2 at the high potential and maintains the third time period after the control signal ctrl is at the second potential and the conversion enable signal de2 is at the high potential, the above steps are repeated until the input enable signal de1 generates a rising edge, that is, the input enable signal de1 is recovered to be normal when the control signal ctrl is at the second potential and the conversion enable signal de2 is at the high potential, so that the selection output module 30 can continuously output the blank data0 in the process that the input enable signal de1 continuously disappears, and the normal display of the picture is ensured.
Based on the same inventive concept, the invention also provides a display device comprising the time sequence controller. The structure of the timing controller will not be described repeatedly herein. The display device can be a liquid crystal display device or other display devices in the prior art which need to be provided with a time schedule controller.
The timing controller of the display device of the present invention utilizes the input enable signal de1 as the write enable of the memory module 10 to control the memory module 10 to buffer the video data, and utilizes the enable signal regeneration module 20 to detect the input enable signal de1, if the input enable signal de1 does not disappear, no matter whether the enable signal de1 has glitch, the enable signal regeneration module 20 will make the conversion enable signal de2 generate a high level pulse with a third duration at a time spaced by a second duration after the rising edge time of the input enable signal de1 to be used as the read enable of the memory module 10, control the memory module 10 to read the video data stored therein and transmit the same to the selection output module 30, and make the enable signal regeneration module 20 further make the control signal ctrl be a first potential, the selection output module 30 outputs the video data transmitted by the memory module 10 under the control of the control signal ctrl at the first potential, therefore, the display screen abnormity generated due to the burr of the input enable signal de1 can be eliminated. If the duration of keeping the low voltage of the input enable signal de1 is longer than the preset fourth duration, which indicates that the input enable signal de1 disappears, at this time, the enable signal regeneration module 20 makes the control signal ctrl at the second voltage level and makes the conversion enable signal de2 at the high voltage level and maintains the third duration, and the selection output module 30 outputs the empty data0 under the control of the control signal ctrl at the second voltage level, so that the timing controller can output the empty data after the input enable signal de1 disappears suddenly, and the abnormal display picture caused by the sudden disappearance of the video data can be eliminated. Further, the enable signal regenerating module 20 determines whether the input enable signal de1 has a rising edge when the control signal ctrl is at the second potential and the conversion enable signal de2 is at the high potential, that is, whether the input enable signal de1 returns to normal, if so, it indicates that the input enable signal de1 has returned to normal, the enable signal regenerating module 20 changes the conversion enable signal de2 to a low potential and the control signal ctrl to a first potential after the control signal ctrl is at the second potential and the conversion enable signal de2 is at the high potential and maintains a third time period, if not, it indicates that the input enable signal de1 still disappears, the enable signal regenerating module 20 continues to make the control signal ctrl at the second potential and continue to make the conversion enable signal 2 at the high potential and maintains the third time period after the control signal ctrl is at the second potential and the conversion enable signal de2 is at the high potential, the above steps are repeated until the input enable signal de1 generates a rising edge, that is, the input enable signal de1 is recovered to be normal when the control signal ctrl is at the second potential and the conversion enable signal de2 is at the high potential, so that the selection output module 30 can continuously output the blank data0 in the process that the input enable signal de1 continuously disappears, and the normal display of the picture is ensured.
In summary, the timing controller of the present invention includes a storage module, an enable signal regeneration module, and a selection output module. The input enabling signal is detected by the enabling signal regenerating module, the waveform burr-free conversion enabling signal is generated to serve as the reading enabling of the storage module, the display picture abnormity caused by the burr existing in the input enabling signal can be eliminated, meanwhile, if no effective video input exists within a preset time period, the enabling signal regenerating module controls the selection output module to output null data, and the display picture abnormity caused by sudden disappearance of video data can be eliminated. The display device of the invention can eliminate the display picture abnormity caused by the burr of the input enabling signal and the sudden disappearance of the video data.
As described above, it will be apparent to those skilled in the art that other various changes and modifications may be made based on the technical solution and concept of the present invention, and all such changes and modifications are intended to fall within the scope of the appended claims.
Claims (9)
1. A time schedule controller is characterized by comprising a storage module (10), an enabling signal regenerating module (20) electrically connected with the storage module (10) and a selection output module (30) electrically connected with both the storage module (10) and the enabling signal regenerating module (20);
the storage module (10) is accessed to an input enabling signal (de1) and video data (data); the enabling signal regeneration module (20) is connected with an input enabling signal (de1), outputs a conversion enabling signal (de2) to the storage module (10) and outputs a control signal (ctrl) to the selection output module (30); the selection output module (30) accesses null data (data 0);
when the rising edge of the input enabling signal (de1) arrives and the duration of keeping the low potential of the input enabling signal (de1) before the rising edge arrives is greater than or equal to a preset first duration, at the time when a preset second duration passes after the rising edge, the enabling signal regeneration module (20) judges the potential of the conversion enabling signal (de2), if the conversion enabling signal (de2) is low, the enabling signal regeneration module (20) enables the conversion enabling signal (de2) to be high and to be low after keeping a preset third duration, and the control signal (ctrl) is the first potential, otherwise, the enabling signal regeneration module (20) keeps the current potentials of the conversion enabling signal (de2) and the control signal (ctrl); when the duration of keeping the low potential of the input enable signal (de1) is longer than the preset fourth duration, the enable signal regeneration module (20) enables the control signal (ctrl) to be at the second potential and enables the conversion enable signal (de2) to be at the high potential and maintains the third duration; the fourth duration is greater than the first duration and less than the sum of the first duration and the third duration;
the storage module (10) stores the video data (data) when the input enable signal (de1) is at a high potential, and outputs the stored video data (data) to the selection output module (30) when the conversion enable signal (de2) is at a high potential;
the selection output module (30) outputs the video data (data) transmitted by the storage module (10) when the control signal (ctrl) is at a first potential, and outputs the dummy data (data0) when the control signal (ctrl) is at a second potential;
the enable signal regeneration module (20) determines whether the input enable signal (de1) has a rising edge when the control signal (ctrl) is at the second potential and the conversion enable signal (de2) is at the high potential, if so, the enable signal regeneration module (20) changes the conversion enable signal (de2) to the low potential and the control signal (ctrl) to the first potential after the control signal (ctrl) is at the second potential and the conversion enable signal (de2) is at the high potential and the third duration is maintained, and if not, the enable signal regeneration module (20) continues to make the control signal (ctrl) at the second potential and the conversion enable signal (de2) to the high potential and the third duration after the control signal (ctrl) is at the second potential and the conversion enable signal (de2) is at the high potential and the third duration is maintained.
2. The timing controller of claim 1, wherein the second duration is greater than 0 and less than a sum of the first duration and the third duration.
3. The timing controller of claim 1, wherein the first potential is a low potential and the second potential is a high potential.
4. The timing controller of claim 1, further comprising a write address generating module (40) electrically connected to both the enable signal regenerating module (20) and the memory module (10), and a read address generating module (50) electrically connected to both the enable signal regenerating module (20) and the memory module (10);
the write address generation module (40) accesses an input enabling signal (de 1); the enable signal regeneration module (20) outputs a conversion enable signal (de2) to the memory module (10) and also outputs a conversion enable signal (de2) to the read address generation module (50).
5. The timing controller according to claim 4, wherein the memory module (10) has a plurality of sequentially arranged memory cells;
when the rising edge of the input enabling signal (de1) arrives and the duration of keeping the low potential of the input enabling signal (de1) before the rising edge arrives is greater than or equal to a preset first duration, in a stage that the duration is a third duration after the rising edge moment, the writing address generating module (40) sequentially transmits a plurality of writing addresses corresponding to a plurality of storage units to the storage module (10), and when the input enabling signal (de1) is at a high potential, the storage module (10) correspondingly stores the video data (data) into the plurality of storage units according to the plurality of writing addresses transmitted by the writing address generating module (40);
in a stage that the time length is a third time length after the rising edge time of the conversion enabling signal (de2), the reading address generating module (50) sequentially transmits a plurality of reading addresses corresponding to the plurality of storage units to the storage module (10), so that the storage module (10) sequentially reads video data (data) stored in the plurality of storage units and transmits the video data to the selection output module (30) when the conversion enabling signal (de2) is at a high potential.
6. The timing controller of claim 1, wherein the dummy data (data0) is video data corresponding to a black frame.
7. The timing controller of claim 6, wherein the video data corresponding to the black frame is video data having a gray level of red sub-pixel, a gray level of green sub-pixel, and a gray level of blue sub-pixel all equal to 0.
8. The timing controller according to claim 1, wherein the memory module (10) is a random access memory.
9. A display device comprising the timing controller according to any one of claims 1 to 8.
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| CN109712564A (en) * | 2019-02-25 | 2019-05-03 | 京东方科技集团股份有限公司 | Driving method, driving circuit and display device |
| CN110767179B (en) * | 2019-06-10 | 2020-11-24 | 惠科股份有限公司 | Backlight control method, driving module and display device |
| CN112150953B (en) * | 2019-06-26 | 2022-04-15 | 京东方科技集团股份有限公司 | Display device and display method thereof |
| CN111540296B (en) * | 2020-05-18 | 2023-01-10 | Tcl华星光电技术有限公司 | Time schedule controller and display device |
| CN112201194B (en) * | 2020-10-21 | 2022-08-23 | Tcl华星光电技术有限公司 | Display panel and display device |
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Address after: 518132 No. 9-2 Ming Avenue, Guangming New District, Guangdong, Shenzhen Patentee after: TCL Huaxing Photoelectric Technology Co.,Ltd. Address before: 518132 No. 9-2 Ming Avenue, Guangming New District, Guangdong, Shenzhen Patentee before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |