CN113488537A - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the same Download PDFInfo
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- CN113488537A CN113488537A CN202110580071.3A CN202110580071A CN113488537A CN 113488537 A CN113488537 A CN 113488537A CN 202110580071 A CN202110580071 A CN 202110580071A CN 113488537 A CN113488537 A CN 113488537A
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- 230000000903 blocking effect Effects 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims description 32
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
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- H01L27/0203—Particular design considerations for integrated circuits
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Abstract
In the semiconductor device and the forming method thereof, when the first ion implantation process is executed on the low-voltage device area based on the laminated first grid and the first mask structure, the ion blocking capability of the first grid area can be enhanced by using the first mask structure; meanwhile, when a second ion implantation process is performed on the high-voltage device region based on the stacked second gate and the second mask structure, the second mask structure can be used for making up the defect of ion blocking capability of the second gate for second ion implantation. Therefore, the thicknesses of the first grid electrode and the second grid electrode are the same, the ion implantation performance of the low-voltage device area and the high-voltage device area is better, and the performance of the high-voltage device and the low-voltage device can be improved.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for forming the same.
Background
With the continuous development of science and technology, more and more electronic devices are widely applied to daily life and work of people, bring convenience to daily life and work of people, and become an indispensable important tool for people at present.
Semiconductor devices are the main components of integrated circuits for electronic devices implementing various functions. With the development of integrated circuits, single chip system integration is becoming a trend; such as integrating power management circuitry or memory circuitry on the same chip. In order to realize the setting function and the performance parameter, it is necessary to adopt a semiconductor device having both a high-voltage device (such as a high-voltage MOS) function and a low-voltage device (such as a low-voltage MOS). Thus, a high voltage device region and a low voltage device region need to be integrated into a single semiconductor device to implement the functions of the high voltage device and the low voltage device, respectively.
In the prior art, when manufacturing the semiconductor device, the high-voltage device region usually needs to adopt a gate layer with a larger thickness, so as to block the larger energy implantation when performing the higher energy implantation to form the doped region on both sides of the gate layer. In contrast, the low-voltage device region generally uses a thinner gate layer to achieve faster device response speed. And the gate layers respectively located in the low-voltage device region and the high-voltage device region have different thicknesses, so that the high-voltage device and the low-voltage device are difficult to integrate. In order to solve the problem, in the prior art, a gate layer generally adopts a compromise thickness, the thickness is smaller than an optimal thickness for blocking larger energy injection in a high-voltage device region and larger than an optimal thickness for realizing a faster device response speed in a low-voltage device region, which may cause a certain reduction in the performance of both the high-voltage device region and the low-voltage device region, and thus the overall performance of a semiconductor device is poor.
Disclosure of Invention
The invention aims to provide a method for forming a semiconductor device and aims to solve the problem that the overall performance of the semiconductor device is poor when the conventional high-voltage device and low-voltage device are integrated.
In order to solve the above technical problem, the present invention provides a method for forming a semiconductor device, the method comprising:
providing a substrate, wherein the substrate comprises a low-voltage device area and a high-voltage device area;
forming a patterned gate layer and a hard mask layer on the substrate, wherein the gate layer comprises a first gate and a second gate which are equal in thickness, the first gate is located in the low-voltage device area, the second gate is located in the high-voltage device area, the hard mask layer comprises a first mask structure and a second mask structure, the first mask structure is located on the first gate and aligned with the first gate, and the second mask structure is located on the second gate and aligned with the second gate;
performing a first ion implantation process on the low-voltage device region based on the first mask structure and the first grid electrode to form first doped regions in the substrate on two sides of the first grid electrode;
and performing a second ion implantation process on the high-voltage device region based on the second mask structure and the second grid electrode so as to form second doped regions in the substrate at two sides of the second grid electrode.
Optionally, the ion implantation energy of the second ion implantation process is higher than that of the first ion implantation process.
Optionally, the width of the first gate is 40nm to 1000nm, and the width of the second gate is 500nm to 2000 nm.
Optionally, the method for forming the gate layer and the hard mask layer includes:
sequentially forming a grid material layer, a hard mask material layer and a patterned sacrificial layer on the substrate;
and sequentially etching the hard mask material layer and the grid material layer by taking the sacrificial layer as a mask to form a hard mask layer and a grid layer, wherein the grid layer comprises a first grid and a second grid which are equal in thickness, and the hard mask layer comprises a first mask structure aligned with the first grid and a second mask structure aligned with the second grid.
Optionally, before performing the first ion implantation process, the method further includes: and forming a first blocking structure in the high-voltage device area, wherein the first blocking structure covers the second hard mask layer and the second gate and is positioned on the substrate of the high-voltage device area.
Optionally, before performing the second ion implantation process, the method further includes: and forming a second blocking structure in the low-voltage device area, wherein the second blocking structure covers the first hard mask layer and the first grid and is positioned on the substrate of the low-voltage device area.
Optionally, before forming the gate layer, the method further includes:
and forming a gate oxide layer on the substrate, wherein the thickness of the gate oxide layer positioned in the low-voltage device area is smaller than that of the gate oxide layer positioned in the high-voltage device area.
Optionally, the thickness of the gate layer is:
optionally, after forming the first doped region and the second doped region, the method further includes:
removing the first mask structure and the second mask structure, and forming side walls on the side walls of the first grid electrode and the second grid electrode;
and performing ion implantation on the basis of the first grid and the side wall positioned on the side wall of the first grid to form a third doped region, and performing ion implantation on the basis of the second grid and the side wall positioned on the side wall of the second grid to form a fourth doped region.
In order to solve the above problems, the present invention also provides a semiconductor device manufactured by the semiconductor device forming method as described in any one of the above.
In the forming method of the semiconductor device, the first ion implantation process is performed on the low-voltage device area by utilizing the first grid electrode and the first mask structure which are arranged in a stacked mode, so that the blocking capability of the first grid electrode on ions is enhanced; and a second ion implantation process with high energy is executed on the high-voltage device area based on the stacked second grid and the second mask structure, so that the defect of the ion blocking capability of the second grid to the second ion implantation can be made up by using the second mask structure, and further the ion implantation performance of the low-voltage device area and the high-voltage device area can be better still realized under the condition that the thicknesses of the first grid and the second grid are the same, so that the performances of the high-voltage device and the low-voltage device can be improved.
Drawings
Fig. 1 is a flow chart of a method of forming a semiconductor device in an embodiment of the invention;
fig. 2 to 8 are process diagrams of a method of forming a semiconductor device in an embodiment of the present invention;
wherein the reference numbers are as follows:
1-a substrate;
2-a gate oxide layer;
3-a gate layer; 31-a first gate;
32-a second gate; 30-a layer of gate material;
4-a mask layer; 41-a first mask structure;
42-a second mask structure; 40-a layer of masking material;
50-an anti-reflection layer;
6-a photoresist layer;
7-a first barrier structure;
8-a second barrier structure;
9-side wall;
10-a dielectric layer;
11-a plug;
11A-a first doped region; 11B-a second doped region;
12A-a third doped region; 12B a fourth doped region;
a1-low voltage device region; a2-high voltage device region.
Detailed Description
The semiconductor device and the method for forming the same according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
In step S10, as shown in fig. 2, a substrate 1 is provided, the substrate 1 having a high voltage device region a1 and a low voltage device region a 2.
The substrate 1 may include a semiconductor compound, a conductive material, or any combination thereof, and may have a single-layer structure or a multi-layer structure. Thus, the substrate may be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III/V or II/VI compound semiconductors. Layered substrates such as, for example, Si/SiGe, Si/SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator may also be included.
In step S20, referring to fig. 3 with emphasis on fig. 3, a patterned gate layer 3 and a hard mask layer 4 are sequentially formed on the substrate 1, where the gate layer 3 includes a first gate 31 and a second gate 32 with equal thickness, the first gate 31 is located in the low-voltage device region a1, the second gate 32 is located in the high-voltage device region a2, the hard mask layer 4 includes a first mask structure 41 and a second mask structure 42, the first mask structure 41 is located on the first gate 31 and aligned with the first gate 31, and the second mask structure 42 is formed on the second gate 32 and aligned with the second gate 32.
As shown in fig. 2 to 3, the method for forming the gate layer 3 and the hard mask layer 4 includes the following first step and second step.
In step one, as shown in fig. 2, a gate material layer 30, a hard mask material layer 40 and a patterned sacrificial layer 6 are sequentially formed on the substrate 1. In this embodiment, the sacrificial layer 6 may be a positive photoresist or a negative photoresist, and the characteristics of the sacrificial layer 6 are not specifically limited herein, depending on the actual application.
In a second step, referring to fig. 2 and shown in fig. 3, the sacrificial layer 6 is used as a mask, and the hard mask material layer 40 and the gate material layer 30 are sequentially etched to form a gate layer 3 and a hard mask layer 4; the gate layer 3 includes a first gate 31 and a second gate 32 with equal thickness, and the hard mask layer 4 includes a first mask structure 41 aligned with the first gate 31 and a second mask structure 42 aligned with the second gate 32. Wherein the hard mask layer 4 has a thickness of
The thickness of the gate layer 3 is as follows:
and the hard mask layer 4 is made of silicon nitride or silicon oxynitride, wherein the ratio of nitrogen to oxygen in the silicon oxynitride and the ratio of nitrogen to silicon in the silicon nitride can be adjusted according to actual conditions. And is not particularly limited herein.
And, referring to fig. 2, before forming the sacrificial layer 6 on the hard mask material layer 40, the method further comprises: a layer of antireflective material 50 is formed on the layer of hardmask material 40. The anti-reflective material layer 50 is used to improve the photolithography performance.
In the present embodiment, the width of the first gate 31 in the low-voltage device region is smaller than the width of the second gate 32 in the high-voltage device region, for example, the width of the first gate 31 is 40nm to 1000nm, and the width of the second gate 32 is 500nm to 2000 nm.
Further, after forming the gate layer 3, the method further includes: removing the sacrificial layer 6 and the anti-reflection layer (not shown); wherein the sacrificial layer 6 and the anti-reflection layer (not shown) can be removed by an oxygen burning method.
In addition, with continued reference to fig. 2-4, before forming the gate material layer 30, the method further includes: forming a gate oxide layer 2 on said substrate 1, wherein the thickness of said gate oxide layer 2 in said low voltage device region A1Is less than the thickness of the gate oxide layer 2 located in the high voltage device region a 2. Optionally, the thickness of the gate oxide layer 2 in the low-voltage device region a1 is
The thickness of the gate oxide layer 2 in the high-voltage device area A2 is equal to
In an embodiment, the gate oxide layer 2 may be formed by a thermal oxidation method.
Further, in this embodiment, the method for etching the gate material layer 30 is dry etching, and an etching selection ratio of the etching gas of the dry etching to the gate material layer 30 and the gate oxide layer 3 is greater than 10: 1. Since the etching gas has a high etching selection ratio to the gate material layer 30 and the gate oxide layer 3, the gate oxide layer 3 is not damaged when the gate material layer 30 is etched.
In step S30, referring to fig. 4, a first ion implantation process is performed to form a first doping region 11A in the substrate 1 of the low voltage device region a1 based on the first mask structure 41 and the first gate 31. The ions implanted by the first ion implantation process may be P-type ions or N-type ions.
In this embodiment, when the first ion implantation process is performed on the low-voltage device region a1, the stacked first gate 31 and the first mask structure 41 may be directly used as a mask, so as to further improve the ion blocking capability and prevent the substrate under the first gate from being doped.
With continued reference to fig. 4, in this embodiment, before the performing the first ion implantation process, the method further includes: forming a first blocking structure 7 on the high-voltage device region a2, wherein the first blocking structure 7 covers the second mask structure 42 and the second gate 32 and is located on the substrate 1 of the high-voltage device region a 2. As such, the high voltage device region a2 is protected from being affected while the first ion implantation process is performed. Optionally, in this embodiment, the material of the first blocking structure 7 is, for example, a photoresist. Referring to fig. 5, after the first ion implantation process is performed, the first barrier structure 7 is removed, and a method for removing the first barrier structure 7 may be, for example, an oxygen burning process.
In step S40, with continued reference to fig. 5, a second ion implantation process is performed to form a second doped region 11B in the high voltage device region a2 of the substrate 1 based on the second mask structure 42 and the second gate 31. The ions implanted by the second ion implantation process may be P-type ions or N-type ions.
Wherein the ion implantation energy of the second ion implantation process in the high-voltage device region a2 is greater than the ion implantation energy of the first ion implantation process in the low-voltage device region a 1. For the second ion implantation process with higher energy, in this embodiment, the second mask structure 42 is superimposed on the second gate 32, so that the second mask structure 42 is used to make up for the deficiency of the second gate 32 in the ion blocking capability of the second ion implantation, thereby achieving effective blocking of the high-energy ion implantation process. It can be seen that, in the embodiment, the second gate 32 in the high-voltage device region and the first gate 31 in the low-voltage device region are allowed to have the same thickness, and at this time, the ion implantation performance of the low-voltage device region a1 and the ion implantation performance of the high-voltage device region a2 can be still ensured to be better, so that the performance of the high-voltage device and the performance of the low-voltage device can be improved.
Meanwhile, compared with the scheme of selecting a compromise thickness in the prior art, the scheme of adding the hard mask layer 4 on the first gate 31 and the second gate 32 also avoids the problems that gate depletion and device performance degradation are easy to occur due to the high thickness of the first gate 31. Meanwhile, the blocking performance of the hard mask layer 4 is better than that of crystalline silicon, so that the blocking effect can be realized by the thin hard mask layer 4, the performance requirement can be met without the thickness of the first grid 31 being too high, and the problem that the filling performance is reduced due to the fact that the depth-to-width ratio of a spacing area between the first grids 31 is higher due to the fact that the thickness of the first grid 31 is higher when the components are dense can be solved. Meanwhile, the problem that the first gate 31 cracks and topples over when the subsequent etching is performed due to the high thickness of the first gate 31 can be avoided. With continued reference to fig. 5, in this embodiment, before performing the second ion implantation process, the method further includes: forming a second blocking structure 8 in the low-voltage device region a1, wherein the second blocking structure 8 covers the first mask structure 41 and the first gate 31 and is located on the substrate 1 of the low-voltage device region a 1. As such, the low-voltage device region a1 is protected from being affected while the second ion implantation process is performed. Optionally, in this embodiment, the material of the second blocking structure 7 may also be, for example, a photoresist. Referring to fig. 6, after the second ion implantation process is performed, the second barrier structure 7 is removed, and the method for removing the second barrier structure 7 may also be an oxygen burning process, for example.
Further, before performing a first ion implantation process for the low-voltage device region a1 and a second ion implantation process for the high-voltage device region a2, the method further comprises: an oxidation process is performed on the gate layer 3, and a thermal oxidation method may be used to form a silicon oxide layer on the top surface and sidewalls of the gate layer 3, so as to protect the gate layer 3 from being damaged in a subsequent process. Wherein the thickness of the silicon oxide layer is
With continued reference to fig. 7 to 8, after the first doped region 11A and the second doped region 11B are formed, the method further includes the following first to second steps.
In the first step, as shown in fig. 7 and 8, the first mask structure 41 and the second mask structure 42 are removed, and a sidewall 9 is formed at least on sidewalls of the first gate 31 and the second gate 32.
The method for removing the first mask structure 41 and the second mask structure 42 is wet etching. And the method for forming the sidewall spacers 9 on the sidewalls of the first gate 31 and the second gate 32 may include: and forming a side wall material layer on the first gate 31 and the second gate 32, and etching the side wall material layer to form the side wall. The side wall is made of silicon nitride or silicon oxide. Optionally, the sidewall spacer 8 may further include multiple layers, such as an ONO layer.
In the second step, based on the first gate 31 and the sidewall 9 located on the sidewall of the first gate 31, ion implantation is performed to form a third doped region 12A, and based on the second gate 32 and the sidewall 9 located on the sidewall of the second gate 32, ion implantation is performed to form a fourth doped region 12B.
The ion doping types of the third doping region 12A and the fourth doping region 12B may be adjusted correspondingly according to the doping types of the first doping region 11A and the second doping region 11B, and may be optionally the same as the doping types of the first doping region 11A and the second doping region 11B.
In this embodiment, the third doped region 12A is formed at least in the first doped region 11A, and the fourth doped region 12B is located in the second doped region 11B. Specifically, the depth of the first doped region 11A is smaller than the depth of the third doped region 12A, and the depth of the third doped region 12A is smaller than the depth of the second doped region 11B. In addition, in this embodiment, the third doped region 12A and the fourth doped region 12B may be doped in the same step, or may be doped in two steps. The present invention is not limited to the above embodiments, and may be modified in various ways.
In addition, after the above steps are completed, a dielectric layer 10 may be formed on the gate layer 3, a plurality of conductive plugs 11 are formed in the dielectric layer 10, and the conductive plugs 11 are electrically connected to the gate layer 3, the third doped region 12A, and the fourth doped region 12B.
In this embodiment, the high-voltage device and the low-voltage device prepared by the above method may be, for example, a low-voltage NMOS device (LVNMOS), a low-voltage PMOS device (LVPMOS), a high-voltage NMOS device (HVNMOS), or a high-voltage PMOS device (HVPMOS).
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A method of forming a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises a low-voltage device area and a high-voltage device area;
forming a patterned gate layer and a hard mask layer on the substrate, wherein the gate layer comprises a first gate and a second gate which are equal in thickness, the first gate is located in the low-voltage device area, the second gate is located in the high-voltage device area, the hard mask layer comprises a first mask structure and a second mask structure, the first mask structure is located on the first gate and aligned with the first gate, and the second mask structure is located on the second gate and aligned with the second gate;
performing a first ion implantation process on the low-voltage device region based on the first mask structure and the first grid electrode to form first doped regions in the substrate on two sides of the first grid electrode;
and performing a second ion implantation process on the high-voltage device region based on the second mask structure and the second grid electrode so as to form second doped regions in the substrate at two sides of the second grid electrode.
2. The method of forming a semiconductor device according to claim 1, wherein an ion implantation energy of the second ion implantation process is higher than that of the first ion implantation process.
3. The method for forming a semiconductor device according to claim 1, wherein the width of the first gate is 40nm to 1000nm, and the width of the second gate is 500nm to 2000 nm.
4. The method of forming a semiconductor device of claim 1, wherein the method of forming the gate layer and the hard mask layer comprises:
sequentially forming a grid material layer, a hard mask material layer and a patterned sacrificial layer on the substrate;
and sequentially etching the hard mask material layer and the grid material layer by taking the sacrificial layer as a mask to form a hard mask layer and a grid layer, wherein the grid layer comprises a first grid and a second grid which are equal in thickness, and the hard mask layer comprises a first mask structure aligned with the first grid and a second mask structure aligned with the second grid.
5. The method of forming a semiconductor device of claim 1, wherein prior to performing the first ion implantation process, the method further comprises: and forming a first blocking structure in the high-voltage device area, wherein the first blocking structure covers the second hard mask layer and the second gate and is positioned on the substrate of the high-voltage device area.
6. The method of forming a semiconductor device of claim 1, wherein prior to performing the second ion implantation process, the method further comprises: and forming a second blocking structure in the low-voltage device area, wherein the second blocking structure covers the first hard mask layer and the first grid and is positioned on the substrate of the low-voltage device area.
7. The method of forming a semiconductor device of claim 1, wherein prior to forming the gate layer, the method further comprises:
and forming a gate oxide layer on the substrate, wherein the thickness of the gate oxide layer positioned in the low-voltage device area is smaller than that of the gate oxide layer positioned in the high-voltage device area.
8. Such as rightThe method of claim 1, wherein the gate layer has a thickness of:
9. the method of forming a semiconductor device of claim 1, wherein after forming the first doped region and the second doped region, the method further comprises:
removing the first mask structure and the second mask structure, and forming side walls on the side walls of the first grid electrode and the second grid electrode;
and performing ion implantation on the basis of the first grid and the side wall positioned on the side wall of the first grid to form a third doped region, and performing ion implantation on the basis of the second grid and the side wall positioned on the side wall of the second grid to form a fourth doped region.
10. A semiconductor device, characterized in that it is produced by a method of forming a semiconductor device according to any one of claims 1 to 9.
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