CN113488435A - 半导体元件及其形成方法 - Google Patents

半导体元件及其形成方法 Download PDF

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Publication number
CN113488435A
CN113488435A CN202110750252.6A CN202110750252A CN113488435A CN 113488435 A CN113488435 A CN 113488435A CN 202110750252 A CN202110750252 A CN 202110750252A CN 113488435 A CN113488435 A CN 113488435A
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layer
interconnect structure
over
substrate
bonding
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黄文社
郑詠世
杨景峰
陈郁翔
陈啟平
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体元件及其形成方法，方法包括：在一基板的一前侧上方形成一晶体管，其中该晶体管包含一通道区、该通道区上方的一栅极区及该栅极区的多个相对侧上的多个源极/漏极区；在该晶体管上方形成一前侧互连结构，其中该前侧互连结构包括一介电层及多个导电特征；及经由一接合层将该前侧互连结构接合至一载体基板，其中该接合层是在该前侧互连结构与该载体基板之间，且该接合层相较于该前侧互连结构的该介电层具有一较高导热率。

Description

半导体元件及其形成方法
技术领域
本揭露是关于一种半导体元件及其形成方法。
背景技术
半导体元件用于多种电子应用，诸如例如个人计算机、手机、数字摄影机及其他电子装备中。半导体元件通常通过以下操作来制造：在半导体基板上方依序沉积绝缘或介电层、导电层及半导体材料层，及使用光微影来使各种材料层图案化以在基板上形成电路组件及器件。
半导体行业通过最小特征大小上的连续减小而继续改良各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的整合密度，此情形允许更多组件整合至给定区域中。然而，随着最小特征大小被减小，应解决的额外问题出现。
发明内容
在本揭露的一些实施例中，一种半导体元件的形成方法包括：在一基板的一前侧上方形成一晶体管，其中该晶体管包含一通道区、该通道区上方的一栅极区及该栅极区的相对侧上的源极/漏极区；在该晶体管上方形成一前侧互连结构，其中该前侧互连结构包括一介电层及导电特征；及经由一接合层将该前侧互连结构接合至一载体基板，其中该接合层是在该前侧互连结构与该载体基板之间，且该接合层相较于该前侧互连结构的该介电层具有一较高导热率。
在本揭露的一些实施例中，一种半导体元件的形成方法包括：在一基板的一前侧上方形成一鳍片；在该鳍片上方形成一栅极结构及源极/漏极结构；在该栅极结构上方形成一前侧互连结构；在一载体基板上方形成一导热层；在该导热层上方形成一介电层和接合衬垫，其中该导热层相较于该介电层具有一较高导热率；将该介电层及该些接合衬垫接合至该前侧互连结构；及在该基板的一背侧上方形成一背侧互连结构。
在本揭露的一些实施例中，一种半导体元件包括：一基板、一晶体管、一前侧互连结构、一导热层及一背侧互连结构。晶体管位于基板的前侧上方，晶体管包含通道区、通道区上方的栅极结构及栅极结构的多个相对侧上的多个源极/漏极结构。前侧互连结构位于晶体管上方。导热层位于前侧互连结构上方，其中该导热层相较于前侧互连结构的距基板最远的介电层具有较高导热率。背侧互连结构位于基板的背侧上方。
附图说明
本揭露的态样在与随附附图一起研读时自以下详细描述内容来最佳地理解。应注意，根据行业中的标准惯例，各种特征未按比例绘制。实际上，各种特征的尺寸可为了论述清楚经任意地增大或减小。
图1图示根据一些实施例的三维视图中纳米结构场效晶体管(nanostructurefield-effect transistor，nano-FET)的实例；
图2至图27C为根据一些实施例的纳米FET的制造中中间阶段的横截面图；
图28A及图28B图示根据本揭露的一些实施例的形成纳米FET的方法；
图29A及图29B为根据一些实施例的纳米FET的制造中中间阶段的横截面图；
图30A及图30B为根据一些实施例的纳米FET的制造中中间阶段的横截面图；
图31A及图31B为根据一些实施例的纳米FET的制造中中间阶段的横截面图。
【符号说明】
50:基板
50A:块体硅层
50B:氧化物层
50C:半导体层
51:第一半导体层
52:第一纳米结构
53:第二半导体层
54:第二纳米结构
55:纳米结构
62:介电层
63:介电层
64:多层堆叠
66:鳍片
68:浅沟槽隔离区
69:介电鳍片/虚设鳍片
71:虚设栅极介电质
76:虚设栅极
78:图案化遮罩
81:间隔物
86:第一凹部
87:第二凹部
90:内部间隔物
91:磊晶插座
92:磊晶源极/漏极结构
94:触点蚀刻终止层(CESL)
96:第一层间介电质(ILD)
98:第三凹部
100:栅极介电层
102:栅极电极
104:触点开口
105:源极/漏极触点
106:第二层间介电质(ILD)
107:蚀刻终止层(ESL)
112:源极/漏极通孔
114:栅极触点
115:元件层
120:互连结构
122:导电特征
124:堆叠介电层
125:高电阻(HiR)电阻器
126:介电层
127:导电衬垫
134:导电接线
136:互连结构
142:虚设特征
145:导电通孔
150:载体基板
154:接合层/导热层
154A:第一层
154B:第二层
158:堆叠介电层
160:导电特征
164:钝化层
166:UBM
168:外部连接器
224:接合衬垫
228:介电层
252:复合接合层
252A:第一接合层
252B:第二接合层
254:导热层
M1:形成纳米FET的方法
S101:步骤
S102:步骤
S103:步骤
S104:步骤
S105:步骤
S106:步骤
S107:步骤
S108:步骤
S109:步骤
S110:步骤
S111:步骤
S112:步骤
S113:步骤
S114:步骤
S115:步骤
S116:步骤
S117:步骤
S118:步骤
S119:步骤
S120:步骤
S121:步骤
S122:步骤
S123:步骤
S124:步骤
S125:步骤
S126:步骤
具体实施方式
以下揭示内容提供用于实施所提供标的物的不同特征的许多不同实施例或实例。下文描述组件及配置的特定实例以简化本揭露。当然，这些组件及配置仅为实例且并非意欲为限制性的。举例而言，在以下描述中第一特征于第二特征上方或上的形成可包括第一及第二特征直接接触地形成的实施例，且亦可包括额外特征可形成于第一特征与第二特征之间使得第一特征及第二特征可不直接接触的实施例。此外，本揭露在各种实例中可重复参考数字及/或字母。此重复是出于简单及清楚的目的，且本身并不指明所论述的各种实施例及/或组态之间的关系。
另外，空间相对术语，诸如“……下面”、“下方”、“下部”、“……上方”、“上部”及类似者本文中可出于易于描述而使用以描述如诸图中图示的一个元素或特征与另一(些)元素或特征的关系。空间相对术语意欲涵盖元件的使用或操作中的不同于诸图中描绘的定向外的定向。设备可以其他方式定向(旋转90度或处于其他定向)，且本文中使用的空间相对描述词可同样经因此解释。
随着技术节点在半导体元件的进阶节点中收缩，元件在操作期间的温度亦可归因于用于热耗散的减小的晶片区域及增大的晶体管密度而升高。各种实施例提供自产生热的元件(例如，晶体管、电阻器或类似者)至晶片外部的导热路径，借此允许改良的热耗散且补偿操作温度升高。在一些实施例中，导热路径包括在半导体晶片的背侧及/或前侧上形成于互连结构中的虚设特征。
实施例在特定情形在下文描述包含纳米FET的晶粒。然而，替代纳米FET或结合纳米FET，各种实施例可应用至包含其他类型的晶体管(例如，鳍片式场效晶体管(fin fieldeffect transistor，FinFET)、平面晶体管，薄膜晶体管(thin film transistor，TFT)或类似者)的晶粒。
图1图示根据一些实施例的三维视图中的纳米FET(例如，纳米导线FET、纳米片材FET或类似者)的实例。纳米FET包括基板50(例如，半导体基板)上的鳍片66上方的纳米结构55(例如，纳米片材、纳米导线或类似者)，其中纳米结构55充当纳米FET的通道区。纳米结构55可包括p型纳米结构、n型纳米结构或其组合。隔离区68安置于相邻鳍片66之间，这些相邻鳍片可在相邻隔离区68上方且自相邻隔离区之间突出。尽管隔离区68描述/图示为与基板50分离，但如本文中所使用，术语“基板”可单独指基板或指半导体基板与隔离区的组合。另外，尽管鳍片66的底部部分图示为与基板50的单独连续材料，但鳍片66的底部部分及/或基板50可包括单一材料或多种材料。在此情形下，鳍片66指在相邻隔离区68之间延伸的部分。
栅极介电层100是在鳍片66的顶表面上方且沿着纳米结构55的顶表面、侧壁及底表面。栅极电极102是在栅极介电层100上方。磊晶源极/漏极结构92在栅极介电层100及栅极电极102的相对侧上安置于鳍片66上。栅极介电层100及栅极电极102促成晶体管的栅极区，磊晶源极/漏极结构92促成晶体管的源极/漏极区，且纳米结构55促成晶体管的通道区。
图1进一步图示用于后续诸图中的参考横截面。横截面A-A是沿着栅极电极102的纵向轴线且是在例如垂直于在纳米FET的磊晶源极/漏极结构92之间的电流流动方向的方向上。横截面B-B平行于横截面A-A且延伸穿过纳米FET的磊晶源极/漏极区。横截面C-C垂直于横截面A-A且平行于纳米FET的鳍片66的纵向轴线，且是在例如在纳米FET的磊晶源极/漏极结构之间的电流的方向上。为了清楚，后续诸图提及这些参考横截面。
本文中所论述的一些实施例在使用后栅极制程(gate-last process)形成的纳米FET的情形下予以论述。在其他实施例中，可使用先栅极制程(gate-first process)。又，一些实施例预期到用于平面元件，诸如平面FET或鳍片场效晶体管(fin field-effecttransistor，FinFET)中的态样。
图2至图27C为根据一些实施例的纳米FET的制造中中间阶段的横截面图。图2至图6及图7A至图27A图示在图1中图示的参考横截面A-A。图7B至图27B图示在图1中图示的参考横截面B-B。图7C至图27C图示在图1中图示的参考横截面C-C。
参看图2，绘示基板50。在一些实施例中，基板50为绝缘体上半导体(semiconductor-on-insulator，SOI)基板。SOI基板可包括通过诸如分离植入氧气(separation by implanted oxygen，SIMOX)的制程及/或其他合适制程来形成的嵌埋式氧化物(buried oxide，BOX)层。在图2的实例中，基板50为SOI基板，包括块体硅层50A、块体硅层50A上方的氧化物层50B及氧化物层50B上方的半导体层50C。氧化物层50B可为嵌埋式氧化物(buried oxide，BOX)层。在一些实施例中，BOX层为二氧化硅(SiO2)。半导体层50C可包括硅。半导体层50C可合适地掺杂有n型及/或p型掺杂剂。
进一步在图2中，多层堆叠64形成于基板50上方。多层堆叠64包括第一半导体层51及第二半导体层53的交替层。出于图示的目的且如下文更详细地论述，第一半导体层51将被移除，且第二半导体层53将经图案化以形成纳米FET的通道区。
出于图示性目的，多层堆叠64图示为包括第一半导体层51及第二半导体层53中每一者的三个层。在一些实施例中，多层堆叠64可包括合适数目个第一半导体层51及第二半导体层53。
第一半导体层51及第二半导体层53可包括不同材料及/或组件，使得第一半导体层51及第二半导体层53具有不同蚀刻速率。在一些实施例中，第一半导体层51由SiGe制成。第一半导体层51的锗百分数(原子百分数浓度)是在约10％至约20％的范围内，而亦可使用较高或较低锗百分数。然而，应了解，贯穿描述内容叙述的值为实例，且可改变至不同值。举例而言，第一半导体层51可为Si0.8Ge0.2或Si0.9Ge0.1，其中Si与Ge之间的比例可在实施例间发生变化，且本揭露不限于此。第二半导体层53可为不含锗的纯硅层。第二半导体层53亦可大体上为纯硅层，例如，其中锗百分数低于约1％。在一些实施例中，第一半导体层51相较于第二半导体层53具有较高锗原子百分数浓度。第一半导体层51及第二半导体层53可通过化学气相沉积(chemical vapor deposition，CVD)、分子射束磊晶(molecular beamepitaxy，MBE)或其他合适制程形成。在一些实施例中，第一半导体层51及第二半导体层53通过磊晶生长制程形成，且因此第一半导体层51及第二半导体层53在此内容中亦可被称作磊晶层。
现参看图3，根据一些实施例，鳍片66形成于基板50的半导体层50C中，且纳米结构55由多层堆叠64(参见图2)形成。在一些实施例中，纳米结构55及鳍片66可通过在多层堆叠64及基板50的半导体层50C中蚀刻沟槽来形成。蚀刻可为任何可接受蚀刻制程，诸如反应性离子蚀刻(reactive ion etch，RIE)、中性离子射束蚀刻(neutral beam etch，NBE)、类似者或其组合。蚀刻可为各向异性的。通过蚀刻多层堆叠64形成纳米结构55可进一步自第一半导体51界定第一纳米结构52，且自第二半导体层53界定第二纳米结构54。第一纳米结构52及第二纳米结构54可被统称为纳米结构55。
鳍片66及纳米结构55可通过任何合适方法来图案化。举例而言，鳍片66及纳米结构55可使用一或多种光学微影制程，包括双重图案化或多重图案化制程来图案化。大体而言，双重图案化或多重图案化制程组合光学微影及自对准制程，从而允许图案被产生，这些图案相较于使用单一直接光学微影制程以其他方式可获得的图案具有例如较小间距。举例而言，在一个实施例中，牺牲层形成于基板上方，且使用光学微影制程来图案化。间隔物使用自对准制程沿着经图案化的牺牲层来形成。牺牲层接着经移除，且剩余间隔物可接着用于使鳍片66图案化。
虽然鳍片66及纳米结构55中的每一者图示为具有一致宽度产出率，但在其他实施例中，鳍片66及/或纳米结构55可具有渐缩侧壁，使得鳍片66及/或纳米结构55中每一者的宽度在朝向基板50的方向上连续地增大。在此类实施例中，纳米结构55中的每一者可具有不同宽度且形状上为梯形。
参看图4。介电层62及介电层63形成于鳍片66上方。在一些实施例中，介电层62与鳍片66的轮廓保形地沉积。其后，介电层63可沉积于介电层62上方，且填充介电层62中的空间。在一些实施例中，介电层62及介电层63可通过高密度电浆CVD(high-density plasmaCVD，HDP-CVD)、可流动CVD(flowable CVD，FCVD)、类似者或器组合来形成。通过任何可接受制程形成的其他绝缘材料可予以使用。在一些实施例中，介电层62可包括氧化物，诸如氧化硅。在一些实施例中，介电层63可包括氮化物，诸如氮化硅。在一些实施例中，介电层62及介电层63由不同材料制成。
参看图5。介电层62及介电层63经平坦化，以便使介电层62及介电层63的顶表面平齐。在一些实施例中，介电层62及介电层63可使用CMP制程来平坦化。介电层63的剩余部分被称作介电鳍片69。在一些实施例中，介电鳍片69亦可被称作虚设鳍片。
参看图6。介电层62经回蚀以相邻于鳍片66形成浅沟槽隔离区(shallow trenchisolation，STI)68。在一些实施例中，回蚀制程经选择以在大体上不蚀刻介电鳍片69的情况下选择性蚀刻介电层62，此情形允许介电鳍片69在回蚀制程完成后自STI区68突出。因此，STI区68可环绕介电鳍片69的下部部分，同时使介电鳍片69的上部部分暴露。另外，STI区68的顶表面如所图示可具有平坦表面、凸起表面、凹入表面(诸如，碟形)，或其组合。STI区68的顶表面可通过适当蚀刻形成为平坦的、凸起及/或凹入的。STI区68可使用可接受蚀刻制程，诸如对于STI区68的材料为选择性(例如，相较于鳍片66、纳米结构55及介电鳍片69的材料以更快速率蚀刻STI区68的材料)的制程凹入。举例而言，使用例如稀释氢氟(dilutehydrofluoric，dHF)酸的氧化物移除可予以使用。
参看图7A至图7C。虚设栅极76及虚设栅极介电质71形成于基板50上方，且使鳍片66及介电鳍片69交叉。在一些实施例中，图案化遮罩78可形成于虚设栅极76上方。虚设栅极介电质71可例如为氧化硅、氮化硅、其组合或类似者，且可根据可接受技术来沉积或热生长。虚设栅极76可为导电或非导电材料，且可选自包括以下各者的群组：非晶硅、多晶硅(polycrystalline-silicon、polysilicon)、多晶硅锗(poly-crystalline silicon-germanium、poly-SiGe)、金属氮化物、金属硅化物、金属氧化物及金属。虚设栅极76及虚设栅极介电质71可通过例如以下操作来形成：例如在基板上方沉积虚设介电层及虚设栅极层，在虚设栅极层上方形成图案化遮罩78，及接着通过使用图案化遮罩78作为蚀刻遮罩而对虚设介电层及虚设栅极层执行图案化制程。在一些实施例中，虚设栅极76可通过物理气相沉积(physical vapor deposition，PVD)、CVD、溅镀沉积或用于沉积所选择材料的其他技术来沉积。在一些实施例中，虚设栅极介电质71可通过热氧化形成，使得虚设栅极介电质71可仅形成于纳米结构55的暴露表面上。即，STI区68及介电鳍片69的表面无虚设栅极介电质71的覆盖。图案化遮罩78可包括例如氮化硅、氮氧化硅或类似者。
参看图8A至图8C。间隔物81形成于虚设栅极76的相对侧壁、鳍片66的相对侧壁及介电鳍片69的相对侧壁上。在一些实施例中，间隔物81可通过例如在基板上沉积间隔物层毯覆物且随后执行各向异性蚀刻制程以移除间隔物层的水平部分来形成，使得间隔物层的垂直部分保持于虚设栅极76、鳍片66及介电鳍片69的侧壁上。间隔物81可使用诸如热氧化的技术由氧化硅、氮化硅、氮氧化硅、其组合来形成，或通过CVD、ALD或类似者来沉积。
参看图9A至图9C。根据一些实施例，第一凹部86形成于鳍片66、纳米结构55及基板50的半导体层50C中。第一凹部86可延伸穿过第一纳米结构52及第二纳米结构54且延伸至基板50的半导体层50C中。如图9B中所图示，STI区68的顶表面可与第一凹部86的底表面平齐。在各种实施例中，鳍片66可经蚀刻，使得第一凹部86的底表面是在STI区68的顶表面下方。第一凹部86可通过使用各向异性蚀刻制程，诸如RIE、NBE或类似者蚀刻鳍片66、纳米结构55及基板50的半导体层50C来形成。间隔物81及图案化遮罩78在用以形成第一凹部86的蚀刻制程期间遮蔽鳍片66、纳米结构55及基板50的数个部分。单一蚀刻制程或多个蚀刻制程可用以蚀刻纳米结构55及/或鳍片66的每一层。定时蚀刻制程可用以在第一凹部86达到所要深度之后停止第一凹部86的蚀刻。
参看图10A至图10C。第一纳米结构52的通过第一凹部86暴露的部分经蚀刻以形成侧壁凹部，且接着内部间隔物90形成于侧壁凹部中。在一些实施例中，第一纳米结构52的侧壁可使用各向同性蚀刻制程，诸如湿式蚀刻或类似者来蚀刻。在第一纳米结构52包括例如SiGe且第二纳米结构54包括例如Si或SiC的一些实施例中，运用氢氧化四甲铵(tetramethylammonium hydroxide，TMAH)、氢氧化铵(ammonium hydroxide，NH4OH)或类似者的干式蚀刻制程可用以蚀刻第一纳米结构52的侧壁。
内部间隔物90可通过保形沉积制程，诸如CVD、ALD或类似者来沉积。内部间隔物层可包括诸如氮化硅或氮氧化硅的材料，尽管可利用具有小于约3.5的k值的低介电常数(低k)材料的任何合适材料。内部间隔物90可通过例如以下操作来形成：在基板50上方沉积内部间隔物毯覆物并填充第一纳米结构52的侧壁凹部，且接着执行各向异性蚀刻来移除内部间隔物层的非所要部分。尽管内部间隔物90的外部侧壁图示为与第二纳米结构54的侧壁平齐，但内部间隔物90的外部侧壁可延伸超出第二纳米结构54的侧壁或自这些侧壁凹入。
参看图11A至图11C。第二凹部87形成于基板50的半导体层50C中。在一些实施例中，第二凹部87可足够深以暴露基板50的氧化物层50B。在一些实施例中，第二凹部87可使用例如各向异性蚀刻制程形成于基板50的半导体层50C中。在一些实施例中，各向异性蚀刻可通过运用电浆源及反应气体的干式化学蚀刻来执行。借助于实例且并非限制，电浆源可为电感耦合电浆(inductively coupled plasma，ICR)源、变压器耦合电浆(transformercoupled plasma，TCP)源、电子回旋谐振(electron cyclotron resonance，ECR)源或类似者，且反应气体可为氟类气体(诸如SF6、CH2F2、CH3F、CHF3或类似者)、氯类气体(例如，Cl2)、溴化氢气体(HBr)、氧气(O2)、类似者或其组合。
参看图12A至图12C。磊晶插座91形成于第二凹部87中。在一些实施例中，磊晶插座91与基板50的氧化物层50B实体接触。在一些实施例中，磊晶生长制程经执行以在第二凹部87中生长磊晶材料，直至磊晶材料堆积于磊晶插座91上，从而填充第二凹部87。磊晶插座91可包括不同于基板50的半导体层50C的组合物或材料。举例而言，基板50的半导体层50C为Si，且磊晶插座91为SiGe。在一些实施例中，磊晶插座91掺杂有合适掺杂剂(例如，重度n型掺杂剂或p型掺杂剂)以充当背侧导电插座，从而将随后形成的磊晶源极/漏极结构电连接至背侧互连结构。
在磊晶插座91由SiGe制成的一些实施例中，根据本揭露的一些实施例，为了防止SiGe无意地形成于第二纳米结构54的端表面上，磊晶插座91可以底部向上样式生长。借助于实例且非限制，磊晶插座91可通过磊晶沉积/部分蚀刻制程生长，此情形重复磊晶沉积/部分蚀刻制程至少一次。此类经重复的沉积/部分蚀刻制程亦被称作循环沉积蚀刻(cyclicdeposition-etch，CDE)制程。在一些其他实施例中，磊晶插座91可通过例如以下操作形成：沉积磊晶材料从而填充第一凹部86及第二凹部87，且接着回蚀磊晶材料以形成磊晶插座91。
参看图13A至图13C，在第一凹部86中形成磊晶源极/漏极结构92。在一些实施例中，磊晶源极/漏极结构92可施加应力于第二纳米结构54上，借此改良效能。如图13C中所图示，磊晶源极/漏极结构92形成于第一凹部86中，使得每一虚设栅极76安置于各别相邻对的磊晶源极/漏极结构92之间。在一些实施例中，间隔物81用以分离磊晶源极/漏极结构92与虚设栅极76，且内部间隔物90用以使磊晶源极/漏极结构92与第一纳米结构52分离开适当侧向距离，使得磊晶源极/漏极结构92并不与所得纳米FET的随后形成的栅极短路连接。在一些实施例中，磊晶源极/漏极结构92包括用于形成p型FET的p型掺杂剂，诸如硼。在其他实施例中，磊晶源极/漏极结构92包括用于形成n型FET的n型掺杂剂，诸如磷。
参看图14A至图14C。第一层间介电质(interlayer dielectric，ILD)96沉积于分别图示于图13A至图13C中的结构上方。在一些实施例中，CMP制程可对第一ILD 96执行，直至虚设栅极76的顶表面予以暴露。第一ILD 96可由介电材料形成，且可通过任何合适方法，诸如CVD、电浆增强型CVD(plasma-enhanced CVD，PECVD)或FCVD沉积。介电材料可包括磷硅玻璃(phospho-silicate glass，PSG)、硼硅玻璃(boro-silicate glass，BSG)、硼磷硅玻璃(boron-doped phospho-silicate glass，BPSG)、无掺杂硅玻璃(undoped silicateglass，USG)或类似者。可使用通过任何可接受制程形成的其他绝缘材料。在一些实施例中，触点蚀刻终止层(contact etch stop layer，CESL)94安置于第一ILD 96及磊晶源极/漏极结构92与间隔物81之间。CESL 94可沿着介电鳍片69的侧壁及顶表面延伸。CESL 94可包括具有不同于上覆第一ILD 96的材料的蚀刻速率的介电材料，诸如氮化硅、氧化硅、氮氧化硅或类似者。
参看图15A至图15C。虚设栅极76及虚设栅极介电质71在一或多个蚀刻步骤中被移除，使得第三凹部98被形成。在一些实施例中，虚设栅极76及虚设栅极介电质71可通过各向异性干式蚀刻制程来移除。举例而言，蚀刻制程可包括使用反应气体的干式蚀刻制程，反应气体以快于第一ILD 96或间隔物81的速率选择性地蚀刻虚设栅极76。每一第三凹部98暴露及/或上覆纳米结构55的部分，这些部分充当后续完成纳米FET的通道区。纳米结构55的充当通道区的数个部分安置于相邻数对磊晶源极/漏极结构92之间。在移除期间，当虚设栅极76经蚀刻时，虚设栅极介电质71可用作蚀刻终止层。虚设栅极介电质可接着在移除虚设栅极76之后被移除。
接着，第一纳米结构52经移除以使第三凹部98延伸。第一纳米结构52可通过执行诸如湿式蚀刻的各向同性蚀刻制程或类似者使用对于第一纳米结构52的材料为选择性的蚀刻剂来移除，而第二纳米结构54、基板50、STI区68相较于第一纳米结构52保持相对未蚀刻。在第一纳米结构52包括例如SiGe且第二纳米结构54包括例如Si或SiC的实施例中，氢氧化四甲铵(tetramethylammonium hydroxide，TMAH)、氢氧化铵(ammonium hydroxide，NH4OH)或类似者可用以移除第一纳米结构52。
参看图16A至图16C。栅极介电层100及栅极电极102经形成以供替换栅极。栅极介电层100在第三凹部98中经保形地沉积。栅极介电层100可是在基板50的顶表面及侧壁上且在第二纳米结构54的顶表面、侧壁及底表面上形成。
根据一些实施例，栅极介电层100可包括一或多个介电层，诸如氧化物、金属氧化物、类似者或其组合。举例而言，在一些实施例中，栅极介电质可包括氧化硅层及氧化硅层上方的金属氧化物层。在一些实施例中，栅极介电层100包括高k介电材料，且在这些实施例中，栅极介电层100可具有大于约7.0的k值，且可包括铪、铝、锆、镧、锰、钡、钛、铅及其组合的金属氧化物，或硅酸盐。栅极介电层100的形成方法可包括分子束沉积(molecular-beamdeposition，MBD)、ALD、PECVD，及类似者。
栅极电极102分别沉积于栅极介电层100上方，且填充第三凹部98的剩余部分。栅极电极102可包括含金属材料，诸如氮化钛、氧化钛、氮化钽、碳化钽、钴、钌、铝、钨、其组合物，或其多层。举例而言，尽管单一层栅极电极102图示于图16A至图16C中，但栅极电极102可包括任何数目个衬里层、任何数目个功函数调谐层及填充材料。
在填充第二凹部98之后，平坦化制程，诸如CMP可经执行以移除栅极介电层100及栅极电极102的材料的过量部分，这些过量部分是在第一ILD 96的顶表面上方。栅极电极102及栅极介电层100的材料的剩余部分因此形成所得纳米FET的替换栅极结构。栅极电极102及栅极介电层100可统称为“栅极结构”。
参看图17A至图17C。触点开口104形成于第一ILD 96中以暴露磊晶源极/漏极结构92。在一些实施例中，开口104可通过例如以下操作形成：在第一ILD 96上方形成遮罩层，诸如光阻剂层；图案化遮罩层以在遮罩层中形成开口；经由遮罩层中的开口蚀刻第一ILD 96；及接着移除遮罩层。如第17B的横截面图中所绘示，在一些实施例中，磊晶源极/漏极结构92(在右侧)在形成触点开口104之后通过第一ILD 96覆盖。在此类实施例中，介电鳍片69的一个侧壁可通过开口104暴露，而介电鳍片69的另一侧壁及顶表面可通过第一ILD 96覆盖。
参看图18A至图18C。源极/漏极触点105分别形成于触点开口104中。在一些实施例中，源极/漏极触点105可通过例如以下操作来形成：在触点开口104中沉积一或多个导电材料，及执行CMP制程以移除过量导电材料，直至第一ILD 96的顶表面被暴露。触点105可包括一或多个层，诸如阻障层、扩散层及填充材料。在一些实施例中，触点可各自包括由钛、氮化钛、钽、氮化钽或类似者制成的阻障层，及由铜、铜合金、银、金、钨、钴、铝、镍或类似者制成的导电材料。
在一些实施例中，在形成源极/漏极触点105之前，硅化物层(图中未示)可形成于通过开口104暴露的磊晶源极/漏极结构92上方。在一些实施例中，硅化物层通过以下操作来形成：首先沉积能够与下伏磊晶源极/漏极结构92的半导体材料(例如，硅、硅锗、锗)反应的金属(未图示)，诸如镍、钴、钛、钽、铂、钨、其他贵金属、其他耐火金属、稀土金属或其合金于磊晶源极/漏极结构92的暴露部分上方，以形成硅化物或锗化物区；接着执行热退火制程以形成硅化物层。所沉积金属的未经反应部分接着例如通过蚀刻制程来移除。
参看图19A至图19C。蚀刻终止层(etch stop layer，ESL)107形成于第一ILD 96上方，第二ILD 106形成于ESL 107上方，且源极/漏极通孔112及栅极触点114经形成，从而延伸通过第二ILD 106及ESL 107分别至源极/漏极触点105及栅极电极102。在一些实施例中，源极/漏极通孔112及栅极触点114可通过例如以下操作来形成：图案化第二ILD 106及ESL107以形成开口，在开口中沉积一或多个导电材料，及执行CMP制程以移除过量导电材料，直至第二ILD 106的顶表面被暴露。源极/漏极通孔112及栅极触点114可包括一或多个层，诸如阻障层、扩散层及填充材料。在一些实施例中，触点各自可包括由钛、氮化钛、钽、氮化钽或类似者制成的阻障层，及由铜、铜合金、银、金、钨、钴、铝、镍或类似者制成的导电材料。
参看图20A至图20C。互连结构120形成于第二ILD 106上方。互连结构120亦可被称作前侧互连结构，此是因为该互连结构形成于基板50的前侧上。
互连结构120可包括形成于一或多个堆叠介电层124中的导电特征122的一或多个层。堆叠介电层124中的每一者可包括介电材料，诸如低k介电材料、超低k(extra low-k，ELK)介电材料或类似者。介电层124可使用适当制程，诸如CVD、ALD、PVD、PECVD或类似者来沉积。
导电特征122可包括导电接线及互连导电接线层的导电通孔。导电通孔可延伸穿过介电层124中的各别介电层以提供导电接线层之间的垂直连接。导电特征122可经由任何可接受制程，诸如镶嵌制程、双重镶嵌制程或类似者来形成。
举例而言，导电特征122可使用镶嵌制程形成，该镶嵌制程中，各别介电层124利用光微影与蚀刻技术的组合来图案化以形成对应于导电特征122的所要图案的沟槽。可选扩散阻障层及/或可选粘着层可经沉积，且沟槽可接着填充有导电材料。阻障层的合适材料包括钛、氮化钛、氧化钛、钽、氮化钽、氧化钛、或其他替代例，且导电材料的合适材料包括铜、银、金、钨、铝、其组合或类似者。在实施例中，导电特征122可通过沉积铜或铜合金的晶种层且通过电镀填充沟槽来形成。化学机械平坦化(chemical mechanical planarization，CMP)制程或类似者可用以自各别介电层124的表面移除过量导电材料且平坦化表面以供随后处理。
在一些实施例中，高电阻(high resistance，HiR)电阻器125可形成于互连结构120中。举例而言，HiR电阻器125由高电阻材料，例如氮化钛(TiN)或氮化钽(TaN)形成。
在图20A至图20C中，导电特征122及介电层124的五个层予以图示。然而，应了解，互连结构120可包括安置于任何数目个介电层124中的任何数目个导电特征。互连结构120可电连接至栅极触点114及源极/漏极通孔112以形成功能电路。在一些实施例中，通过互连结构120形成的功能电路可包括逻辑电路、记忆体电路、影像感测器电路或类似者。
参看图21A至图21C。接合层154形成于互连结构120上方。在一些实施例中，接合层154为导热层，且因此在此内容中可被互称为导热层154。在一些实施例中，接合层154为提供电隔离的绝缘材料。在一些实施例中，接合层154通过合适制程，诸如ALD、CVD或旋涂而形成于互连结构120上。
接合层154可包括一材料，该材料具有高于互连结构120的介电层124的导热率的导热率，且可高于稍后接合的载体基板(例如，载体基板150)的导热率。在一些实施例中，接合层154包括具有导热率的材料，该导热率大于约0.39W/m*K，诸如约25W/m*K至290W/m*K。在一些实施例中，接合层154可包括诸如氮化铝(AlN)或氧化铝(Al2O3)的材料。举例而言，AlN的导热率是在自约280W/m*K至约290W/m*K的范围内，诸如285W/m*K。Al2O3的导热率是在自约25W/m*K至约35W/m*K的范围内，诸如30W/m*K。
在一些实施例中，接合层154可包括第一层154A及第二层154B，其中第一层154A是在互连结构120与第二层154B之间。在一些实施例中，第一层154A由AlN制成，且第二层154B由Al2O3制成，且因此第一层154A具有高于第二层154B的导热率。在替代性实施例中，第一层154A由Al2O3制成，且第二层154B由AlN制成，且因此第一层154A具有低于第二层154B的导热率。
在一实施例中，接合层154的厚度是在约
Figure BDA0003145893170000161
至约
Figure BDA0003145893170000162
的范围内。在一些实施例中，接合层154的第一层154A的厚度是在自约
Figure BDA0003145893170000163
至约
Figure BDA0003145893170000164
Figure BDA0003145893170000165
的范围内，且接合层154的第二层154B的厚度是在自约
Figure BDA0003145893170000166
至约
Figure BDA0003145893170000167
的范围内。若接合层154的厚度过低，则接合层154可能不足以改良晶圆堆叠或晶粒堆叠的热管理能力及/或改良热耗散。另一方面，若接合层154的厚度过大，则制造成本增大而无显著优势。
在一些实施例中，接合层154可为单层结构。即，接合层154可包括第一层154A及第二层154B中的仅一者。举例而言，接合层154可为单一AlN层，或可为单一Al2O3层。
在一些其他实施例中，接合层154可包括诸如SiC、SiN、SiCN、氮化硼(BN)、金刚石、金刚石类碳(diamond-like carbon，DLC)、氧化石墨烯、石墨的材料，或其他合适材料。导热层154的材料可为单晶硅或多晶硅。
参看图22A至图22C。载体基板150接合至接合层154。换言之，载体基板150经由接合层154接合至互连结构120。载体基板150可为玻璃载体基板、陶瓷载体基板、半导体基板(例如，硅基板)、晶圆(例如，硅晶圆)或类似者。载体基板150在后续处理步骤期间且在完成元件中提供结构支撑。载体基板150可大体上无任何主动或被动元件。在一些实施例中，载体基板150的厚度是在约
Figure BDA0003145893170000171
至约
Figure BDA0003145893170000172
的范围内。
在各种实施例中，载体基板150可使用合适技术接合至互连结构120。在一些实施例中，接合制程可进一步包括对接合层154进行表面处置。表面处置可包括电浆处置。电浆处置可在真空环境中执行。在电浆处置之后，表面处置可进一步包括可施加至接合层154的清洁制程(例如，运用去离子水的清洗或类似者)。载体基板150接着与互连结构120对准，且两者抵靠彼此按压以起始载体基板150至互连结构120的预接合。预接合可在室温(约21度与约25度之间)下执行。在预接合之后，退火制程可通过例如加热互连结构120及载体基板150至约200℃至400℃的温度来施加。
参看图23A至图23C。在载体基板150接合至互连结构120之后，元件可经反转，使得基板50的背侧面向上。基板50的背侧可指与基板50的前侧相对的侧，元件层(例如，包括晶体管的层)形成于该前侧上。接着，CMP制程对基板50的背侧执行。在一些实施例中，CMP制程经控制以移除基板50的块体硅层50A，直至基板50的氧化物层50B暴露。
参看图24A至图24C。导电通孔145形成于基板50的氧化物层50B中。在一些实施例中，导电通孔145分别与磊晶插座91实体接触。在一些实施例中，导电通孔145可例如通过以下操作形成：图案化基板50的氧化物层50B以形成暴露磊晶插座91的开口，在氧化物层50B上方沉积导电材料且填充氧化物层50B中的开口，且接着执行CMP制程以移除过导电量材料，直至氧化物层50B被暴露。在一些实施例中，导电通孔145可包括铜、银、金、钨、铝、其组合或类似者。在一些实施例中，导电通孔145亦可被称作背侧通孔。
参看图25A至图25C。介电层126沉积于基板50的氧化物层50B上，且导电衬垫127形成于介电层126中。在一些实施例中，介电层126可通过如下操作来形成：在氧化物层50B上方沉积介电材料，及视需要执行CMP制程以削薄介电材料。导电衬垫127可通过例如以下操作来形成：图案化介电层126以形成开口，在开口中沉积导电材料，及接着执行CMP制程以移除过量导电材料，直至介电层126的顶表面被暴露。在一些实施例中，介电层126可包括磷硅玻璃(phospho-silicate glass，PSG)、硼硅玻璃(boro-silicate glass，BSG)、硼磷硅玻璃(boron-doped phospho-silicate glass，BPSG)、无掺杂硅玻璃(undoped silicateglass，USG)或类似者。在一些实施例中，导电衬垫127可包括铜、银、金、钨、铝、其组合或类似者。
参看图26A至图26C。互连结构136形成于介电层126上方。互连结构136亦可被称作背侧互连结构，此是因为该互连结构形成于基板50的前侧上。在一些实施例中，互连结构136可包括形成于一或多个堆叠介电层158中的导电特征160的一或多个层。导电特征160及介电层158可类似于互连结构120的导电特征122及介电层124，且因此为了简单其相关细节将不予重复。
参看图27A至图27C。钝化层164、UBM 166及外部连接器168形成于互连结构136上方。钝化层164可包含聚合物，诸如PBO、聚酰亚胺、BCB或类似者。替代地，钝化层164可包括无机介电材料，诸如氧化硅、氮化硅、碳化硅、氮氧化硅或类似者。钝化层164可通过例如CVD、PVD、ALD或类似者来沉积。
UBM 166穿过钝化层164形成至互连结构136中的导电特征140，且外部连接器168形成于UBM 166上。UBM 166可包含铜、镍、或类似者的一或多个层，前述各层通过镀敷制程或类似者来形成。外部连接器168(例如，焊球)形成于UBM 166上。外部连接器168的形成可包括将焊球置放于UBM 166的经暴露部分上且对焊球进行回焊。在替代性实施例中，外部连接器168的形成包括执行镀覆步骤以在最顶导电特征140上方形成焊料区，且接着对焊料区进行回焊。UBM 166及外部连接器168可用以提供输入/输出连接至其他电组件，诸如其他元件晶粒、重新分布结构、印刷电路板(printed circuit board，PCB)、母版或其类似者中。UBM 166及外部连接器168亦可被称作背侧输入/输出衬垫，这些衬垫可提供信号、供电电压及/或接地连接至上文所描述的纳米FET。
UBM 166及外部连接器168可通过虚设特征142热连接至元件层115及/或导电接线134(例如，电力轨条)。因此，虚设特征142可有助于经由背侧互连结构136将热传导远离主动元件及/或导电接线134至半导体晶粒的外部。在一些实施例中，载体基板150不存在背侧互连结构136。
图28A及图28B图示根据本揭露的一些实施例的形成纳米FET的方法M1。尽管方法M1经图示及/或描述为一系列动作或事件，但应了解，方法不限于所图示的次序或动作。因此，在一些实施例中，动作可以不同于所图示的次序执行，及/或可同时执行。另外，在一些实施例中，所图示动作或事件可经再分为多个动作或事件，这些动作或事件在独立时间或与其他动作或子动作同时执行。在一些实施例中，一些所图示动作或事件可被省略，且其他未图示动作或事件可被包括。
在步骤S101处，第一及第二半导体层交替地形成于基板上方。图2图示对应于步骤S101中的动作的一些实施例的横截面图。
在步骤S102处，鳍片形成于基板上方。图3图示对应于步骤S102中的动作的一些实施例的横截面图。
在步骤S103处，第一介电层及第二介电层形成于鳍片上方。图4图示对应于步骤S103中的动作的一些实施例的横截面图。
在步骤S104处，第一介电层及第二介电层经平坦化。图5图示对应于步骤S104中的动作的一些实施例的横截面图。
在步骤S105处，第一介电层经回蚀以形成介电鳍片。图6图示对应于步骤S105中的动作的一些实施例的横截面图。
在步骤S106处，虚设栅极及虚设栅极介电质形成于基板上方，且使鳍片及介电鳍片交叉。图7A至图7C图示对应于步骤S106中的动作的一些实施例的横截面图。
在步骤S107处，间隔物形成于虚设栅极、鳍片及介电鳍片的相对侧壁上。图8A至图8C图示对应于步骤S107中的动作的一些实施例的横截面图。
在步骤S108处，根据一些实施例，第一凹部形成于鳍片中。图9A至图9C图示对应于步骤S108中的动作的一些实施例的横截面图。
在步骤S109处，第一半导体层的数个部分经蚀刻以形成侧壁凹部，且内部间隔物形成于侧壁凹部中。图10A至图10C图示对应于步骤S109中的动作的一些实施例的横截面图。
在步骤S110处，第二凹部形成于基板中。图11A至图11C图示对应于步骤S110中的动作的一些实施例的横截面图。
在步骤S111处，磊晶插座形成于第二凹部中。图12A至图12C图示对应于步骤S111中的动作的一些实施例的横截面图。
在步骤S112处，磊晶源极/漏极结构形成于第一凹部中。图13A至图13C图示对应于步骤S112中的动作的一些实施例的横截面图。
在步骤S113处，第一ILD沉积于磊晶源极/漏极结构上方。图14A至图14C图示对应于步骤S113中的动作的一些实施例的横截面图。
在步骤S114处，虚设栅极介电质及第一半导体层经移除以形成第三凹部。图15A至图15C图示对应于步骤S114中的动作的一些实施例的横截面图。
在步骤S115处，栅极介电层及栅极电极经形成用于替换栅极。图16A至图16C图示对应于步骤S115中的动作的一些实施例的横截面图。
在步骤S116处，开口形成于第一ILD中以暴露磊晶源极/漏极结构。图17A至图17C图示对应于步骤S116中的动作的一些实施例的横截面图。
在步骤S117处，第一触点形成于开口中。图18A至图18C图示对应于步骤S117中的动作的一些实施例的横截面图。
在步骤S118处，ESL及第二ILD形成于第一ILD上方，且第二触点经形成从而延伸通过第二ILD及ESL。图19A至图19C图示对应于步骤S118中的动作的一些实施例的横截面图。
在步骤S119处，第一互连结构形成于第二ILD上方。图20A至图20C图示对应于步骤S119中的动作的一些实施例的横截面图。
在步骤S120处，接合层形成于第一互连结构上方。图21A至图21C图示对应于步骤S120中的动作的一些实施例的横截面图。
在步骤S121处，载体基板接合至接合层。图22A至图22C图示对应于步骤S121中的动作的一些实施例的横截面图。
在步骤S122处，CMP制程对基板的背侧执行。图23A至图23C图示对应于步骤S122中的动作的一些实施例的横截面图。
在步骤S123处，导电通孔形成于基板的氧化物层中。图24A至图24C图示对应于步骤S123中的动作的一些实施例的横截面图。
在步骤S124处，介电层沉积于基板的氧化物层上，且导电衬垫形成于介电层中。图25A至图25C图示对应于步骤S124中的动作的一些实施例的横截面图。
在步骤S125处，第二互连结构形成于介电层上方。图26A至图26C图示对应于步骤S125中的动作的一些实施例的横截面图。
在步骤S126处，钝化层、UBM及外部连接器形成于互连结构上方。图27A至图27C图示对应于步骤S126中的动作的一些实施例的横截面图。
图29A及图29B为根据一些实施例的纳米FET的制造中中间阶段的横截面图。图29A至图29B的一些器件类似于关于图2至图27C描述的那些器件，此类器件标记为相同的，且细节为了简单将不重复。图29A及图29B图示接合互连结构120与载体基板150的实施例。
不同于图2至图27C的实施例，在图29A中，接合层154在接合互连结构120与载体基板150之前形成于载体基板150上方。即，互连结构120的表面(例如，最外介电层124及最外导电特征122)在接合制程之前无接合层154的材料的覆盖。
类似地，接合层154可包括第一层154A及第二层154B，其中第一层154A是在载体基板150与第二层154B之间。在一些实施例中，第一层154A由AlN制成，且第二层154B由Al2O3制成，且因此第一层154A具有高于第二层154B的导热率。在替代性实施例中，第一层154A由Al2O3制成，且第二层154B由AlN制成，且因此第一层154A具有低于第二层154B的导热率。
互连结构120接合至接合层154，且所得结构绘示于图29B中。换言之，互连结构120经由接合层154接合至载体基板150。应注意，图29B的结构可经历在图23A至图27C中描述的制程，且相关细节为了简单将不予以重复。
图30A及图30B为根据一些实施例的纳米FET的制造中中间阶段的横截面图。图30A至图30B的一些器件类似于关于图2至图27C描述的那些器件，此类器件标记为相同的，且细节为了简单将不重复。图30A及图30B图示接合互连结构120与载体基板150的实施例。
在图30A中，分别地，第一接合层252A形成于载体基板150上，且第二接合层252B形成于互连结构120上。在一些实施例中，第一接合层252A及第二接合层252B可包括诸如氮化铝(AlN)或氧化铝(Al2O3)的材料。在一些实施例中，第一接合层252A及第二接合层252B可包括同一材料。举例而言，第一接合层252A及第二接合层252B可皆由AlN制成，或皆由Al2O3制成。另一方面，第一接合层252A及第二接合层252B可包括不同材料。举例而言，第一接合层252A可由AlN制成，且第二接合层252B可由Al2O3制成，且因此第一接合层252A具有高于第二接合层252B的导热率。替代地，第一接合层252A可由AlN制成，且第二接合层252B可由Al2O3制成，且因此第一接合层252A具有高于第二接合层252B的导热率。
接着，第一接合层252A接合至第二接合层252B，且所得结构绘示于图30B中。换言之，互连结构120经由第一接合层252A及第二接合层252B接合至载体基板150。在一些实施例中，第一接合层252A及第二接合层252B可被统称为复合接合层252。应注意，图30B的结构可经历在图23A至图27C中描述的制程，且相关细节为了简单将不予以重复。
图31A及图31B为根据一些实施例的纳米FET的制造中中间阶段的横截面图。图31A至图31B的一些器件类似于关于图2至图27C描述的那些器件，此类器件标记为相同的，且细节为了简单将不重复。图31A及图31B图示接合互连结构120与载体基板150的实施例。
在图31A中，导热层254在接合制程之前形成于载体基板150的表面上。在一些实施例中，导热层254可类似于如关于图2至图27C论述的接合层154，且因此相关细节为了简单将不予重复。在一些实施例中，导热层254的厚度是在约
Figure BDA0003145893170000221
至约
Figure BDA0003145893170000222
的范围内。
接着，介电层228形成于导热层254上，且接合衬垫224形成于介电层128中。在一些实施例中，介电层228可包括磷硅玻璃(phospho-silicate glass，PSG)、硼硅玻璃(boro-silicate glass，BSG)、硼磷硅玻璃(boron-doped phospho-silicate glass，BPSG)、无掺杂硅玻璃(undoped silicate glass，USG)或类似者。在一些实施例中，接合衬垫224可包括铜、银、金、钨、铝、其组合或类似者。在一些实施例中，导热层254相较于介电层228具有较高导热率。在一些实施例中，介电层228厚于导热层254。举例而言，介电层228的厚度是在约
Figure BDA0003145893170000223
至约
Figure BDA0003145893170000224
的范围内。
接着，介电层228及接合衬垫224使用混合式接合而接合至互连结构120，且所得结构绘示于图31B中。换言之，互连结构120经由介电层228、接合衬垫224及导热层254接合至载体基板150。在一些实施例中，混合式接合经执行，使得介电层228熔融接合至互连结构120的最外介电层124，且接合衬垫224运用金属至金属接合来直接接合至导电特征122。应注意，图31B的结构可经历在图23A至图27C中描述的制程，且相关细节为了简单将不予以重复。
基于以上论述内容，可看到，本揭露给予优势。然而，应理解，其他实施例可给予额外优势，且并非所有优势有必要揭示于本文中，且无特定优势针对所有实施例被需要。一个优势为，通过使用导热材料作为元件基板与载体基板之间的接合层，此情形将改良热耗散及电迁移。在一个实施例中，模拟结果展示，当应用导热接合层时，互连结构中高电阻(highresistance，HiR)电阻器的温度可自约45.8℃减小至约37.5℃，此情形达成至少约18％的改良。
在本揭露的一些实施例中，一种方法包括：在一基板的一前侧上方形成一晶体管，其中该晶体管包含一通道区、该通道区上方的一栅极区及该栅极区的相对侧上的源极/漏极区；在该晶体管上方形成一前侧互连结构，其中该前侧互连结构包括一介电层及导电特征；及经由一接合层将该前侧互连结构接合至一载体基板，其中该接合层是在该前侧互连结构与该载体基板之间，且该接合层相较于该前侧互连结构的该介电层具有一较高导热率。
在部分实施例中，其中该接合层在将该前侧互连结构接合至该载体基板之前形成于该前侧互连结构上方。
在部分实施例中，其中该接合层在将该前侧互连结构接合至该载体基板之前形成于该载体基板上方。
在部分实施例中，其中在将该前侧互连结构接合至该载体基板之前，该接合层的一第一层形成于该前侧互连结构上方，且该接合层的一第二层形成于该载体基板上方。
在部分实施例中，其中该接合层的该第一层及该接合层的该第二层由不同材料制成。
在部分实施例中，其中该接合层包含一第一层及与该第一层接触的一第二层。
在部分实施例中，其中该第一层由氧化铝制成，且该第二层由氮化铝制成。
在部分实施例中，其进一步包含以下步骤：在将该前侧互连结构接合至该载体基板之后在该基板的一背侧上方形成一背侧互连结构。
在部分实施例中，进一步包含对该基板的该背侧执行一平坦化制程；及在该基板中形成多个背侧通孔。
在本揭露的一些实施例中，一种方法包括：在一基板的一前侧上方形成一鳍片；在该鳍片上方形成一栅极结构及源极/漏极结构；在该晶体管上方形成一前侧互连结构；在一载体基板上方形成一导热层；在该导热层上方形成一介电层和接合衬垫，其中该导热层相较于该介电层具有一较高导热率；将该介电层及该些接合衬垫接合至该前侧互连结构；及在该基板的一背侧上方形成一背侧互连结构。
在部分实施例中，其中该导热层为双层。
在部分实施例中，其中该导热层的一厚度是在自约
Figure BDA0003145893170000241
至约
Figure BDA0003145893170000242
的一范围内。
在部分实施例中，其中该介电层厚于该导热层。
在部分实施例中，其进一步包含以下步骤：在该基板的一背侧上方形成一背侧互连结构。
在部分实施例中，进一步包含在形成该些源极/漏极结构之前，蚀刻该鳍片以形成延伸至该基板中的一凹部，直至达到该基板的一嵌埋式氧化物层；及在该凹部中且与该基板的该嵌埋式氧化物层接触地形成一磊晶插座。
在部分实施例中，进一步包含在将该介电层及该些接合衬垫接合至该前侧互连结构之后，对该基板的该背侧执行一平坦化制程以暴露该基板的该嵌埋式氧化物层；及在该嵌埋式氧化物层中且与该磊晶插座接触地形成一背侧通孔。
在本揭露的一些实施例中，一种半导体元件包括：一基板、一晶体管、一前侧互连结构、一导热层及一背侧互连结构。晶体管位于基板的前侧上方，晶体管包含通道区、通道区上方的栅极结构及栅极结构的多个相对侧上的多个源极/漏极结构。前侧互连结构位于晶体管上方。导热层位于前侧互连结构上方，其中该导热层相较于前侧互连结构的距基板最远的介电层具有较高导热率。背侧互连结构位于基板的背侧上方。
在部分实施例中，其中该导热层包含与该前侧互连结构接触的一第一层及该第一层上方的一第二层，且该第一层的一导热率低于该第二层的一导热率。
在部分实施例中，其中该导热层包含与该前侧互连结构接触的一第一层及该第一层上方的一第二层，且该第一层的一导热率高于该第二层的一导热率。
在部分实施例中，其中该导热层包含氧化铝或氮化铝。
前述内容概述若干实施例的特征，使得熟悉此项技术者可更佳地理解本揭露的态样。熟悉此项技术者应了解，其可易于使用本揭露作为用于设计或修改用于实施本文中引入的实施例的相同目的及/或达成相同优势的其他制程及结构的基础。熟悉此项技术者亦应认识到，此类等效构造并不偏离本揭露的精神及范畴，且此类等效构造可在本文中进行各种改变、取代及替代而不偏离本揭露的精神及范畴。

Claims (10)

1.一种半导体元件的形成方法，其特征在于，包含以下步骤：
在一基板的一前侧上方形成一晶体管，其中该晶体管包含一通道区、该通道区上方的一栅极区及该栅极区的多个相对侧上的多个源极/漏极区；
在该晶体管上方形成一前侧互连结构，其中该前侧互连结构包含一介电层及多个导电特征；及
经由一接合层将该前侧互连结构接合至一载体基板，其中该接合层是在该前侧互连结构与该载体基板之间，且该接合层相较于该前侧互连结构的该介电层具有一较高导热率。
2.根据权利要求1所述的方法，其特征在于，该接合层在将该前侧互连结构接合至该载体基板之前形成于该前侧互连结构上方。
3.根据权利要求1所述的方法，其特征在于，该接合层在将该前侧互连结构接合至该载体基板之前形成于该载体基板上方。
4.根据权利要求1所述的方法，其特征在于，在将该前侧互连结构接合至该载体基板之前，该接合层的一第一层形成于该前侧互连结构上方，且该接合层的一第二层形成于该载体基板上方。
5.根据权利要求1所述的方法，其特征在于，该接合层包含一第一层及与该第一层接触的一第二层。
6.一种半导体元件的形成方法，其特征在于，包含以下步骤：
在一基板的一前侧上方形成一鳍片；
在该鳍片上方形成一栅极结构及多个源极/漏极结构；
在该栅极结构上方形成一前侧互连结构；
在一载体基板上方形成一导热层；
在该导热层上方形成一介电层及多个接合衬垫，其中该导热层相较于该介电层具有一较高导热率；及
将该介电层及所述多个接合衬垫接合至该前侧互连结构。
7.根据权利要求6所述的方法，其特征在于，该导热层为双层。
8.一种半导体元件，其特征在于，包含：
一基板；
该基板的一前侧上方的一晶体管，该晶体管包含一通道区、该通道区上方的一栅极结构及该栅极结构的多个相对侧上的多个源极/漏极结构；
该晶体管上方的一前侧互连结构；
该前侧互连结构上方的一导热层，其中该导热层相较于该前侧互连结构的距该基板最远的一介电层具有一较高导热率；及
该基板的一背侧上方的一背侧互连结构。
9.根据权利要求8所述的半导体元件，其特征在于，该导热层包含与该前侧互连结构接触的一第一层及该第一层上方的一第二层，且该第一层的一导热率低于该第二层的一导热率。
10.根据权利要求8所述的半导体元件，其特征在于，该导热层包含与该前侧互连结构接触的一第一层及该第一层上方的一第二层，且该第一层的一导热率高于该第二层的一导热率。
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