CN113488386A - Method and device for preparing self-aligned T-shaped gate high-mobility transistor - Google Patents
Method and device for preparing self-aligned T-shaped gate high-mobility transistor Download PDFInfo
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
Abstract
The invention discloses a method and a device for preparing a self-aligned T-shaped gate high-mobility transistor, wherein a substrate is subjected to first deposition and first etching treatment, so that a first deposition layer and a second deposition layer in a preset shape are deposited on the substrate; forming a first side wall and a second side wall on the side wall of the second deposition layer; carrying out ion implantation treatment and annealing treatment on the substrate to form a source drain metal deposition layer; polishing a fifth deposition layer formed after the third deposition treatment is carried out on the substrate, and then completely corroding the second side wall; performing fourth deposition and fourth etching treatment on the substrate to form a third side wall; carrying out gate metal deposition and etching treatment on the substrate to form a metal deposition layer with a T-shaped gate structure; and completely etching the first side wall, the third side wall, the first deposition layer and the fifth deposition layer. The invention adopts the side wall transfer technology, reduces the photoetching difficulty and improves the production efficiency.
Description
Technical Field
The invention relates to the technical field of transistor preparation, in particular to a method and a device for preparing a self-aligned T-shaped gate high-mobility transistor.
Background
The T-shaped gate high-mobility transistor can work in the fields of ultrahigh frequency (millimeter wave) and ultra high speed, but with the improvement of communication frequency nowadays, the requirement on the working frequency of the T-shaped gate high-mobility transistor is also improved, the working frequency of the T-shaped gate high-mobility transistor is improved, and the most effective method is to reduce the gate length.
According to the conventional process, the gate length is generally reduced by improving the lithography precision of a lithography machine. However, the manufacturing cost is greatly increased while the photolithography precision is improved, and the difficulty of the corresponding manufacturing process is also improved. For devices with a grid length of 100nm or less, an electron beam lithography machine is used, which is expensive and low in efficiency. In addition, the process deviation increases, which causes a decrease in yield and a narrowing of the process window.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the method and the device for manufacturing the self-aligned T-shaped gate high-mobility transistor are provided, the photoetching difficulty is reduced, and the production efficiency is improved.
In order to solve the above technical problem, the present invention provides a method for manufacturing a self-aligned T-gate high mobility transistor, comprising:
s1: carrying out first deposition and first etching treatment on a substrate to enable a first deposition layer and a second deposition layer in a preset shape to be deposited on the substrate, wherein the preset shape is a step shape;
s2: performing second deposition and second etching treatment on the substrate to form a first side wall and a second side wall on the side wall of the second deposition layer, and completely corroding the second deposition layer;
s3: carrying out ion implantation treatment and annealing treatment on the substrate to form a source and drain region, and carrying out metal deposition on the source and drain region to form a source and drain metal deposition layer;
s4: carrying out third deposition treatment on the substrate, polishing a fifth deposition layer formed by the third deposition treatment until the tops of the first side wall and the second side wall are exposed, and then completely corroding the second side wall;
s5: performing fourth deposition and fourth etching treatment on the substrate to form third side walls on the left and right sides of the interval between the first side wall and the fifth deposition layer, wherein the third side walls are two parallel walls, and etching treatment is performed on the first deposition layer deposited in the middle of the third side walls;
s6: carrying out gate metal deposition and etching treatment on the substrate to form a metal deposition layer with a T-shaped gate structure;
s7: and completely etching the first side wall, the third side wall, the first deposition layer and the fifth deposition layer.
Further, before performing step S1, the substrate is a three-layer structure substrate; the three-layer structure comprises a barrier layer, a channel layer and a substrate from top to bottom in sequence.
Further, the substrate is subjected to a first deposition and a first etching treatment, specifically:
depositing a first medium on the substrate to form a first deposition layer, depositing a second medium on the substrate to generate a second deposition layer, and etching the second deposition layer, wherein the thickness of the second medium deposition layer is greater than that of the first medium deposition layer.
Further, performing second deposition and second etching treatment on the substrate to form a first side wall and a second side wall on the side wall of the step-shaped deposition layer, specifically:
isotropic deposition is carried out on the third medium on the substrate to form a third deposition layer, anisotropic etching is carried out on the third deposition layer to form a first side wall at the side wall of the step-shaped second deposition layer formed in the step S1, isotropic deposition is carried out on the fourth medium on the substrate to form a fourth deposition layer, anisotropic etching is carried out on the fourth deposition layer to form a second side wall on one side of the first side wall, and the heights of the first side wall and the second side wall are the same as the thickness of the second deposition layer.
Further, the ion implantation treatment and the annealing treatment are carried out on the substrate, and the method specifically comprises the following steps:
and carrying out ion implantation treatment and annealing treatment on the channel layer, the barrier layer and the first deposition layer of the substrate, wherein the channel layer, the barrier layer and the first deposition layer of the substrate corresponding to the first side wall and the second side wall are not treated.
Further, the present invention also provides a device for manufacturing a self-aligned T-gate high mobility transistor, comprising: the first processing module, the second processing module, the third processing module, the fourth processing module, the fifth processing module, the sixth processing module and the seventh processing module:
the first processing module is used for carrying out first deposition and first etching processing on a substrate so as to enable a first deposition layer and a second deposition layer in a preset shape to be deposited on the substrate, and the preset shape is step-shaped;
the second processing module is used for carrying out second deposition and second etching processing on the substrate so as to form a first side wall and a second side wall on the side wall of the second deposition layer and completely corrode the second deposition layer;
the third processing module is used for carrying out ion implantation processing and annealing processing on the substrate to form a source and drain electrode area, and carrying out metal deposition on the source and drain electrode area to form a source and drain metal deposition layer;
the fourth processing module is used for carrying out third deposition processing on the substrate, polishing a fifth deposition layer formed by the third deposition processing until the tops of the first side wall and the second side wall are exposed, and then completely corroding the second side wall;
the fifth processing module is used for carrying out fourth deposition and fourth etching processing on the substrate so as to form third side walls on the left side and the right side of the interval between the first side wall and the fifth deposition layer, the third side walls are two parallel walls, and etching processing is carried out on the first deposition layer deposited in the middle of the third side walls;
the sixth processing module is used for carrying out gate metal deposition and etching processing on the substrate to form a metal deposition layer with a T-shaped gate structure;
the seventh processing module is configured to completely etch the first sidewall, the third sidewall, the first deposition layer, and the fifth deposition layer.
Further, the substrate in the first processing module is a three-layer structure substrate; the three-layer structure comprises a barrier layer, a channel layer and a substrate from top to bottom in sequence.
Further, the first processing module performs a first deposition and a first etching process on the substrate, specifically:
depositing a first medium on the substrate to form a first deposition layer, depositing a second medium on the substrate to generate a second deposition layer, and etching the second deposition layer, wherein the thickness of the second medium deposition layer is greater than that of the first medium deposition layer.
Further, a second processing module performs second deposition and second etching processing on the substrate to form a first side wall and a second side wall on the side wall of the step-shaped deposition layer, specifically:
the third medium is isotropically deposited on the substrate to form a third deposition layer, then the third deposition layer is anisotropically etched, so that a first side wall is formed at the side wall of the step-shaped second deposition layer formed in the first processing module, then the fourth medium is isotropically deposited on the substrate to form a fourth deposition layer, then the fourth deposition layer is anisotropically etched, so that a second side wall is formed on one side of the first side wall, and the heights of the first side wall and the second side wall are the same as the thickness of the second deposition layer.
Further, the third processing module performs ion implantation processing and annealing processing on the substrate, specifically:
and carrying out ion implantation treatment and annealing treatment on the channel layer, the barrier layer and the first deposition layer of the substrate, wherein the channel layer, the barrier layer and the first deposition layer of the substrate corresponding to the first side wall and the second side wall are not treated.
Compared with the prior art, the preparation method and the device of the self-aligned T-shaped gate high-mobility transistor have the following beneficial effects:
carrying out first deposition and first etching treatment on a substrate to enable a first deposition layer and a second deposition layer in a preset shape to be deposited on the substrate, wherein the preset shape is a step shape; performing second deposition and second etching treatment on the substrate to form a first side wall and a second side wall on the side wall of the second deposition layer, and completely corroding the second deposition layer; carrying out ion implantation treatment and annealing treatment on the substrate to form a source and drain region, and carrying out metal deposition on the source and drain region to form a source and drain metal deposition layer; carrying out third deposition treatment on the substrate, polishing a fifth deposition layer formed by the third deposition treatment until the tops of the first side wall and the second side wall are exposed, and then completely corroding the second side wall; performing fourth deposition and fourth etching treatment on the substrate to form third side walls on the left and right sides of the interval between the first side wall and the fifth deposition layer, wherein the third side walls are two parallel walls, and etching treatment is performed on the first deposition layer deposited in the middle of the third side walls; carrying out gate metal deposition and etching treatment on the substrate to form a metal deposition layer with a T-shaped gate structure; and completely etching the first side wall, the third side wall, the first deposition layer and the fifth deposition layer. The invention adopts the side wall transfer technology to replace the photoetching technology in the preparation of the traditional T-shaped gate high-mobility transistor, thereby reducing the photoetching difficulty and improving the production efficiency.
Drawings
FIG. 1 is a schematic flow chart diagram illustrating one embodiment of a method for fabricating a self-aligned T-gate high mobility transistor according to the present invention;
FIG. 2 is a schematic structural diagram of an embodiment of a self-aligned T-gate high mobility transistor fabrication apparatus provided in the present invention;
fig. 3 is a process diagram of an embodiment of a method for fabricating a self-aligned T-gate high mobility transistor according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
Referring to fig. 1, fig. 1 is a schematic flow chart of an embodiment of a method for manufacturing a self-aligned T-gate high mobility transistor according to the present invention, as shown in fig. 1, the method includes steps 101 to 107, specifically as follows:
step 101: the method comprises the steps of carrying out first deposition and first etching treatment on a substrate to enable a first deposition layer and a second deposition layer with a preset shape to be deposited on the substrate, wherein the preset shape is a step shape.
In this embodiment, the substrate is a three-layer structure substrate, see fig. 3 a; the three-layer structure comprises a barrier layer, a channel layer and a substrate from top to bottom in sequence; first depositing a first dielectric on the barrier layer of the substrate to form a first deposition layer, see fig. 3 b; depositing a second medium on the first deposition layer to generate a second deposition layer, and etching the second deposition layer, in this embodiment, completely etching away the left half part of the second deposition layer, and leaving the right half part of the second deposition layer, so that the etched second deposition layer and the first deposition layer form a step-shaped deposition layer, as shown in fig. 3 c; it can also be understood that, the right half of the second deposition layer can be selectively etched away, so that the left half of the second deposition layer and the first deposition layer form a step-shaped deposition layer, in this embodiment, the thickness of the first deposition layer is 20nm, the thickness of the second deposition layer is 300nm, the thickness of the first deposition layer and the thickness of the second deposition layer can be preset as required, and the thickness of the second medium deposition layer is greater than the thickness of the first medium deposition layer.
Step 102: and carrying out second deposition and second etching treatment on the substrate to form a first side wall and a second side wall on the side wall of the second deposition layer, and completely corroding the second deposition layer.
In this embodiment, on the basis that the step-shaped first deposition layer and the step-shaped second deposition layer are formed on the substrate in step 101, isotropic deposition is performed using a third medium to form a third deposition layer, see fig. 3 d; the term "isotropic" as used herein refers to a characteristic that physical and chemical properties of an object do not change with a difference in direction, that is, the measured performance values of an object in different directions are completely the same, isotropic deposition is used to make a third deposition layer uniformly cover each position of a step-like deposition layer, and then the third deposition layer is subjected to anisotropic etching, where the anisotropic etching generally refers to an etching method in which different planes exhibit different etching rates. So that first side walls are formed at the side walls of the step-shaped second deposition layer formed in step 101, see fig. 3 e; using the same method, isotropic deposition is performed on the fourth medium on the substrate to form a fourth deposition layer, see fig. 3 f; performing anisotropic etching on the fourth deposition layer to form a second sidewall on one side of the first sidewall, as shown in fig. 3 g; the heights of the first side wall and the second side wall are the same as the thickness of the second deposition layer, in this embodiment, the thickness of the third deposition layer is 50nm, the thickness of the fourth deposition layer is 100nm, and the thickness of the first deposition layer and the thickness of the second deposition layer can be preset according to requirements; finally, the second deposited layer is completely etched, see fig. 3 h.
Step 103: and carrying out ion implantation treatment and annealing treatment on the substrate to form a source and drain region, and carrying out metal deposition on the source and drain region to form a source and drain metal deposition layer.
In this embodiment, the channel layer and the barrier layer of the substrate corresponding to the first side wall and the second side wall, and the channel layer, the barrier layer of the substrate and the first deposition layer outside the first deposition layer are subjected to ion implantation treatment and annealing treatment to form a source/drain region, which is shown in fig. 3 i; the thickness of the source/drain region is from the first deposition layer to the barrier layer of the substrate but not to the channel layer of the substrate, and metal deposition is performed on the left and right sides of the source/drain region to form a source/drain metal deposition layer, as shown in fig. 3 j. In this embodiment, the thickness of the formed source/drain metal deposition layer is smaller than the thickness of the first sidewall and the second sidewall.
Step 104: and carrying out third deposition treatment on the substrate, polishing a fifth deposition layer formed by the third deposition treatment until the tops of the first side wall and the second side wall are exposed, and then completely corroding the second side wall.
In this embodiment, on the basis of step 103, a fifth medium is used for deposition processing to form a fifth deposition layer, see fig. 3 k; in this embodiment, the thickness of the fifth deposition layer is 500nm, and the fifth deposition layer is polished by using a chemical mechanical polishing process, the thickness of the polishing process is 250nm, until the fifth deposition layer is polished to a plane exposing the tops of the first side wall and the second side wall, as shown in fig. 3 l; the second sidewall is then etched completely to form a gap between the first sidewall and the fifth deposition layer, as shown in fig. 3 m.
Step 105: and carrying out fourth deposition and fourth etching treatment on the substrate so as to form third side walls on the left side and the right side of the interval between the first side wall and the fifth deposition layer, wherein the third side walls are two parallel walls, and etching treatment is carried out on the first deposition layer deposited in the middle of the third side walls.
In this embodiment, on the basis of step 104, isotropic deposition is performed using a sixth medium to form a sixth deposition layer, see fig. 3 n; enabling the sixth deposition layer to uniformly cover each position of the current substrate surface, and then performing anisotropic etching on the sixth deposition layer to form third side walls on the left side and the right side of the interval between the first side wall and the fifth deposition layer, wherein the third side walls are two parallel wall bodies, as shown in fig. 3 o; etching the first deposition layer deposited in the middle of the third sidewall, as shown in fig. 3 p; in this embodiment, the distance between the two walls of the third sidewall is the gate length of the T-shaped gate, and the thickness of the sixth deposition layer is 30 nm.
Step 106: and carrying out gate metal deposition and etching treatment on the substrate to form a metal deposition layer with a T-shaped gate structure.
In this embodiment, on the basis of step 105, isotropic deposition is performed using a gate metal to form a gate metal deposition layer, see fig. 3 q; etching the gate metal in a preset shape to form a cap of the T-shaped gate on the uppermost layer of the substrate, and etching other gate metals beyond the preset cap size range, see fig. 3 r.
Step 107: and completely etching the first side wall, the third side wall, the first deposition layer and the fifth deposition layer.
In this embodiment, the first sidewall, the third sidewall, the first deposition layer, and the fifth deposition layer are completely etched, so that the shape of the T-shaped gate can be independently displayed, as shown in fig. 3 s.
Referring to fig. 2, fig. 2 is a schematic structural diagram of an embodiment of a device for manufacturing a self-aligned T-gate high mobility transistor according to the present invention, as shown in fig. 2, the method includes: the first processing module 201, the second processing module 202, the third processing module 203, the fourth processing module 204, the fifth processing module 205, the sixth processing module 206 and the seventh processing module 207 are specifically as follows:
the first processing module 201 is configured to perform a first deposition and a first etching process on a substrate, so that a first deposition layer and a second deposition layer having a preset shape are deposited on the substrate, where the preset shape is a step shape. In this embodiment, the substrate is a three-layer structure substrate; the three-layer structure comprises a barrier layer, a channel layer and a substrate from top to bottom in sequence; depositing a first medium on the barrier layer of the substrate to form a first deposition layer, depositing a second medium on the first deposition layer to form a second deposition layer, and etching the second deposition layer, in this embodiment, the left half part of the second deposition layer is completely etched, and the right half part of the second deposition layer is left, so that the etched second deposition layer and the first deposition layer form a step-shaped deposition layer, it can also be understood that the right half part of the second deposition layer can be selectively etched, so that the left half part of the second deposition layer and the first deposition layer form a step-shaped deposition layer, in this embodiment, the thickness of the first deposition layer is 20nm, the thickness of the second deposition layer is 300nm, the thickness of the first deposition layer and the thickness of the second deposition layer can be preset as required, and the thickness of the second medium deposition layer is greater than the thickness of the first medium deposition layer.
The second processing module 202 is configured to perform a second deposition and a second etching process on the substrate, so as to form a first sidewall and a second sidewall on the sidewalls of the second deposition layer, and completely etch the second deposition layer. In this embodiment, on the basis of forming the step-shaped first deposition layer and the step-shaped second deposition layer on the substrate in the first processing module, isotropic deposition is performed by using a third medium to form a third deposition layer, where isotropic deposition refers to a characteristic that properties in the aspects of physics, chemistry, and the like of an object do not change due to different directions, that is, performance values of a certain object measured in different directions are completely the same, isotropic deposition is used to enable the third deposition layer to uniformly cover each position of the step-shaped deposition layer, and then anisotropic etching is performed on the third deposition layer, where anisotropic etching generally refers to an etching method in which different planes exhibit different etching rates. In this embodiment, the thickness of the third deposition layer is 50nm, the thickness of the fourth deposition layer is 100nm, and the thickness of the first deposition layer and the thickness of the second deposition layer can be preset as required.
The third processing module 203 is configured to perform ion implantation processing and annealing processing on the substrate to form a source/drain region, and perform metal deposition on the source/drain region to form a source/drain metal deposition layer. In this embodiment, the channel layer and the barrier layer of the substrate corresponding to the first side wall and the second side wall, and the channel layer, the barrier layer and the first deposition layer of the substrate outside the first deposition layer are subjected to ion implantation treatment and annealing treatment to form a source and drain region, the thickness of the source and drain region exceeds the barrier layer of the substrate from the first deposition layer downwards but does not exceed the channel layer of the substrate, and metal deposition is performed on the left side and the right side of the source and drain region to form a source and drain metal deposition layer. In this embodiment, the thickness of the formed source/drain metal deposition layer is smaller than the thickness of the first sidewall and the second sidewall.
The fourth processing module 204 is configured to perform a third deposition process on the substrate, perform a polishing process on a fifth deposition layer formed by the third deposition process until the tops of the first side wall and the second side wall are exposed, and then completely corrode the second side wall. In this embodiment, on the basis of the third processing module, use the fifth medium to carry out deposition processing, form the fifth sedimentary deposit, the thickness of the fifth sedimentary deposit is 500nm in this embodiment, use chemical machinery to carry out polishing processing to the fifth sedimentary deposit, the thickness of polishing is 250nm, until polishing becomes a plane that exposes first side wall and second side wall top, carry out complete corrosion to the second side wall again, make and form an interval between first side wall and the fifth sedimentary deposit.
The fifth processing module 205 is configured to perform a fourth deposition and a fourth etching on the substrate, so as to form third side walls on left and right sides of the first side wall and the fifth deposition layer at an interval, where the third side walls are two parallel walls, and perform an etching process on the first deposition layer deposited in the middle of the third side wall. In this embodiment, on the basis of the fourth processing module, isotropic deposition is performed using a sixth medium to form a sixth deposition layer, so that the sixth deposition layer covers each position of the current substrate surface uniformly, and then anisotropic etching is performed on the sixth deposition layer, so that third side walls are formed on the left and right sides of the first side wall and the fifth deposition layer at intervals, the third side walls are two parallel walls, etching is performed on the first deposition layer deposited in the middle of the third side wall, and the barrier layer of the substrate is exposed at the corresponding position.
The sixth processing module 206 is configured to perform gate metal deposition and etching on the substrate to form a metal deposition layer with a T-shaped gate structure. In this embodiment, on the basis of the fifth processing module, isotropic deposition is performed on gate metal to form a gate metal deposition layer, etching of a preset shape is performed on the gate metal, a cap of a T-shaped gate is formed on the uppermost layer of the substrate, and etching is performed on other gate metals beyond the size range of the preset cap.
The seventh processing module 207 is configured to completely etch the first sidewall, the third sidewall, the first deposition layer, and the fifth deposition layer. In this embodiment, the first side wall, the third side wall, the first deposition layer, and the fifth deposition layer are completely etched, so that the shape of the T-shaped gate can be independently displayed.
In this embodiment 1, the first dielectric, the second dielectric, the third dielectric, the fourth dielectric, the fifth dielectric, and the sixth dielectric mentioned in the above steps are one of silicon dioxide and silicon nitride.
In summary, according to the method for manufacturing a self-aligned T-shaped gate high mobility transistor provided by the present invention, a first deposition layer and a first etching process are performed on a substrate, so that a first deposition layer and a second deposition layer with a preset shape are deposited on the substrate, and the preset shape is a step shape; performing second deposition and second etching treatment on the substrate to form a first side wall and a second side wall on the side wall of the second deposition layer, and completely corroding the second deposition layer; carrying out ion implantation treatment and annealing treatment on the substrate to form a source and drain region, and carrying out metal deposition on the source and drain region to form a source and drain metal deposition layer; carrying out third deposition treatment on the substrate, polishing a fifth deposition layer formed by the third deposition treatment until the tops of the first side wall and the second side wall are exposed, and then completely corroding the second side wall; performing fourth deposition and fourth etching treatment on the substrate to form third side walls on the left and right sides of the interval between the first side wall and the fifth deposition layer, wherein the third side walls are two parallel walls, and etching treatment is performed on the first deposition layer deposited in the middle of the third side walls; carrying out gate metal deposition and etching treatment on the substrate to form a metal deposition layer with a T-shaped gate structure; and completely etching the first side wall, the third side wall, the first deposition layer and the fifth deposition layer. Compared with the prior art, the side wall transfer technology is adopted, the photoetching difficulty is reduced, and the production efficiency is improved.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and substitutions can be made without departing from the technical principle of the present invention, and these modifications and substitutions should also be regarded as the protection scope of the present invention.
Claims (10)
1. A method for preparing a self-aligned T-shaped gate high mobility transistor is characterized by comprising the following steps:
s1: carrying out first deposition and first etching treatment on a substrate to enable a first deposition layer and a second deposition layer in a preset shape to be deposited on the substrate, wherein the preset shape is a step shape;
s2: performing second deposition and second etching treatment on the substrate to form a first side wall and a second side wall on the side wall of the second deposition layer, and completely corroding the second deposition layer;
s3: carrying out ion implantation treatment and annealing treatment on the substrate to form a source and drain region, and carrying out metal deposition on the source and drain region to form a source and drain metal deposition layer;
s4: carrying out third deposition treatment on the substrate, polishing a fifth deposition layer formed by the third deposition treatment until the tops of the first side wall and the second side wall are exposed, and then completely corroding the second side wall;
s5: performing fourth deposition and fourth etching treatment on the substrate to form third side walls on the left and right sides of the interval between the first side wall and the fifth deposition layer, wherein the third side walls are two parallel walls, and etching treatment is performed on the first deposition layer deposited in the middle of the third side walls;
s6: carrying out gate metal deposition and etching treatment on the substrate to form a metal deposition layer with a T-shaped gate structure;
s7: and completely etching the first side wall, the third side wall, the first deposition layer and the fifth deposition layer.
2. The method of claim 1, wherein before performing step S1, the substrate is a three-layer structure substrate; the three-layer structure comprises a barrier layer, a channel layer and a substrate from top to bottom in sequence.
3. The method for manufacturing a self-aligned T-gate high mobility transistor according to claim 2, wherein the first deposition and the first etching are performed on the substrate, specifically:
depositing a first medium on the substrate to form a first deposition layer, depositing a second medium on the substrate to generate a second deposition layer, and etching the second deposition layer, wherein the thickness of the second medium deposition layer is greater than that of the first medium deposition layer.
4. The method according to claim 3, wherein the substrate is subjected to a second deposition and a second etching process to form a first sidewall and a second sidewall on the sidewall of the step-shaped deposition layer, and specifically:
isotropic deposition is carried out on the third medium on the substrate to form a third deposition layer, anisotropic etching is carried out on the third deposition layer to form a first side wall at the side wall of the step-shaped second deposition layer formed in the step S1, isotropic deposition is carried out on the fourth medium on the substrate to form a fourth deposition layer, anisotropic etching is carried out on the fourth deposition layer to form a second side wall on one side of the first side wall, and the heights of the first side wall and the second side wall are the same as the thickness of the second deposition layer.
5. The method according to claim 4, wherein the substrate is subjected to ion implantation treatment and annealing treatment, and specifically comprises:
and carrying out ion implantation treatment and annealing treatment on the channel layer, the barrier layer and the first deposition layer of the substrate, wherein the channel layer, the barrier layer and the first deposition layer of the substrate corresponding to the first side wall and the second side wall are not treated.
6. An apparatus for fabricating a self-aligned T-gate high mobility transistor, comprising: the first processing module, the second processing module, the third processing module, the fourth processing module, the fifth processing module, the sixth processing module and the seventh processing module:
the first processing module is used for carrying out first deposition and first etching processing on a substrate so as to enable a first deposition layer and a second deposition layer in a preset shape to be deposited on the substrate, and the preset shape is step-shaped;
the second processing module is used for carrying out second deposition and second etching processing on the substrate so as to form a first side wall and a second side wall on the side wall of the second deposition layer and completely corrode the second deposition layer;
the third processing module is used for carrying out ion implantation processing and annealing processing on the substrate to form a source and drain electrode area, and carrying out metal deposition on the source and drain electrode area to form a source and drain metal deposition layer;
the fourth processing module is used for carrying out third deposition processing on the substrate, polishing a fifth deposition layer formed by the third deposition processing until the tops of the first side wall and the second side wall are exposed, and then completely corroding the second side wall;
the fifth processing module is used for carrying out fourth deposition and fourth etching processing on the substrate so as to form third side walls on the left side and the right side of the interval between the first side wall and the fifth deposition layer, the third side walls are two parallel walls, and etching processing is carried out on the first deposition layer deposited in the middle of the third side walls;
the sixth processing module is used for carrying out gate metal deposition and etching processing on the substrate to form a metal deposition layer with a T-shaped gate structure;
the seventh processing module is configured to completely etch the first sidewall, the third sidewall, the first deposition layer, and the fifth deposition layer.
7. The apparatus of claim 6, wherein the substrate in the first processing module is a three-layer substrate; the three-layer structure comprises a barrier layer, a channel layer and a substrate from top to bottom in sequence.
8. The apparatus according to claim 7, wherein the first processing module performs a first deposition and a first etching process on the substrate, and specifically comprises:
depositing a first medium on the substrate to form a first deposition layer, depositing a second medium on the substrate to generate a second deposition layer, and etching the second deposition layer, wherein the thickness of the second medium deposition layer is greater than that of the first medium deposition layer.
9. The apparatus according to claim 8, wherein the second processing module performs a second deposition and a second etching on the substrate to form a first sidewall and a second sidewall on the sidewall of the step-shaped deposition layer, and specifically comprises:
the third medium is isotropically deposited on the substrate to form a third deposition layer, then the third deposition layer is anisotropically etched, so that a first side wall is formed at the side wall of the step-shaped second deposition layer formed in the first processing module, then the fourth medium is isotropically deposited on the substrate to form a fourth deposition layer, then the fourth deposition layer is anisotropically etched, so that a second side wall is formed on one side of the first side wall, and the heights of the first side wall and the second side wall are the same as the thickness of the second deposition layer.
10. The apparatus of claim 9, wherein the third processing module performs ion implantation and annealing on the substrate, and specifically comprises:
and carrying out ion implantation treatment and annealing treatment on the channel layer, the barrier layer and the first deposition layer of the substrate, wherein the channel layer, the barrier layer and the first deposition layer of the substrate corresponding to the first side wall and the second side wall are not treated.
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