CN113472307A - Piezoelectric MEMS silicon resonator, forming method thereof and electronic equipment - Google Patents
Piezoelectric MEMS silicon resonator, forming method thereof and electronic equipment Download PDFInfo
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Images
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/02244—Details of microelectro-mechanical resonators
- H03H9/02259—Driving or detection means
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/02244—Details of microelectro-mechanical resonators
- H03H9/02338—Suspension means
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/02244—Details of microelectro-mechanical resonators
- H03H9/02433—Means for compensation or elimination of undesired effects
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
- H03H2003/027—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks the resonators or networks being of the microelectro-mechanical [MEMS] type
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- Physics & Mathematics (AREA)
- Acoustics & Sound (AREA)
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
Abstract
The invention discloses a piezoelectric MEMS silicon resonator, a forming method thereof and electronic equipment. The piezoelectric MEMS silicon resonator includes: a silicon substrate; a lower cavity, a top plane of the lower cavity being higher or lower than a top plane of the substrate; a remaining silicon layer located over the lower cavity; a piezoelectric layer and an upper electrode over the remaining silicon layer. The forming method comprises the following steps: providing a silicon substrate; sequentially forming a sacrificial silicon layer, a reserved silicon layer, a piezoelectric layer and an upper electrode on a silicon substrate; and opening an etching window, and removing the sacrificial silicon layer to form a lower cavity, wherein one of the silicon substrate and the reserved silicon layer is subjected to common N-type doping under the condition that the sacrificial silicon layer is subjected to P-type doping with the second doping concentration, and the other one of the silicon substrate and the reserved silicon layer is subjected to P-type doping with the first doping concentration, or one of the silicon substrate and the reserved silicon layer is subjected to common P-type doping under the condition that the sacrificial silicon layer is subjected to N-type doping with the second doping concentration, and the other one of the silicon substrate and the reserved silicon layer is subjected to N-type doping with the first doping concentration, wherein the first doping concentration is greater than the second doping concentration.
Description
Technical Field
The invention relates to the technical field of resonators, in particular to a piezoelectric MEMS silicon resonator, a forming method thereof and electronic equipment.
Background
The piezoelectric MEMS silicon resonator is an MEMS resonator which uses silicon as a resonance main body and performs mechanical driving and electrical signal detection by using the piezoelectric effect of a piezoelectric film, and such devices generally need to suspend a device part in the air during processing.
(1) Referring to fig. 1 and 2, 1001 is a bottom silicon layer of an SOI silicon wafer, 1002 is a buried oxide layer of the SOI silicon wafer, 1003 is a top silicon layer of the SOI silicon wafer, 1004 is a lower electrode, 1005 is a piezoelectric layer, and 1006 is an upper electrode. After the cantilever beam is manufactured in the top silicon layer of the SOI silicon wafer as shown in figure 1, etching is carried out from the back surface to remove the bottom silicon, and finally, the buried oxide layer is washed away by HF to release the cantilever beam, so that the structure shown in figure 2 is obtained. This process is commonly referred to as a back-etching process. Because the resonator usually needs to be sealed and packaged when in use, the device manufactured by the back etching process needs to be packaged on both the top surface and the bottom surface, so that the processing cost and the final thickness of the device are increased, and on the other hand, the strength of the substrate is reduced by adopting the back etching process, the high-density arrangement of the device is not facilitated, so that the number of the devices on the whole wafer is reduced, and the cost of a single device is increased.
(2) The SOI silicon chip with the cavity is manufactured by the following general manufacturing process: and sequentially depositing and patterning a lower electrode, a piezoelectric layer and an upper electrode on the SOI with the cavity, etching away top silicon and an oxygen buried layer at the free end and two sides of the beam to release the beam, and finally packaging in a bonded silicon cap mode. Firstly, due to the low air pressure in the cavity of the cavity SOI, the top silicon layer on the cavity is usually recessed under atmospheric pressure, and the device fabricated on the cavity is also bent accordingly; when the cavity is vented to atmosphere after the beam is released, the top silicon and buried oxide layers tend to return to a flat state while the initial state of the electrode layers and piezoelectric layers is a curved state, thus creating a large stress between the top silicon and piezoelectric layers during this process. This stress will result in a reduction of the device quality factor Q. Second, SOI with cavities needs to be tailored to different resonators, and thus, the fabrication cycle is long and very expensive, and thus the cost of devices fabricated using cavity SOI also increases.
The devices manufactured by the two processes have common defects, although the cantilever beam is released, the fixed end of the cantilever beam is fixed on the bottom silicon by the original silicon-silicon oxide interface of the SOI, and the fixation belongs to rigid connection, so that the performance of the devices is seriously influenced by parasitic stress, packaging stress, environmental thermal stress and the like in the SOI, the resonant frequency drifts, and the stability is not high. Meanwhile, devices such as resonators are easily affected by external impact, vibration, thermal noise, etc., and the devices manufactured by these two processes cannot effectively shield such noise. Therefore, it is difficult to further improve the quality factor and stability of the device manufactured by the conventional process, which becomes a key obstacle to commercialization of the product.
Disclosure of Invention
In view of the above, the present invention provides a piezoelectric MEMS silicon resonator with less resonant frequency drift and high stability, a method for manufacturing the same, and an electronic device including the piezoelectric MEMS silicon resonator.
A first aspect of the present invention provides a piezoelectric MEMS silicon resonator, comprising: a silicon substrate; a lower cavity located above the silicon substrate, a top plane of the lower cavity being higher or lower than a top plane of the substrate; a remaining silicon layer located over the lower cavity; a piezoelectric layer and an upper electrode stacked in sequence over the remaining silicon layer.
Optionally, the remaining silicon layer is monocrystalline silicon.
Optionally, one of the silicon substrate and the remaining silicon layer is doped with a common N-type dopant, and the other of the silicon substrate and the remaining silicon layer is doped with a P-type dopant with a first doping concentration; or, one of the silicon substrate and the reserved silicon layer is doped in a common P type, and the other one of the silicon substrate and the reserved silicon layer is doped in an N type with a first doping concentration.
Optionally, the first doping concentration is 1019To 9X 1020cm-3。
Optionally, the method further comprises: a lower electrode located between the remaining silicon layer and the piezoelectric layer.
Optionally, the piezoelectric MEMS silicon resonator is one of: cantilever beam, extensional vibration mode, thickness longitudinal vibration mode, lamb wave vibration mode, in-plane bending vibration mode, surface acoustic wave vibration mode.
The second aspect of the present invention provides a method for forming a piezoelectric MEMS silicon resonator, including: providing a silicon substrate; forming a sacrificial silicon layer over the silicon substrate; forming a remaining silicon layer over the sacrificial silicon layer; sequentially forming a piezoelectric layer and an upper electrode on the reserved silicon layer; and opening an etching window, and then selectively removing the sacrificial silicon layer to form a lower cavity, wherein one of the silicon substrate and the reserved silicon layer is doped in a common N type under the condition that the sacrificial silicon layer is doped in a P type with a second doping concentration, and the other one of the silicon substrate and the reserved silicon layer is doped in a P type with a first doping concentration, or one of the silicon substrate and the reserved silicon layer is doped in a common P type under the condition that the sacrificial silicon layer is doped in an N type with a second doping concentration, and the other one of the silicon substrate and the reserved silicon layer is doped in an N type with a first doping concentration.
Optionally, the first doping concentration is greater than the second doping concentration.
Optionally, the first doping concentration is 1019To 9X 1020cm-3The second doping concentration is 1013To 9X 1018cm-3。
Optionally, the step of forming a sacrificial silicon layer over the silicon substrate comprises: the sacrificial silicon layer is epitaxially formed on the silicon substrate.
Optionally, the step of forming a remaining silicon layer over the sacrificial silicon layer comprises: the remaining silicon layer is epitaxially formed over the sacrificial silicon layer.
Optionally, the method further comprises: a lower electrode is formed between the remaining silicon layer and the piezoelectric layer.
Optionally, a bottom plane of the sacrificial silicon layer is lower than a top plane of the silicon substrate, and a top plane of the sacrificial silicon layer is higher than the top plane of the silicon substrate; or the bottom plane of the sacrificial silicon layer is lower than the top plane of the silicon substrate, and the top plane of the sacrificial silicon layer is equal to the top plane of the silicon substrate; or the bottom plane of the sacrificial silicon layer is equal to the top plane of the silicon substrate, and the top plane of the sacrificial silicon layer is higher than the top plane of the silicon substrate; or the bottom plane of the sacrificial silicon layer is lower than the top plane of the silicon substrate, and the top plane of the sacrificial silicon layer is lower than the top plane of the silicon substrate.
Optionally, the piezoelectric MEMS silicon resonator is a cantilever beam type, an extensional vibration mode, a thickness longitudinal vibration mode, a lamb wave vibration mode, an in-plane bending vibration mode, or a surface acoustic wave vibration mode.
In a third aspect, the invention provides a piezoelectric MEMS silicon resonator, which is manufactured by the forming method disclosed by the invention.
A fourth aspect of the present invention provides an electronic device, comprising the piezoelectric MEMS silicon resonator disclosed in the present invention.
According to the technical scheme of the invention, the use of the cavity SOI and the common SOI is avoided, so that the cost is reduced, and meanwhile, the bending phenomenon existing in the manufacturing process of the SOI with the cavity is avoided, so that the stress problem caused by the release of the cavity SOI is avoided. Second, in the present example, gold-gold bonding is used instead of SOI, and because gold is a soft material, the stress problem due to the silicon oxide-silicon hard bond is eliminated. In addition, a three-dimensional structure (such as a beam structure which is longitudinally raised or lowered) can be manufactured at the fixed end of the beam, and the interference of external stress, vibration and thermal noise can be greatly eliminated, so that the device has higher stability and signal-to-noise ratio, and the three-dimensional structure can prevent the energy of beam vibration from being dissipated outwards, thereby being beneficial to improving the quality factor. Third, the thickness of the grown silicon film in the silicon epitaxial process is controllable and wide (for example, more than 20 microns), so that the silicon epitaxial process has certain advantages in the manufacture of devices with large amplitude (for example, cantilever beam type resonators). Finally, the process of the invention adopts a plane process, and has better micro-mechanical process compatibility compared with the cavity SOI manufactured by adopting a bulk process. The quality factor of the device is significantly improved due to the substantial reduction of stress and the reduction of mechanical losses.
Drawings
For purposes of illustration and not limitation, the present invention will now be described in accordance with its preferred embodiments, particularly with reference to the accompanying drawings, in which:
FIG. 1 is a schematic cross-sectional view of a prior art device for fabricating cantilever on SOI prior to a back etching operation;
FIG. 2 is a schematic cross-sectional view of a prior art device after a back-etching operation for fabricating cantilever arms on SOI;
FIG. 3 is a cross-sectional schematic view of a piezoelectric MEMS silicon resonator of an embodiment of the present invention;
FIGS. 4a to 4i are schematic views illustrating a process of fabricating a piezoelectric MEMS silicon resonator according to a first embodiment of the present invention;
FIGS. 5a to 5c are schematic cross-sectional views, schematic steps of forming a heavily doped sacrificial layer, and schematic surface planarization steps of a piezoelectric MEMS silicon resonator according to a second embodiment of the present invention;
FIGS. 6a and 6b are schematic cross-sectional views of a piezoelectric MEMS silicon resonator and a schematic step of forming a heavily doped sacrificial layer according to a third embodiment of the present invention;
FIGS. 7a and 7b are schematic cross-sectional views of a piezoelectric MEMS silicon resonator and a schematic step of forming a heavily doped sacrificial layer according to a fourth embodiment of the present invention;
FIG. 8 is a cross-sectional schematic view of a piezoelectric MEMS silicon resonator of a fifth embodiment of the present invention.
Detailed Description
In view of the problems in the prior art, the core of the piezoelectric MEMS silicon resonator and the manufacturing method thereof in the embodiment of the invention is to manufacture a cantilever beam of the resonator by adopting a method of monocrystalline silicon epitaxy and selective etching, and deposit a piezoelectric film on the monocrystalline silicon to form the resonator. The method of the embodiment of the invention is simple and easy to implement, and the manufactured device has the advantages of low cost, high quality factor, high stability and the like.
As shown in fig. 3, the piezoelectric MEMS silicon resonator of the embodiment of the present invention mainly includes: a silicon substrate 100; a lower cavity 210 on the silicon substrate 100, the lower cavity 210 being sacrificial by the sacrificial silicon layer 200; a remaining silicon layer 300 located over the lower cavity 210; a lower electrode 400, a piezoelectric layer 500, and an upper electrode 600 stacked in this order on the remaining silicon layer 300. Wherein the remaining silicon layer 300 may be single crystal silicon. Silicon substrate 100 and retained siliconOne of the two layers 300 is commonly N-type doped, and the other of the two layers is P-type doped with a first doping concentration; alternatively, one of the silicon substrate 100 and the remaining silicon layer 300 is doped with a common P-type dopant, and the other is doped with an N-type dopant of the first dopant concentration. Wherein the doping concentration of the common N-type doping and the common P-type doping is less than 1019cm-3. The first doping concentration may be 1019To 9X 1020cm-3. It should be noted that the lower electrode 400 is an optional structure. The silicon layer 300 has good conductivity while maintaining the material of the silicon layer as degenerate silicon, and may directly serve as an electrode, so that the lower electrode 400 may be omitted.
In this embodiment, the upper electrode 600, the piezoelectric layer 500, the lower electrode 400, and the remaining silicon layer 300 together form a cantilever. However, in addition to the cantilever beam type, the piezoelectric MEMS silicon resonator according to another embodiment of the present invention may have an extension vibration mode, a thickness longitudinal vibration mode, a lamb wave vibration mode, an in-plane bending vibration mode, a surface acoustic wave vibration mode, or the like.
In this embodiment, the bottom plane of the lower cavity 210 is lower than the top plane of the silicon substrate 100, and the top plane of the lower cavity 210 is higher than the top plane of the silicon substrate 100. In the piezoelectric MEMS silicon resonator according to another embodiment, the following may be applied: the bottom plane of the lower cavity is lower than the top plane of the silicon substrate, and the top plane of the lower cavity is equal to the top plane of the silicon substrate; or the bottom plane of the lower cavity is equal to the top plane of the silicon substrate, and the top plane of the lower cavity is higher than the top plane of the silicon substrate; or the bottom plane of the lower cavity is lower than the top plane of the silicon substrate, and the top plane of the lower cavity is lower than the top plane of the silicon substrate. Methods of forming piezoelectric MEMS silicon resonators with different modes of the lower cavity will be mentioned in detail later. It should be noted that the resonators based on SOI wafer processing mentioned in the background art do not satisfy the feature of "the top plane of the lower cavity and the top plane of the silicon substrate are not coplanar". Therefore, compared with the prior art, the piezoelectric MEMS silicon resonator provided by the embodiment of the invention has the advantages of flexible design, capability of meeting certain special application requirements and the like.
In this embodiment, the piezoelectric MEMS silicon resonator may further comprise a silicon cap 900, the silicon cap 900 comprising an insulating layer 930, an upper substrate 920 and a metal connection region 910. The insulating layer 930 is optional, and the metal connection region 910 may be a layer of metal material or a plurality of layers of metal materials. The silicon cap 900 is bonded to the remaining silicon layer 300 through the bonding layer 800 and the upper cavity 700 is constructed.
The material selection of the various parts is as follows:
the substrate 100, which is illustrated in embodiments 1 to 4 of the present invention, is an N-type single crystal silicon, and may be other materials, such as aluminum nitride, gallium arsenide, and sapphire.
A lower cavity 210.
The remaining silicon layer 300, in this example matched to the substrate 100, may be monocrystalline silicon P-type with a first doping concentration.
The specific material of the lower electrode 400 may be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium, or a composite or alloy thereof, or a non-metal conductive material, such as doped silicon, may be used. The lower electrode 400 is an optional structure, for example, the reserved silicon layer 300 can directly play the role of the lower electrode, so that the manufacture of the lower electrode is omitted, and the method is simple and easy to implement; on the other hand, the temperature stability of the resonator is improved after the lower electrode is omitted because the frequency temperature drift coefficient of the lower electrode is generally larger.
The piezoelectric layer 500 may be made of aluminum nitride, zinc oxide, PZT, or the like, and may include a rare earth element doped material in a certain atomic ratio.
The specific material of the upper electrode 600 may be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium, or a composite or alloy thereof, or a non-metal conductive material such as doped silicon may be used.
An upper cavity 700.
The bonding layer 800 is typically a gold-gold combination, but may be other metal combinations (e.g., aluminum-germanium, copper-copper, copper-gold-copper, gold-tin-copper, etc.), silicon dioxide, high polymer, and other common bonding materials.
A silicon cap 900, comprising:
the metal connection region 910 may be made of gold, copper, aluminum, or a combination of the above metals or an alloy thereof;
the upper substrate 920 is made of monocrystalline silicon, polycrystalline silicon, aluminum nitride, gallium arsenide, sapphire, metal, or the like;
the insulating layer 930 may be made of silicon oxide, aluminum nitride, aluminum oxide, silicon nitride, or the like.
The following describes the manufacturing process of the piezoelectric MEMS silicon resonator of five embodiments.
Example 1
A method of forming a piezoelectric MEMS silicon resonator according to a first embodiment of the present invention is shown in fig. 4a to 4 i. The method mainly comprises the following steps:
step 1: and (6) windowing. Referring to fig. 4a, a layer of silicon dioxide 110 is deposited on a single crystal silicon substrate 100, and the silicon dioxide 110 is patterned by using photoresist as a mask, so that a region where a cavity under a resonator is to be formed is exposed.
Step 2: and etching the groove. As shown in fig. 4b, the silicon dioxide 110 patterned in the above step is used as a mask to etch silicon, and dry etching or wet etching may be used. Here the depth of the etched recess is controllable and thus the height of the resulting lower cavity is controllable.
And step 3: and (5) extending the sacrificial layer. As shown in FIG. 4c, a second doping concentration P-type single crystal silicon (e.g. doped with boron and having a doping concentration of 10) is epitaxially grown on the recess obtained in step 218cm-3) By increasing hydrogen chloride gas and controlling the flow rate of hydrogen chloride gas during epitaxy, selective epitaxy can be realized only on monocrystalline silicon, and an epitaxial silicon layer is not grown on the surface of a silicon dioxide mask. When the epitaxial second doping concentration P-type silicon is used as a sacrificial layer, the thickness of the epitaxial second doping concentration P-type silicon can be controlled through epitaxial time, a large cavity can be formed, and the thickness range is 1-50 um.
And 4, step 4: epitaxially leaving the silicon layer 300 and depositing the bottom electrode 400. Referring to FIG. 4d, the oxide layer is removed from the structure obtained in step 3 by HF, and then P-type silicon with a first doping concentration is epitaxially grown on the surface (e.g., doped with boron and having a doping concentration of 10)20cm-3) Thus, the remaining silicon layer 300 is obtained, and then a layer of molybdenum is deposited as the lower electrode 400.
And 5: a piezoelectric layer 500 is deposited and patterned. As shown in fig. 4e, an aluminum nitride piezoelectric layer is deposited, and the aluminum nitride is patterned by dry etching, followed by dry or wet etching of the lower electrode to pattern it.
Step 6: the upper electrode 600 is deposited. As shown in fig. 4f, a layer of molybdenum is deposited, and then the molybdenum electrode is etched by using the patterned photoresist as a mask to be patterned, so as to obtain the upper electrode 600.
Note that in the above steps 4 to 6, the processing sequence of the three layers of the lower electrode 400, the piezoelectric layer 500, and the upper electrode 600 may not be limited to the above scheme, for example: it is also possible to pattern the lower electrode 400 first, then deposit the piezoelectric layer 500 and the upper electrode 600, and then pattern the upper electrode 600 and the piezoelectric layer 500 in sequence.
And 7: and (5) opening an etching window. As shown in fig. 4g, a layer of silicon oxide is deposited first, then wet etching is performed on the silicon oxide with the photoresist as a mask, then dry etching is performed on the first doping concentration P-type silicon layer with the silicon oxide as a hard mask until the second doping concentration P-type silicon layer is etched and exposed at the right end and the two sides of the beam, and the silicon oxide on the surface is removed with HF as an etching agent.
And 8: the beam is released. Referring to fig. 4h, the structure obtained in step 7 is placed in an etching solution, and a pulse signal is applied according to the above description to selectively etch away the heavily doped sacrificial layer 200 with the second doping concentration P-type.
And step 9: and (7) bonding and packaging. As shown in fig. 4i, a silicon cap 900 fabricated in advance is placed on the structure obtained in step 8 for bonding packaging. Au-Au bonding, Al-Ge bonding, Cu-Au-Cu bonding or other metal or polymer bonding.
Example 2
A piezoelectric MEMS silicon resonator according to a second embodiment of the invention is shown in figure 5 a. Embodiment 2 differs from embodiment 1 in that the resonator body is flat. In the manufacturing process of this embodiment, the difference from embodiment 1 is that, as shown in fig. 5b, the sacrificial layer is epitaxially grown until the sacrificial layer is slightly higher than the interface between silicon and silicon oxide, then the silicon oxide is washed away with HF, and the planarized surface is polished by chemical mechanical polishing, as shown in fig. 5 c. As a flat surface is obtained here, a flat resonator body is obtained in subsequent operation.
Example 3
A piezoelectric MEMS silicon resonator according to a third embodiment of the invention is shown in figure 6 a. The lower cavity in embodiment 3 is formed entirely by the tilting of the epitaxial beam without a groove on the silicon substrate 100. Compared with the example 1, the process steps are different in that: after windowing in step 1, step 2 of etching the groove is skipped, and deposition of the sacrificial layer is directly performed, as shown in fig. 6 b.
Example 4
A piezoelectric MEMS silicon resonator according to a fourth embodiment of the invention is shown in figure 7 a. In example 4, the beam is concave downward, and compared with example 1, the difference in the manufacturing process is that: the sacrificial layer is deposited by lowering the surface of the sacrificial layer below the interface of silicon and silicon oxide as shown in FIG. 7b, and the rest of the procedure is the same as in example 1.
Example 5
A piezoelectric MEMS silicon resonator according to a fourth embodiment of the invention is shown in figure 8. In contrast to the structure of embodiment 1, in this embodiment, the silicon substrate 100 'is a P-type single crystal silicon with the first doping concentration, while the silicon layer 300' is an N-type single crystal silicon. The process differs from example 1 in that: and (3) operating by taking the P-type silicon with the first doping concentration as a raw material, wherein the sacrificial layer is still the P-type silicon with the second doping concentration, and extending N-type monocrystalline silicon on the sacrificial layer. The N-type silicon is still connected with a positive voltage during selective etching.
According to the piezoelectric MEMS silicon resonator provided by the embodiment of the invention, the silicon layer with the first doping concentration can adjust the doping concentration as required so as to change the temperature coefficient TCF of the frequency. Because the frequency temperature coefficient of the beam is related to the frequency temperature coefficient and the thickness structure of each layer of material, the doping concentration of the silicon layer with the first doping concentration can be adjusted to enable the TCF to be a proper value and offset with the TCFs of other parts of the resonator, and further the total equivalent TCF of the resonator beam is enabled to be zero, the purpose of temperature compensation is achieved, and temperature drift is avoided.
The forming process of the piezoelectric MEMS silicon resonator according to the embodiment of the present invention may be: sequentially epitaxially growing second doping concentration P-type silicon and first doping concentration P-type silicon on the N-type silicon substrate, wherein the second doping concentration P-type silicon is a sacrificial layer; or sequentially epitaxially and sequentially doping the second dopant on the P-type silicon substrate with the first dopant concentrationThe P-type silicon with the second doping concentration is a sacrificial layer. And sequentially epitaxially growing second doping concentration N-type silicon and first doping concentration N-type silicon on the P-type silicon, or sequentially epitaxially growing second doping concentration N-type silicon and P-type silicon on the first doping concentration N-type silicon, wherein the second doping concentration N-type silicon is a sacrificial layer. Wherein the first doping concentration is greater than the second doping concentration. Optionally, the second doping concentration is 1013To 9X 1018cm-3The first doping concentration is 1019To 9X 1020cm-3. Wherein, the P-type doping dopant is boron element, or can be III-group elements such as aluminum, gallium, indium and the like; the N-type dopant is generally phosphorus or arsenic.
Taking "sequentially epitaxially growing P-type silicon with second doping concentration and P-type silicon with first doping concentration on an N-type silicon substrate, wherein the P-type silicon with second doping concentration is a sacrificial layer" as an example, the process flow adopted when the sacrificial layer is released is described as follows: and a positive pulse electric signal is applied to the N-type silicon substrate, and the negative electrode of the N-type silicon substrate is connected with the P-type silicon with the first doping concentration. When positive voltage is applied to the N-type silicon substrate, current flows from the N-type silicon substrate to the P-type silicon with the second doping concentration through etching liquid, the P-type silicon with the second doping concentration is etched, and a passivation film is formed on the surface of the N-type silicon substrate and the surface of the P-type silicon with the first doping concentration; when the voltage is zero, the etching liquid etches in the same direction, and the passivation film on the surface of the N-type silicon substrate and the P-type silicon with the first doping concentration and the P-type silicon with the second doping concentration are etched. The process is controlled to be repeated through the pulse signals, and selective etching of the P-type silicon with the second doping concentration is achieved. As a result, a cavity is formed below the P-type silicon with the first doping concentration, and a cantilever beam taking the P-type silicon with the first doping concentration as a substrate is formed.
An electronic device of an embodiment of the invention comprises any one of the piezoelectric MEMS silicon resonators disclosed in the invention.
According to the technical scheme of the embodiment of the invention, the silicon resonator is manufactured by adopting the method of silicon epitaxial growth and selective etching of silicon with different doping concentrations, so that the use of a cavity SOI and a common SOI is avoided, and the cost is reduced. Meanwhile, the bending phenomenon in the manufacturing process of the SOI with the cavity is avoided, so that the stress problem caused by the release of the cavity SOI is avoided. Second, in the present example, gold-gold bonding is used instead of SOI, and because gold is a soft material, the stress problem due to the silicon oxide-silicon hard bond is eliminated. In addition, a three-dimensional structure (such as a beam structure which is longitudinally raised or lowered) can be manufactured at the fixed end of the epitaxial beam, and the interference of external stress, vibration and thermal noise can be greatly eliminated, so that the device has higher stability and signal-to-noise ratio, and the three-dimensional structure can prevent the energy of beam vibration from dissipating outwards, thereby being beneficial to improving the quality factor. Third, the thickness of the grown silicon film in the silicon epitaxial process is controllable and wide (for example, more than 20 microns), so that the silicon epitaxial process has certain advantages in the manufacture of devices with large amplitude (for example, cantilever beam type resonators). Finally, the process of the invention adopts a plane process, and has better micro-mechanical process compatibility compared with the cavity SOI manufactured by adopting a bulk process. The quality factor of the device is significantly improved due to the substantial reduction of stress and the reduction of mechanical losses.
The above-described embodiments should not be construed as limiting the scope of the invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions can occur, depending on design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (16)
1. A piezoelectric MEMS silicon resonator, comprising:
a silicon substrate;
a lower cavity located above the silicon substrate, a top plane of the lower cavity being higher or lower than a top plane of the substrate;
a remaining silicon layer located over the lower cavity;
a piezoelectric layer and an upper electrode stacked in sequence over the remaining silicon layer.
2. The piezoelectric MEMS silicon resonator of claim 1, wherein the remaining silicon layer is single crystal silicon.
3. The piezoelectric MEMS silicon resonator of claim 2, wherein one of the silicon substrate and the remaining silicon layer is commonly N-doped and the other is P-doped at the first doping concentration; or, one of the silicon substrate and the reserved silicon layer is doped in a common P type, and the other one of the silicon substrate and the reserved silicon layer is doped in an N type with a first doping concentration.
4. Piezoelectric MEMS silicon resonator according to claim 3, wherein the first doping concentration is 1019To 9X 1020cm-3。
5. The piezoelectric MEMS silicon resonator of claim 1, further comprising: a lower electrode located between the remaining silicon layer and the piezoelectric layer.
6. The piezoelectric MEMS silicon resonator of any one of claims 1 to 5, wherein the piezoelectric MEMS silicon resonator is one of: cantilever beam, extensional vibration mode, thickness longitudinal vibration mode, lamb wave vibration mode, in-plane bending vibration mode, surface acoustic wave vibration mode.
7. A method of forming a piezoelectric MEMS silicon resonator, comprising:
providing a silicon substrate;
forming a sacrificial silicon layer over the silicon substrate;
forming a remaining silicon layer over the sacrificial silicon layer;
sequentially forming a piezoelectric layer and an upper electrode on the reserved silicon layer;
an etch window is opened, and then the sacrificial silicon layer is selectively removed to form a lower cavity, wherein,
under the condition that the sacrificial silicon layer is doped with P type with the second doping concentration, one of the silicon substrate and the reserved silicon layer is doped with common N type, and the other one of the silicon substrate and the reserved silicon layer is doped with P type with the first doping concentration, or,
and under the condition that the sacrificial silicon layer is doped with N type with the second doping concentration, one of the silicon substrate and the reserved silicon layer is doped with common P type, and the other one of the silicon substrate and the reserved silicon layer is doped with N type with the first doping concentration.
8. The method of forming of claim 7, wherein the first doping concentration is greater than the second doping concentration.
9. The method of claim 8, wherein the first doping concentration is 1019To 9X 1020cm-3The second doping concentration is 1013To 9X 1018cm-3。
10. The method of forming of claim 7, wherein the step of forming a sacrificial silicon layer over the silicon substrate comprises: the sacrificial silicon layer is epitaxially formed on the silicon substrate.
11. The method of forming of claim 7, wherein the step of forming a remaining silicon layer over the sacrificial silicon layer comprises: the remaining silicon layer is epitaxially formed over the sacrificial silicon layer.
12. The method of forming as claimed in claim 7, further comprising: a lower electrode is formed between the remaining silicon layer and the piezoelectric layer.
13. The forming method according to claim 7,
the bottom plane of the sacrificial silicon layer is lower than the top plane of the silicon substrate, and the top plane of the sacrificial silicon layer is higher than the top plane of the silicon substrate; alternatively, the first and second electrodes may be,
the bottom plane of the sacrificial silicon layer is lower than the top plane of the silicon substrate, and the top plane of the sacrificial silicon layer is equal to the top plane of the silicon substrate; alternatively, the first and second electrodes may be,
the bottom plane of the sacrificial silicon layer is equal to the top plane of the silicon substrate, and the top plane of the sacrificial silicon layer is higher than the top plane of the silicon substrate; alternatively, the first and second electrodes may be,
the bottom plane of the sacrificial silicon layer is lower than the top plane of the silicon substrate, and the top plane of the sacrificial silicon layer is lower than the top plane of the silicon substrate.
14. The forming method according to any one of claims 7 to 13, wherein the piezoelectric MEMS silicon resonator is a cantilever beam type, an extensional vibration mode, a thickness longitudinal vibration mode, a lamb wave vibration mode, an in-plane bending vibration mode, or a surface acoustic wave vibration mode.
15. A piezoelectric MEMS silicon resonator, produced by the formation method of any one of claims 7 to 14.
16. An electronic device comprising a piezoelectric MEMS silicon resonator as claimed in any one of claims 1 to 6 and claim 15.
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