CN113471275B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN113471275B CN113471275B CN202110696336.6A CN202110696336A CN113471275B CN 113471275 B CN113471275 B CN 113471275B CN 202110696336 A CN202110696336 A CN 202110696336A CN 113471275 B CN113471275 B CN 113471275B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 71
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 68
- 239000010703 silicon Substances 0.000 claims abstract description 68
- 239000000758 substrate Substances 0.000 claims abstract description 65
- 239000000463 material Substances 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 239000000969 carrier Substances 0.000 description 26
- 230000005684 electric field Effects 0.000 description 21
- 230000000694 effects Effects 0.000 description 12
- 230000002829 reductive effect Effects 0.000 description 12
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- 230000004048 modification Effects 0.000 description 8
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- 239000012535 impurity Substances 0.000 description 6
- 230000008569 process Effects 0.000 description 5
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- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
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- 230000005669 field effect Effects 0.000 description 1
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- 229910052751 metal Inorganic materials 0.000 description 1
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- 235000012239 silicon dioxide Nutrition 0.000 description 1
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- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
Abstract
The invention provides a semiconductor device and a method for manufacturing the same, the semiconductor device includes: the semiconductor device comprises a substrate, an insulating layer arranged on the substrate, a grid arranged on the insulating layer, wherein the substrate is provided with a source region and a drain region which are respectively positioned on one side of the grid, a source electrode and a drain electrode which are respectively arranged in the source region and the drain region, and a silicon doping structure arranged in the source region and the drain region, wherein the silicon doping structure is positioned between the grid and the source electrode or between the grid and the drain electrode.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
With the increasing Integration of VLSI (Very Large Scale Integration), the feature size of devices in integrated circuits is also decreasing, such as the channel length, the channel width, the gate Oxide thickness, and the source-drain junction depth of a MOS Transistor (Metal-Oxide-Semiconductor Field Effect Transistor).
The lateral electric field of the conduction channel of the MOS tube is increased because the power supply voltage supplied to the integrated circuit is basically kept unchanged while the channel length and the gate oxide thickness of the MOS tube are reduced. The increase of the transverse electric field causes carriers in the MOS transistor to collide and ionize in the moving process to generate additional electron-hole pairs (i.e., Hot carriers), and due to the high moving speed of the Hot carriers, part of the Hot carriers can tunnel to the gate oxide layer of the MOS transistor, which is called Hot Carrier Injection (HCI) effect.
The hot carrier injection effect can increase the threshold voltage of the MOS transistor, reduce saturation current and carrier mobility, and the like, and finally, the reliability of the MOS transistor is reduced.
Disclosure of Invention
The invention provides a semiconductor device and a preparation method thereof, which effectively solve the problem of reliability reduction of the semiconductor device due to the hot carrier injection effect in the semiconductor device.
In order to solve the above problem, the present invention provides a semiconductor device including:
a substrate;
an insulating layer disposed on the substrate;
the grid is arranged on the insulating layer, and the substrate is provided with a source region and a drain region which are respectively positioned on one side of the grid;
the source electrode and the drain electrode are respectively arranged in the source region and the drain region;
and the silicon doping structure is arranged in the source region and the drain region and is positioned between the grid electrode and the source electrode or between the grid electrode and the drain electrode.
Further preferably, low-doped structures are further disposed in the source region and the drain region, the source and the drain have a first doping concentration, the low-doped structures have a second doping concentration, the first doping concentration is greater than the second doping concentration, and the doping types of the low-doped structures and the source and the drain are the same.
Further preferably, the silicon doped structure is located in the low doped structure.
Further preferably, a graded PN junction is formed between the low-doped structure and the substrate.
Further preferably, the silicon doped structure and the source are separated by the low doped structure or the silicon doped structure and the drain are separated by the low doped structure.
Preferably, the semiconductor device further includes a first sidewall and a second sidewall, the first sidewall is disposed around the outer surface of the gate, and the second sidewall is disposed around the outer surface of the first sidewall.
Further preferably, the first side wall and the second side wall each include a first lamination and a second lamination, the second lamination is disposed on an outer surface of the first lamination, and a material of the first lamination includes an oxide and a material of the second lamination includes a nitride.
Further preferably, the projection plane of the gate electrode and the silicon doped structure in the vertical direction of the substrate has an overlapped part.
It is further preferred that the source and the drain have a first depth in the longitudinal direction and the silicon doped structure has a second depth in the longitudinal direction, the first depth being greater than the second depth.
It is further preferred that the gate has a first length in a lateral direction parallel to the substrate, and the silicon doped structure has a second length in the lateral direction, the second length being not less than the first length.
In another aspect, the present invention further provides a method for manufacturing a semiconductor device, including:
providing a substrate;
forming an insulating layer on the substrate;
forming a gate on the insulating layer, wherein the substrate is provided with a source region and a drain region which are respectively positioned at one side of the gate;
forming a silicon doping structure in the source region and the drain region;
and forming a source electrode and a drain electrode in the source region and the drain region respectively.
Further preferably, after the step of forming the gate electrode on the insulating layer, the method further includes:
forming a first side wall on the outer surface of the grid, wherein the first side wall surrounds the grid;
forming a low-doped structure in the source region and the drain region;
the silicon doped structure is positioned in the low doped structure, the source electrode and the drain electrode have first doping concentration, the low doped structure has second doping concentration, the first doping concentration is larger than the second doping concentration, and the doping type of the low doped structure is the same as that of the source electrode and the drain electrode.
Further preferably, after the step of forming the low doped structure in the source region and the drain region, the method further includes:
and annealing the low-doped structure to form a graded PN junction between the low-doped structure and the substrate.
Further preferably, when the low-doped structure is formed in the source region and the drain region, a multiple ion implantation method is adopted, so that a graded PN junction is formed between the low-doped structure and the substrate.
Further preferably, after the step of forming the silicon doped structure in the source region and the drain region, the method further includes:
and forming a second side wall on the outer surface of the first side wall, wherein the second side wall surrounds the first side wall.
Further preferably, after the step of forming the source electrode and the drain electrode in the source region and the drain region, respectively, the method further includes:
and carrying out rapid annealing on the source electrode and the drain electrode.
The beneficial effects of the invention are as follows: the present invention provides a semiconductor device including: the semiconductor device comprises a substrate, an insulating layer arranged on the substrate, a grid arranged on the insulating layer, and the substrate is provided with a source region and a drain region which are respectively positioned on one side of the grid, a source electrode and a drain electrode which are respectively arranged in the source region and the drain region, and a silicon doping structure arranged in the source region and the drain region, wherein the silicon doping structure is positioned between the grid and the source electrode or between the grid and the drain electrode.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the description of the embodiments according to the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without inventive effort.
Fig. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention.
Fig. 2 is a schematic flow chart of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.
Fig. 3 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present invention.
Fig. 4 is a flow chart illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention.
Fig. 5a to 5h are schematic process flow diagrams of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of protection of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood according to specific situations by those of ordinary skill in the art.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature "on," "above" and "over" the second feature may include the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present invention. Moreover, the present invention may repeat reference numerals and/or reference letters in the various examples, which have been repeated for purposes of simplicity and clarity and do not in themselves dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.
The invention aims at the problem that the reliability of the existing semiconductor device is reduced due to the hot carrier injection effect in the existing semiconductor device, and the embodiment of the invention is used for solving the problem.
Referring to fig. 1, fig. 1 is a schematic cross-sectional view of a semiconductor device 100 according to a first embodiment of the present invention, in which components and relative positions of the components can be seen visually.
As shown in fig. 1, the semiconductor device 100 includes: substrate 110, insulating layer 120, gate 130, source 140 s A drain electrode 140 d The silicon doped structure 150 and the first sidewall 160 will be described in detail below with respect to the components of the semiconductor device 100.
The substrate 110 has source regions a respectively located at one side of the gate 130 s And a drain region A d In the source region A s Therein is provided with a source electrode 140 s In the drain region A d Therein is provided with a drain electrode 140 d . Wherein, the substrate 110 and the source 140 s And a drain electrode 140 d E.g., if the substrate 110 is doped with P-type impurities, the source 140 s And a drain electrode 140 d Doping N-type impurities, wherein the semiconductor device is an N-channel MOS transistor, and doping N-type impurities into the substrate 110 to form the source 140 s And a drain electrode 140 d Doping P-type impurity, and the semiconductor device is P-channel MOS tube.
An insulating layer 120 is disposed over the substrate 110, an exemplary material of the insulating layer 120 being silicon dioxide (Si 0) 2 ) Grid (C)The electrode 130 is disposed on the insulating layer 120, and an exemplary material of the gate electrode 130 is metal aluminum (Al).
The silicon doped structure 150 is disposed in the source region A s And a drain region A d The silicon doped structure 150 is located on the gate 130 and the source 140 s And the silicon doped structure 150 has a gate 130 and a drain 140 d The silicon doped structure 150 is in contact with one surface of the insulating layer 120, wherein the silicon doped structure 150 is in contact with the source 140 s And a drain electrode 140 d Are different.
The first sidewall 160 surrounds the outer surface of the gate 130 and includes a first stack 161 and a second stack 162, wherein the first stack 161 includes an oxide and the second stack 162 includes a nitride.
Next, the substrate 110 is doped with P-type impurities and the source 140 s And a drain electrode 140 d The operation principle of the semiconductor device 100 will be explained by doping N-type impurities as an example: when the drain 140 is in d And a source electrode 140 s The voltage between is zero, and the gate 130 and the source 140 s The voltage therebetween is greater than zero, the current at the gate 130 is zero due to the presence of the insulating layer 120. At this time, the gate 130 collects positive charges, repelling holes on the side of the substrate 110 near the insulating layer 120, and attracting electrons in the substrate 110 to the interface of the substrate 110 and the insulating layer 120. As the voltage of the gate 130 increases, more and more electrons in the substrate 110 are attracted to the interface, thereby forming an N-type conduction channel at the interface, and the electric field direction of the lateral electric field in the N-type conduction channel is controlled by the drain 140 d To the source 140 s 。
It should be noted that when the feature size of the semiconductor device 100 is reduced and the power supply voltage supplied to the semiconductor device 100 is unchanged, the above-mentioned lateral electric field increases. Carriers in the conductive channel under the gate 130 move in a strong electric field and undergo impact ionization to generate new electron-hole pairs (i.e., hot carriers), and the hot carriers may tunnel to the insulating layer 120 due to their high moving speed, thereby degrading the reliability of the semiconductor device 100.
It is easily understood that the silicon doping structure 150 disposed in the semiconductor device 100 can block the carriers in the conductive channel, so that the carriers do not tunnel to the insulating layer 120 under the gate 130, and at the same time, the silicon doping structure 150 and the source 140 are formed therein s And a drain electrode 140 d The doping types of the semiconductor device 100 are different, so that the electric field intensity of a transverse electric field in a conductive channel below the gate 130 is reduced, the probability of collision ionization of carriers in the conductive channel is reduced, the hot carrier effect in the semiconductor device 100 is improved, and the reliability of the semiconductor device 100 is improved.
Further, the gate 130 has a first length in a lateral direction X parallel to the substrate 110, and the silicon doped structure 150 has a second length in the lateral direction X. In one possible variant of the invention, the second length of the silicon doped structure is not less than the first length of the gate. Compared with other semiconductor devices of which the second length of the silicon doped structure is smaller than the first length of the gate, the tunneling path of the carriers in the conduction channel of the semiconductor device provided by the modification in the transverse direction X is blocked, so that the blocking effect of the silicon doped structure in the modification on the carriers in the conduction channel is better.
Further, in another possible modification of the present invention, the projection plane of the gate and the silicon doped structure in the longitudinal direction Y perpendicular to the substrate has an overlapping portion. Compared with other semiconductor devices in which the projection plane of the gate and the silicon doped structure on the longitudinal direction Y perpendicular to the substrate does not have an overlapping portion, a partial region of the insulating layer below the gate of the semiconductor device provided by the modification overlaps with the silicon doped structure, so that tunneling of carriers in the conductive channel to the tunneling plane of the insulating layer is reduced, and therefore the blocking effect of the silicon doped structure in the modification on carriers in the conductive channel is better.
Further, in the present embodiment, the source electrode 140 s And a drain electrode 140 d The silicon doped structure 150 has a first depth in the longitudinal direction Y and a second depth in the longitudinal direction Y, wherein the first depth is greater than the second depth.
Referring to fig. 2, fig. 2 is a flow chart illustrating a method for manufacturing a semiconductor device 100 according to a first embodiment of the invention.
As shown in fig. 2, the preparation method specifically includes:
substrate providing step S101: providing a substrate;
insulating layer forming step S102: forming an insulating layer on a substrate;
gate forming step S103: forming a gate on the insulating layer, wherein the substrate has a source region and a drain region respectively located at one side of the gate;
silicon doped structure forming step S104: forming a silicon doping structure in the source region and the drain region;
source and drain forming step S105: a source electrode and a drain electrode are formed in the source region and the drain region, respectively.
Further, to activate the source 140 s And a drain electrode 140 d The carriers in (2) further include, after the source and drain forming step:
and rapidly annealing the source electrode and the drain electrode.
A first embodiment of the present invention provides a semiconductor device 100, distinguished from the related art, including: a substrate 110, an insulating layer 120 disposed on the substrate 110, a gate 130 disposed on the insulating layer 120, and the substrate 110 having source regions A respectively located at one side of the gate 130 s And a drain region A d Respectively arranged in the source region A s And a drain region A d Source electrode 140 in s And a drain electrode 140 d And is disposed in the source region A s And a drain region A d Wherein the silicon doped structure 150 is located on the gate 130 and the source 140 s With the silicon doped structure 150 between the gate 130 and the drain 140 d Meanwhile, since the doped silicon structure 150 is in contact with one surface of the insulating layer 120, the doped silicon structure 150 can block the movement of carriers in the conductive channel under the gate 130, so that the carriers cannot tunnel to the insulating layer 120 under the gate 130, and meanwhile, since the doped silicon structure 150 and the source 140 are in contact with each other s And a drain electrode 140 d Are different in doping type and canSo as to reduce the electric field strength of the transverse electric field in the conductive channel, and further reduce the probability of collision ionization of carriers in the conductive channel, thereby improving the reliability of the semiconductor device 100.
Referring to fig. 3, fig. 3 is a schematic cross-sectional view of a semiconductor device 200 according to a second embodiment of the present invention, in which the components and the relative positions of the components can be clearly seen.
As shown in fig. 3, the second embodiment has substantially the same structure as the first embodiment, wherein the substrate 210 (including the source region a) in the second embodiment s And a drain region A d ) As with the substrate 110 (including the source region a) in the first embodiment s And a drain region A d ) The function and the setting position of the device are the same; the insulating layer 220 in the second embodiment has the same function and arrangement position as the insulating layer 120 in the first embodiment; the gate 230 in the second embodiment has the same function and arrangement position as the gate 130 in the first embodiment; source 240 in the second embodiment s And a drain electrode 240 d And the source 140 in the first embodiment s And a drain electrode 140 d The functions of the two are the same; the silicon doping structure 250 in the second embodiment functions the same as the silicon doping structure 150 in the first embodiment; the first sidewall 260 (including the first stack 261 and the second stack 262) in the second embodiment has the same function and arrangement position as the first sidewall 160 (including the first stack 161 and the second stack 162) in the first embodiment.
The difference is that in the present embodiment, the source region A s And a drain region A d Therein is also disposed a low doped structure 270, a source 240 s A drain electrode 240 d And the silicon doped structure 250 is located in the low doped structure 270, the silicon doped structure 250 and the source 240 s A low doped structure 270 is formed between the silicon doped structure 250 and the drain 240 d With a low-doped structure 270 therebetween. In the embodiment, a second sidewall 280 is disposed around the outer surface of the first sidewall 260, and the second sidewall 280 includes a first lamination 281 and a second lamination 282. Next, the present embodiment providesThe semiconductor device 200 of (1) will be described in detail with respect to the components different from those of the first embodiment.
It is readily understood that in other embodiments consistent with the present invention, the lowly doped structure is located between the gate and the source, and between the gate and the drain, and the silicon doped structure is located in the lowly doped structure.
It should be noted that when the semiconductor device 200 is in the off state, namely, the gate 230 and the source 240 s If the voltage between the drain 240 is zero d Switch on the supply voltage due to the gate 230 and drain 240 d There is a strong electric field in the overlap region between, and the drain electrode 240 d Under the action of the strong electric field, the carriers from the drain 240 d Tunneling to the gate 230 and causing the drain 240 d There is a Leakage current to the Gate 230, which is called a GIDL (Gate Induced Drain Leakage) effect.
The low doping structure 270 provided in this embodiment can reduce the influence of the GIDL effect on the reliability of the semiconductor device 200. Note that, in this embodiment, the source 240 s And a drain electrode 240 d Has a first doping concentration, the low-doped structure 270 has a second doping concentration, wherein the first doping concentration is greater than the second doping concentration, and the low-doped structure 270 and the source 240 s And a drain electrode 240 d Are of the same doping type. The source electrode 240 is formed more than the source electrode due to the ion implantation energy used in forming the low-doped structure 270 by performing the ion implantation s And a drain electrode 240 d The ion implantation energy used is high, so the low doped structure 270 is longer in the longitudinal direction Y than the source 240 s And a drain electrode 240 d Deeper and the lowly doped structure 270 is deeper in a lateral direction Z parallel to the substrate 210 than the source 240 s And a drain electrode 240 d Is wider. Furthermore, the concentration of the dopant used in forming the low-doped structure 270 by ion implantation is higher than that of the dopant used in forming the source electrode 240 s And a drain electrode 240 d The low dopant concentration is used, so the introduction of the low-doped structure 270 can reduce the electric field strength in the conductive channel under the gate 230, thereby reducing the drain 240 d The probability of carrier tunneling to the gate 230 is improvedThe GIDL effect in the semiconductor device 200, and at the same time, the probability of collision ionization of carriers in the conductive channel is also reduced, the hot carrier effect in the semiconductor device 200 is improved, and the reliability of the semiconductor device 200 is further improved.
Further, in the present embodiment, since the silicon doping structure 250 is located in the low doping structure 270 and the doping types of the silicon doping structure 250 and the low doping structure 270 are different, the depletion region between the low doping structure 270 and the substrate 210 is expanded, so that the electric field strength of the lateral electric field in the conduction channel is reduced, the probability of collision and ionization of carriers in the conduction channel is reduced, and the hot carrier effect in the semiconductor device 200 is further improved.
Further, in another possible modification of the present invention, a graded PN junction is formed between the low-doped structure and the substrate, and the graded PN junction can make the electric field intensity of the lateral electric field in the conductive channel change slowly, so as to reduce the probability of collision and ionization of carriers in the conductive channel, and further improve the hot carrier effect in the semiconductor device provided by the modification.
In the present embodiment, since the ion implantation energy used in forming the low-doped structure 270 is high, the first sidewall 260 is damaged when the low-doped structure 270 is formed, which affects the reliability of the protection of the gate 230 by the first sidewall 260. Further, in the present embodiment, a second sidewall 280 is disposed around the outer surface of the first sidewall 260 to make up for the lack of reliability of the first sidewall 260 in protecting the gate 230, and the second sidewall 280 can enlarge the source 240 s And a gate 230, and a drain 240 d The distance from the gate 230 is such that the conductive channel under the gate 230 is widened, thereby reducing the electric field strength of the lateral electric field in the conductive channel, reducing the probability of impact ionization of carriers in the conductive channel, and further improving the hot carrier effect in the semiconductor device 200. Specifically, the material of the first stack 281 in the second sidewall 280 includes oxide, and the material of the second stack 282 in the second sidewall 280 includes nitrogenNitrides, among others, have better protective barrier capabilities than oxides.
Referring to fig. 4 and fig. 5a to 5h, fig. 4 is a schematic flow chart of a manufacturing method of a semiconductor device 200 according to a second embodiment of the invention, and fig. 5a to 5h are schematic process flow charts of the manufacturing method of the semiconductor device 200 according to the second embodiment of the invention.
As shown in fig. 4, the preparation method specifically includes:
substrate providing step S201: providing a substrate;
insulating layer forming step S202: forming an insulating layer over a substrate;
gate forming step S203: forming a gate on the insulating layer, wherein the substrate has a source region and a drain region respectively located at one side of the gate;
first sidewall forming step S204: forming a first side wall on the outer surface of the grid, wherein the first side wall surrounds the grid;
low-doped structure forming step S205: forming a low-doped structure in the source region and the drain region;
first annealing step S206: annealing the low-doped structure to form a graded PN junction between the low-doped structure and the substrate;
silicon doped structure forming step S207: forming a silicon doping structure in the source region and the drain region;
second sidewall forming step S208: forming a second side wall on the outer surface of the first side wall, wherein the second side wall surrounds the first side wall;
source and drain forming step S209: forming a source electrode and a drain electrode in the source region and the drain region respectively;
second annealing step S210: and carrying out rapid annealing on the source electrode and the drain electrode.
The substrate providing step S201, the insulating layer forming step S202, the gate forming step S203, the first sidewall forming step S204 and the low-doped structure forming step S205 correspond to the process steps in fig. 5a to 5e in sequence, and the silicon doped structure forming step S207, the second sidewall forming step S208 and the second sidewall forming step S208 correspond to the process steps in fig. 5f to 5h in sequence.
Further, the low-doped structure forming step S205 may further adopt a multi-time ion implantation method, so that a graded PN junction may be formed between the low-doped structure 270 and the substrate 210.
A second embodiment of the present invention provides a semiconductor device 200, distinguished from the prior art, including: a substrate 210, an insulating layer 220 disposed on the substrate 210, a gate 230 disposed on the insulating layer 220, and the substrate 210 having source regions a respectively located at one sides of the gate 230 s And a drain region A d Is arranged in the source region A s And a drain region A d Middle low doped structures 270 respectively disposed on the source electrodes 240 of the different low doped structures 270 s And a drain electrode 240 d A silicon doped structure 150 disposed in the low doped structure 270, wherein the silicon doped structure 250 is located on the gate 230 and the source 240 s With the silicon doped structure 250 between the gate 230 and the drain 240 d Meanwhile, since the silicon doped structure 250 is in contact with one surface of the insulating layer 220, the silicon doped structure 250 can block the movement of carriers in the conductive channel under the gate 230, so that the carriers cannot tunnel to the insulating layer 220 under the gate 230, and meanwhile, since the silicon doped structure 250 and the source 240 are in contact with each other s A drain electrode 240 d And the low-doped structure 270 are different in doping type, the electric field strength of the lateral electric field in the conductive channel can be reduced, and the probability of collision ionization of carriers in the conductive channel is further reduced, so that the reliability of the semiconductor device 200 is improved.
In addition to the above embodiments, the present invention may have other embodiments. All technical solutions formed by using equivalents or equivalent substitutions fall within the protection scope of the claims of the present invention.
In view of the foregoing, it is intended that the present invention cover the preferred embodiment of the invention, but not limited to the above-described preferred embodiment, and that various changes and modifications can be made by one skilled in the art without departing from the spirit and scope of the invention.
Claims (14)
1. A semiconductor device, characterized in that the semiconductor device comprises:
a substrate;
an insulating layer disposed on the substrate;
the grid is arranged on the insulating layer, and the substrate is provided with a source region and a drain region which are respectively positioned on one side of the grid;
the source electrode and the drain electrode are respectively arranged in the source region and the drain region;
the low-doped structure is arranged in the source region and the drain region;
a silicon doped structure located in the low doped structure, the silicon doped structure and the low doped structure having different doping types, and the silicon doped structure being located between the gate and the source and between the gate and the drain;
wherein the projection surfaces of the grid electrode and the silicon doped structure and the low doped structure in the longitudinal direction perpendicular to the substrate are provided with coincident parts, the silicon doped structure and the source electrode are provided with a space, and the silicon doped structure and the drain electrode are provided with a space.
2. The semiconductor device of claim 1, wherein the source and the drain have a first doping concentration, the lowly doped structure has a second doping concentration, the first doping concentration is greater than the second doping concentration, and the lowly doped structure is of the same doping type as the source and the drain.
3. The semiconductor device of claim 2, wherein a graded PN junction is formed between the lowly doped structure and the substrate.
4. The semiconductor device of claim 2, wherein the silicon doped structure is separated from the source by the lowly doped structure and the silicon doped structure is separated from the drain by the lowly doped structure.
5. The semiconductor device according to claim 1, further comprising a first sidewall surrounding the outer surface of the gate, and a second sidewall surrounding the outer surface of the first sidewall.
6. The semiconductor device according to claim 5, wherein the first side wall and the second side wall each comprise a first stack and a second stack, wherein the second stack is provided on an outer surface of the first stack, and wherein a material of the first stack comprises an oxide and a material of the second stack comprises a nitride.
7. The semiconductor device of claim 1, wherein the source and the drain have a first depth in the longitudinal direction, and wherein the silicon doped structure has a second depth in the longitudinal direction, and wherein the first depth is greater than the second depth.
8. The semiconductor device according to any one of claims 1 to 7, wherein the gate has a first length in a lateral direction parallel to the substrate, and the silicon doped structure has a second length in the lateral direction, the second length being not less than the first length.
9. A method of manufacturing a semiconductor device, the method comprising:
providing a substrate;
forming an insulating layer on the substrate;
forming a gate on the insulating layer, wherein the substrate is provided with a source region and a drain region which are respectively positioned at one side of the gate;
forming a low-doped structure in the source region and the drain region;
forming a silicon doped structure in the low doped structure, wherein the doping type of the silicon doped structure is different from that of the low doped structure, and the projection plane of the grid electrode, the projection plane of the silicon doped structure and the projection plane of the low doped structure in the longitudinal direction perpendicular to the substrate have a superposition part;
and respectively forming a source electrode and a drain electrode in the source region and the drain region, wherein a space is formed between the silicon doping structure and the source electrode, and a space is formed between the silicon doping structure and the drain electrode.
10. The method of claim 9, further comprising, after the step of forming a gate electrode on the insulating layer:
forming a first side wall on the outer surface of the grid, wherein the first side wall surrounds the grid;
wherein the source and the drain have a first doping concentration, the low-doped structure has a second doping concentration, the first doping concentration is greater than the second doping concentration, and the low-doped structure and the source and the drain have the same doping type.
11. The method of claim 9, further comprising, after the step of forming a low-doped structure in the source region and the drain region:
and annealing the low-doped structure to form a graded PN junction between the low-doped structure and the substrate.
12. The method according to claim 9, wherein a plurality of times of ion implantation is performed to form a graded PN junction between the lowly doped structure and the substrate when the lowly doped structure is formed in the source region and the drain region.
13. The method of claim 10, further comprising, after the step of forming a silicon doped structure in the lowly doped structure:
and forming a second side wall on the outer surface of the first side wall, wherein the second side wall surrounds the first side wall.
14. The method of claim 9, further comprising, after the step of forming a source and a drain in the source region and the drain region, respectively:
and carrying out rapid annealing on the source electrode and the drain electrode.
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| CN112289927A (en) * | 2020-09-16 | 2021-01-29 | 长江存储科技有限责任公司 | Switching device, method of manufacturing the same, and phase change random access memory |
| CN112420843A (en) * | 2020-11-19 | 2021-02-26 | 长江存储科技有限责任公司 | Semiconductor device and method for manufacturing the same |
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| CN102386186A (en) * | 2011-11-14 | 2012-03-21 | 北京大学 | CMOS (complementary metal oxide semiconductor) device capable of reducing charge collection generated by radiation and preparation method thereof |
| CN112289927A (en) * | 2020-09-16 | 2021-01-29 | 长江存储科技有限责任公司 | Switching device, method of manufacturing the same, and phase change random access memory |
| CN112420843A (en) * | 2020-11-19 | 2021-02-26 | 长江存储科技有限责任公司 | Semiconductor device and method for manufacturing the same |
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