CN113468100A

CN113468100A - Daughter card and electronic equipment supporting FPGA prototype verification

Info

Publication number: CN113468100A
Application number: CN202110731458.4A
Authority: CN
Inventors: 于长亮
Original assignee: Spreadtrum Communications Shanghai Co Ltd
Current assignee: Spreadtrum Communications Shanghai Co Ltd
Priority date: 2021-06-30
Filing date: 2021-06-30
Publication date: 2021-10-01
Anticipated expiration: 2041-06-30
Also published as: CN113468100B

Abstract

The application relates to the technical field of communication, in particular to a daughter card and electronic equipment supporting FPGA prototype verification, which can improve the utilization rate of an FPGA IO interface in an FPGA prototype verification platform. The circuit module is used for connecting a pin corresponding to an unoccupied FPGA IO interface on one side of the bottom surface of the first sub card to one side of the top surface of the first sub card, so that when any second sub card is connected with one side of the top surface of the first sub card through the second connector, at least one of the unoccupied FPGA IO interfaces is occupied.

Description

Daughter card and electronic equipment supporting FPGA prototype verification

Technical Field

The application relates to the technical field of application-specific integrated circuits, in particular to a daughter card and electronic equipment supporting FPGA prototype verification.

Background

At present, a general Input/Output (IO) interface provided by a Field-Programmable Gate Array (FPGA) prototype verification platform may be plugged with various functional daughter cards for verification. Under most circumstances, the IO interface quantity that general FPGA IO interface connector provided to the function daughter card of difference is fixed, and the IO interface quantity that the daughter card of different function types need occupy has the difference, occupies the daughter card that IO interface quantity is less when needs, when pegging graft on general FPGA IO interface connector, the IO interface that does not used on the general FPGA IO interface connector just is wasted. How to improve the utilization rate of the IO interface of the general FPGA is a problem to be solved urgently.

Disclosure of Invention

The embodiment of the application provides a daughter card and electronic equipment supporting FPGA prototype verification, and the problem of low utilization rate of a general FPGA IO interface can be solved.

In a first aspect, an embodiment of the present application provides a daughter card supporting FPGA prototype verification, which is adapted to an FPGA carrier card supporting FPGA prototype verification, where the daughter card includes a first daughter card, and one side of a bottom surface of the first daughter card is connected to the FPGA carrier card through a first connector to occupy an FPGA IO interface provided by the FPGA carrier card; one side of the top surface of the first daughter card is used for stacking at least one daughter card; at least a circuit module is arranged on the first sub card and used for connecting the FPGA IO interfaces on one side of the bottom surface of the first sub card, which are not occupied by the first sub card, to one side of the top surface of the first sub card, so that when one side of the bottom surface of the second sub card is connected with one side of the top surface of the first sub card through a second connector, the second sub card occupies at least one of the unoccupied FPGA IO interfaces.

In a possible implementation manner, a plurality of first pins for butting an FPGA IO interface are distributed on one side of the bottom surface of the circuit module; the serial numbers of the first pins are consistent with the serial numbers of the pins of the FPGA IO interface provided by the FPGA card; and a plurality of second pins respectively corresponding to the first pins are distributed on one side of the top surface of the circuit module, the serial numbers of the second pins are sequentially numbered from the lowest serial number value, and the lowest serial number value comprises 0 or 1.

In a second aspect, an embodiment of the present application provides an electronic device supporting FPGA prototype verification, including an FPGA card, at least one connector, and at least two daughter cards; wherein the content of the first and second substances,

one side of the bottom surface of the first sub card is connected with the FPGA carrier card through a first connector so as to occupy an FPGA IO interface provided by the FPGA carrier card; one side of the top surface of the first daughter card is used for stacking at least one daughter card; at least a circuit module is arranged on the first sub card and used for connecting the FPGA IO interfaces on one side of the bottom surface of the first sub card, which are not occupied by the first sub card, to one side of the top surface of the first sub card, so that when one side of the bottom surface of the second sub card is connected with one side of the top surface of the first sub card through a second connector, the second sub card occupies at least one of the unoccupied FPGA IO interfaces.

In a possible implementation manner, any one of the daughter cards stacked on one side of the top surface of the first daughter card is uniformly provided with a corresponding circuit module, so as to connect the unoccupied FPGA IO interface on one side of the bottom surface of the corresponding daughter card to one side of the top surface of the corresponding daughter card.

In a possible implementation manner, a plurality of first pins for butting the unoccupied FPGA IO interface are distributed on one side of the bottom surface of the circuit module; the serial numbers of the first pins are consistent with the serial numbers of the pins of the FPGA IO interface provided by the FPGA card; a plurality of second pins corresponding to the first pins are distributed on one side of the top surface of the circuit module and used for butting the second connector; the numbers of the plurality of second pins are sequentially numbered from a lowest number value, the lowest pin number value including 0 or 1.

In a possible implementation mode, adjacent pins around the FPGA IO interface on the FPGA card are connected with GND.

In a possible implementation mode, adjacent pins around the first pin or the second pin are connected with GND.

In one possible embodiment, the product specification and the material of each connector in the same electronic device are the same.

In a third aspect, an electronic device supporting FPGA prototype verification includes an FPGA circuit board, and a daughter card according to any one of the first aspect or an electronic device according to any one of the second aspect.

The daughter card and the electronic equipment supporting the FPGA prototype verification in the embodiment of the application are additionally provided with the circuit module, pins on the connector located on the bottom surface of the daughter card are communicated to one side of the top surface of the daughter card through the circuit module, the transmission of an unoccupied IO interface of the bottom layer to the upper layer is realized, so that the upper layer daughter card continues to occupy, and the utilization rate of the general FPGA IO interface is improved.

Drawings

FIG. 1 is a schematic diagram of a FPGA card carrier with different function cards plugged therein according to the related art;

FIG. 2 is a schematic diagram of a first daughter card connected to an FPGA carrier card according to an embodiment of the present disclosure;

FIG. 3 is a diagram of a set of connectors on an FPGA carrier card stacking multiple daughter cards according to an embodiment of the present application;

fig. 4 is a schematic diagram illustrating that multiple groups of connectors on the FPGA card carrier stack multiple daughter cards respectively in the embodiment of the present application.

Detailed Description

The terminology used in the description of the embodiments section of the present application is for the purpose of describing particular embodiments of the present application only and is not intended to be limiting of the present application.

The daughter card and the electronic device supporting FPGA prototype verification provided by the embodiment of the application can be applied to an FPGA prototype verification scene. The FPGA prototype verification is an important link in the development process of products such as chips and the like and is used for verifying whether all logic functions are normal or not before tape-out. Chip software is developed on an FPGA prototype verification platform, so that the software development period can be shortened. In the design and verification of integrated circuits of various chips, an FPGA prototype verification platform provides a general FPGA IO interface for plugging various functional daughter cards to verify Register Transfer Level (RTL) codes of different types of chips waiting for verification products. The daughter card is adapted to the FPGA carrier card of the FPGA prototype verification, and the daughter card and the FPGA carrier card can be connected through a general FPGA IO interface connector (hereinafter referred to as a connector for convenience of description), so as to occupy the FPGA IO interface by the daughter card.

At present, in the related art, limited by the hardware specification of the product, the number of connectors that can be provided by one FPGA card is limited, and in most cases, one connector is correspondingly plugged with one daughter card, that is, an interface provided by one connector can only be used by one daughter card, so that the number of the daughter cards plugged by the PFGA card is limited by the number of connectors, and because the number of the FPGA IO interfaces that need to be occupied by the daughter cards of different function types is greatly different, when the daughter cards with a small number of FPGA IO are plugged into a general connector, the IO that is not used on the connector is wasted. For example, as shown in fig. 1, four connectors may be provided on one FPGA card carrier, each connector has 52 IO signal interfaces, four daughter cards are plugged onto the card carrier through the four connectors, and the number of IO interfaces occupied by each daughter card is different, where daughter card 1 only needs to use 5 FPGA IO signal lines, and the spare 52-5-47 signal lines cannot be used by other daughter cards, which is equivalent to wasting nearly 90% of FPGA interface resources. In an actual application scenario, the prototype verification platform has a very high demand on FPGA IO interface resources, and the design makes the IO interface utilization rate low, so that the requirement of a large amount of FPGA interface resources cannot be met.

In view of this, the embodiments of the present application provide a daughter card and an electronic device supporting FPGA prototype verification, and a scheme of stacking the daughter cards is used to improve the interface utilization rate of IO and the number of daughter cards with plug-in functions of an FPGA prototype verification platform, solve the problem that an FPGA IO interface is greatly wasted, and ensure the universality of the FPGA prototype verification platform.

In a first aspect, an embodiment of the present application first provides a daughter card supporting FPGA prototype verification, where a circuit module is additionally arranged on the daughter card, the circuit module is used to transmit an IO interface, which is not occupied by the circuit module, at a bottom layer of the daughter card to a direction of a top surface of the daughter card, and after a connector is connected, other daughter cards may be plugged into the connector, so that the other daughter cards can continue to use the remaining IO interfaces.

For clarity of description, in the embodiment of the present application, the daughter card directly connected with the FPGA carrier through the connector is defined as a first daughter card, and each daughter card located on one side of the top surface of the first daughter card is sequentially defined as a second daughter card, a third daughter card, and the like.

In a possible implementation manner, only the circuit module is arranged on the first daughter card, and the IO interface which cannot be used by the first daughter card can be transferred upwards to improve the utilization rate of the IO interface. For example, referring to fig. 2, the daughter card provided by the present application at least includes a first daughter card 201, one side of a bottom surface (bottom) of the first daughter card 201 is connected to the FPGA carrier card 200 through a first connector 202, so as to enable the first daughter card to occupy a part of the FPGA IO interface provided by the FPGA carrier card 200, while the remaining IO interfaces are transmitted to a top surface (top) side of the first daughter card 201 through a first circuit module 2011, and the top surface side of the first daughter card 201 is fastened to a second connector 204, so that other daughter cards can be plugged into the second connector 204, so as to enable the remaining IO interfaces to be occupied. From another perspective, referring to the two dashed lines shown in fig. 2, the embodiments of the present application provide a solution that is equivalent to directing a portion of the FPGA IO interface signals to the lower pin of the first daughter card (as shown by dashed line L1), which is usable by the first daughter card, while the other FPGA IO interface signals are directed to the top side of the first daughter card (as shown by dashed line L2), which is usable by the other daughter card above the first daughter card. It should be noted that the two dotted lines are only used to illustrate the transfer effect of the FPGA IO interface, and there is no actual line shown by the dotted line.

In another possible implementation manner, two daughter cards located at the bottom layer in the daughter card stacking sequence, that is, the first daughter card and the second daughter card, may also have corresponding circuit modules respectively routed thereon. And the circuit module of the second daughter card is used for connecting a pin corresponding to the FPGA IO interface which is not occupied on one side of the bottom surface of the second daughter card to one side of the top surface of the second daughter card, so that when any third daughter card is connected with one side of the top surface of the second daughter card through the third connector, part or all of the remaining FPGA IO interfaces which are not occupied by the first daughter card 201 or the second daughter card 203 can be occupied. For example, when the sum of the number of the FPGA IO interfaces occupied by the first daughter card and the second daughter card is less than the number of the FPGA IO interfaces provided by the first connector, the top surface side of the second daughter card is further connected to the bottom surface side of the third daughter card through the connector, so that the third daughter card continues to use the remaining IO interfaces.

Illustratively, referring to fig. 3, a bottom surface (bottom surface) B of the first daughter card 201 is connected to the FPGA carrier card 200 through a first connector 202, 5 interfaces of 52 FPGA IO interfaces provided by the first connector are occupied by the first daughter card 201, and based on a circuit module disposed on the first daughter card 201, the remaining 47 unoccupied FPGA IO interfaces on one side of the bottom surface of the first daughter card 201 are transferred upward to a top surface (top surface) T of the first daughter card, for example, a dotted line shows a general direction of transferring from a bottom layer to an upper layer. After the second connector 204 is snapped on the top surface of the first daughter card, the second daughter card 203 may occupy some or all of the remaining 47 IO interface resources by plugging into the second connector 204. In this way, the remaining IO interfaces not occupied by the first daughter card 201 may be continuously used by the second daughter card 203, and if the sum of the number of IO interfaces occupied by the first daughter card and the number of IO interfaces occupied by the second daughter card is still less than the number of interfaces provided by the first connector 202, the third daughter card 205 may be further continuously stacked on the second daughter card, and the third daughter card 205 is connected to the second daughter card 203 through the third connector 206.

It should be noted that the dotted line in fig. 3 is only a simple illustration of the general transmission direction of the pins of the IO interface in one daughter card, and is not a limitation to the actual wiring path or the actual wiring direction. The actual wiring diagram is complex, and the wiring modes of the functional daughter cards are different, and the embodiments of the present application are not listed one by one.

By analogy, the IO interfaces can be sequentially transmitted upwards, two adjacent daughter cards are connected through the connector, at least one other daughter card can be stacked on one side of the top surface of the first daughter card, and the other daughter cards and the first daughter card share the IO interfaces provided by the first connector at the bottommost layer.

In other possible implementations, corresponding circuit modules may be distributed on each daughter card. And the circuit module distributed by each daughter card is used for transmitting the IO interface signals still left after the partial interfaces are occupied by the daughter card of the layer upwards to the top surface side of the daughter card of the layer.

For example, referring to fig. 3, a plurality of daughter cards are stacked above the FPGA carrier card, 16 daughter cards may be simultaneously inserted into one FPGA carrier card, and 4 daughter cards may be sequentially inserted into a connector at a bottom layer, so that the 4 daughter cards share an IO interface provided by one connector at the bottom layer.

In some embodiments, the daughter card may be a Printed Circuit Board (PCB), and the addition of the Circuit module may be implemented by PCB technology. Specifically, a plurality of first pins for interfacing with an FPGA IO interface may be disposed on one side of the bottom surface of the circuit module, and a plurality of second pins corresponding to the plurality of first pins may be disposed on one side of the top surface of the circuit module.

As a possible implementation, the pin numbers on the bottom side of the daughter card are kept identical to the numbers of the bottom connectors, while the pin numbers on the top side are renumbered starting from the lowest number. In other words, in the embodiment of the present application, the PINs of the FPGA interface connector are allocated to use the low-order PINs (for example, sequentially ascending from PIN1 to PIN 2), so as to improve the versatility of the FPGA prototype verification platform.

Taking the first sub-card as an example, the numbers of the plurality of first pins of the first sub-card are consistent with the pin numbers of the FPGA IO interface on the FPGA carrier card, the numbers of the plurality of second pins are numbered sequentially from the lowest number value, the lowest number value may be 0 or 1, and then the pins on the top surface side are numbered from 0 or 1. For example, after the bottom layer 52 IO interfaces are occupied for 5, the numbers of the first pins at the bottom of the circuit module of the first daughter card are consistent with the numbers on the FPGA card carrier, so as to facilitate the plugging of the bottom surface with the first connector, and after the remaining 47 IO interfaces are transferred to the top surface of the first daughter card, the 47 pins are numbered from the lowest number value, for example, numbered from 1, which is designed because the specification of the connector is designed to be adapted to the FPGA card carrier, and when the daughter card is plugged onto the connector, the principle of occupying from the low-order pin is generally adopted, so that, optionally, after the IO interface resources are transplanted to the top surface side of the daughter card, the IO interfaces are still numbered from the lowest order to facilitate the plugging of other daughter cards, which can improve the universality and the adaptability.

It should be noted that the above embodiments of the first aspect of the present application are intended to describe the daughter card, the daughter card may be designed and used as a stand-alone product, and the carrier card and the connector are not necessarily limited to the daughter card product.

In a second aspect, an embodiment of the present application further provides an electronic device supporting FPGA prototype verification, including an FPGA card, at least one connector, and at least two daughter cards; the FPGA IO interface is connected with the first daughter card through the FPGA, wherein at least the first daughter card is provided with a circuit module, so that the IO interface resources left after the first daughter card occupies part of the FPGA IO interface can be transmitted layer by layer. For the circuit module, reference is made to the above-mentioned embodiment of the first aspect, and details are not repeated.

In the embodiment of the second aspect of the present application, it is intended to describe an overall apparatus of an FPGA verification platform, where at least one second daughter card is stacked on one side of a top surface of a first daughter card, and different daughter cards are connected through a connector. The embodiments of the first aspect are referred to for designing top-side and bottom-side pins of a circuit module.

As a possible implementation manner, in the electronic device, adjacent pins around the FPGA IO interface on the FPGA card are all connected to GND (ground). The signal integrity is reduced because the upward transmission process can cause the signal to be lost and interfered by other signals and noise, and the signal integrity can be maintained to a certain extent by grounding adjacent pins around the pins, so that the interference of adjacent signals is reduced.

Accordingly, as a possible implementation, the adjacent pins around the plurality of first pins or second pins of the bottom surface or the top surface of the circuit module of the daughter card are also connected to GND.

For example, referring to table 1 below, an FPGA card with 160 pins (pins) is provided, and pins around four sets of IO signals of AX/BX/CX/DX are grounded. Wherein "G" in Table 1 below represents ground, A0-A12, B0-B12, C0-C12, and D0-D12 represent AX, BX, CX, and DX group pins, respectively, and VCCO represents IO voltage.

TABLE 1

In one possible implementation, the connectors used to connect the first daughter card to the FPGA are of the same product specification and material as the connectors used to connect the different daughter cards, e.g., the first and second connectors and other connectors that may be used in the upper layers are of the same material number (part code). As one possible implementation, the connector employs a high-speed, high-density connector interface.

It should be noted that, the electronic device provided in the embodiment of the present application does not need to change the product specifications of the FPGA card and the connector, and only needs to set the circuit module on the daughter card, and the improved daughter card can be adapted to the general FPGA daughter card and the connector.

An embodiment of the present application further provides an electronic device supporting FPGA prototype verification, which includes an FPGA circuit board, and a daughter card as described in the embodiment of the first aspect or an electronic device as described in the embodiment of the second aspect.

To sum up, the daughter card and the electronic equipment that support FPGA prototype verification that this application embodiment provided are connected to the connector of the top face of function daughter card through the signal that need not use on with FPGA interface connector to be used for pegging graft other function daughter cards, and then can upwards pile up many function daughter cards, reach the effect that many daughter cards piled up, improve the IO's of FPGA prototype interface utilization ratio and the function daughter card quantity of pegging graft.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the procedures or functions described in accordance with the present application are generated, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (e.g., coaxial cable, fiber optic, digital subscriber line) or wirelessly (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk), among others.

In the embodiments of the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, and means that there may be three relationships, for example, a and/or B, and may mean that a exists alone, a and B exist simultaneously, and B exists alone. Wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" and similar expressions refer to any combination of these items, including any combination of singular or plural items. For example, at least one of a, b, and c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or multiple.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A daughter card supporting FPGA prototype verification is adapted to an FPGA carrier card supporting FPGA prototype verification,

the daughter cards comprise a first daughter card, and one side of the bottom surface of the first daughter card is connected with the FPGA carrier card through a first connector so as to occupy an FPGA IO interface provided by the FPGA carrier card; one side of the top surface of the first daughter card is used for stacking at least one daughter card;

at least a circuit module is arranged on the first sub card and used for connecting the FPGA IO interfaces on one side of the bottom surface of the first sub card, which are not occupied by the first sub card, to one side of the top surface of the first sub card, so that when one side of the bottom surface of the second sub card is connected with one side of the top surface of the first sub card through a second connector, the second sub card occupies at least one of the unoccupied FPGA IO interfaces.

2. The daughter card of claim 1,

the daughter card further comprises any daughter card stacked on one side of the top surface of the first daughter card, and a corresponding circuit module is arranged on any daughter card and used for connecting an unoccupied FPGA IO interface on one side of the bottom surface of the corresponding daughter card to one side of the top surface of the corresponding daughter card.

3. The daughter card of claim 1,

a plurality of first pins for butting an FPGA IO interface are distributed on one side of the bottom surface of the circuit module; the serial numbers of the first pins are consistent with the serial numbers of the pins of the FPGA IO interface provided by the FPGA card;

and a plurality of second pins corresponding to the first pins are distributed on one side of the top surface of the circuit module, the serial numbers of the second pins are sequentially numbered from the lowest serial number value, and the lowest serial number value comprises 0 or 1.

4. An electronic device supporting FPGA prototype verification,

the FPGA card reader comprises an FPGA card carrier, at least one connector and at least two daughter cards; wherein the content of the first and second substances,

5. The electronic device of claim 4,

and corresponding circuit modules are uniformly distributed on any daughter card stacked on one side of the top surface of the first daughter card, so that the unoccupied FPGA IO interfaces on one side of the bottom surface of the corresponding daughter card are connected to one side of the top surface of the corresponding daughter card.

6. The electronic device of claim 4,

a plurality of first pins for butting the unoccupied FPGA IO interface are distributed on one side of the bottom surface of the circuit module; the serial numbers of the first pins are consistent with the serial numbers of the pins of the FPGA IO interface provided by the FPGA card;

a plurality of second pins corresponding to the first pins are distributed on one side of the top surface of the circuit module and used for butting the second connector; the numbers of the plurality of second pins are sequentially numbered from a lowest number value, the lowest number value including 0 or 1.

7. The electronic device of claim 4,

and adjacent pins around the FPGA IO interface on the FPGA carrier card are all connected with GND.

8. The electronic device of claim 6,

and adjacent pins around the first pin or the second pin are connected with GND.

9. The electronic device of claim 5,

and the product specification and the material of each connector in the same electronic equipment are the same.

10. An electronic device supporting FPGA proto-verification, comprising an FPGA circuit board, and a daughter card according to any one of claims 1 to 3 or an electronic device according to any one of claims 4 to 9.