CN113452872B - Processor and display method - Google Patents

Processor and display method Download PDF

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Publication number
CN113452872B
CN113452872B CN202010162152.7A CN202010162152A CN113452872B CN 113452872 B CN113452872 B CN 113452872B CN 202010162152 A CN202010162152 A CN 202010162152A CN 113452872 B CN113452872 B CN 113452872B
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China
Prior art keywords
video data
overdrive
frame
input video
circuit
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CN202010162152.7A
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Chinese (zh)
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CN113452872A (en
Inventor
魏瑞德
陈柏安
林伟智
陈雍之
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Realtek Semiconductor Corp
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Realtek Semiconductor Corp
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/62Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/222Studio circuitry; Studio devices; Studio equipment
    • H04N5/262Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/222Studio circuitry; Studio devices; Studio equipment
    • H04N5/262Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
    • H04N5/268Signal distribution or switching

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

A processor is used for coupling a display panel. The processor includes a first storage circuit, a conversion circuit and an overdrive circuit. The first storage circuit is used for storing input video data. The conversion circuit is used for receiving input video data and adjusting the frame rate of the input video data to generate adjusted video data. The overdrive circuit is used for executing an overdrive program according to the adjustment video data to generate a drive signal so that the display panel displays video according to the adjustment video data and the drive signal.

Description

Processor and display method
Technical Field
The present application relates to a circuit technology, and more particularly, to a processor for display and a display method.
Background
With the development of technology, displays have been used in various fields. The gray scale Response Time (RT) of the liquid crystal in the lcd is slower than other displays. This will affect the user's experience. For example, when the lcd displays a dynamic picture, a user can easily see a motion picture (motion picture) due to the slow gray scale response time of the lcd. Based on this, the gray scale response time of the liquid crystal is an important indicator of the performance of the liquid crystal display.
Disclosure of Invention
Some embodiments of the application relate to a processor. The processor is used for coupling with the display panel. The processor includes a first storage circuit, a conversion circuit and an overdrive circuit. The first storage circuit is used for storing input video data. The conversion circuit is used for receiving input video data and adjusting the frame rate of the input video data to generate adjusted video data. The overdrive circuit is used for executing an overdrive program according to the adjustment video data to generate a drive signal so that the display panel displays video according to the adjustment video data and the drive signal.
Some embodiments of the application relate to a processor. The processor is used for coupling with the display panel. The display panel includes an overdrive circuit. The processor includes a first storage circuit and a conversion circuit. The first storage circuit is used for storing input video data. The conversion circuit is used for receiving input video data and adjusting the frame rate of the input video data to generate adjusted video data. The overdrive circuit is used for executing an overdrive program according to the adjustment video data to generate a drive signal so that the display panel displays video according to the adjustment video data and the drive signal.
Some embodiments of the application relate to a display method. The display method comprises the following steps: receiving input video data through a first storage circuit; adjusting a frame rate of the input video data by the conversion circuit to generate adjusted video data; and executing an overdrive program by the overdrive circuit according to the adjustment video data to generate a drive signal so that the display panel displays video according to the adjustment video data and the drive signal.
In summary, the processor and the display method of the present application can accelerate the response time of the display panel and avoid the occurrence of the reverse ghost.
Drawings
The foregoing and other objects, features, advantages and embodiments of the application will be apparent from the following description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a schematic diagram of a display system according to some embodiments of the application;
FIG. 2 is a schematic diagram of raw video data and driving signals;
FIG. 3 is a schematic diagram of processed video data and driving signals according to some embodiments of the application;
FIG. 4 is a schematic diagram of input video data, unprocessed output video data, and processed adjusted video signals according to some embodiments of the present application;
FIG. 5 is a schematic diagram of a display system according to some embodiments of the application; and
Fig. 6 is a flow chart of a display method according to some embodiments of the application.
Symbol description:
100. 500: display system
120: Processor and method for controlling the same
122: Storage circuit
124: Conversion circuit
126. 146: Overdrive circuit
1261. 1461: Storage circuit
140: Display panel
600: Display method
SS: signal source
IV0: frequency data
IV: inputting video data
OV: adjusting video data
DS0, DS: drive signal
LUT: lookup table
F1, F2, F3, F11, F12, F21, F22, F31, F32: frame(s)
A. B, C, A1, A2, B1, B2, C1, C2: displaying data
DT1, DT2: delay time
T1 and T2: time point
S610, S620, S630: operation of
Detailed Description
The term "coupled," as used herein, may also refer to "electrically coupled," and the term "connected" may also refer to "electrically connected. "coupled" and "connected" may also mean that two or more elements co-operate or interact with each other.
Reference is made to fig. 1. Fig. 1 is a schematic diagram of a display system 100 according to some embodiments of the application. For example, in fig. 1, the display system 100 includes a signal source SS, a processor 120, and a display panel 140. The processor 120 includes a storage circuit 122, a conversion circuit 124, and an overdrive (overdrive) circuit 126. The overdrive circuit 126 includes a storage circuit 1261. In some embodiments, the storage circuit 1261 is implemented as a frame buffer (frame buffer). In some embodiments, the display panel 140 is implemented as a Liquid Crystal Display (LCD) panel (liquid CRYSTAL DISPLAY).
The signal source SS is coupled to the storage circuit 122. The storage circuit 122 is coupled to the conversion circuit 124. The conversion circuit 124 is coupled to the overdrive circuit 126 and the display panel 140. The overdrive circuit 126 is coupled to the display panel 140.
In operation, the source SS sends out input video data IV. The input video data IV includes video data for display by the display panel 140. The storage circuit 122 stores the input video data IV. The conversion circuit 124 is configured to receive the input video data IV and adjust a frame rate of the input video data IV (FRAME RATE) to generate the adjusted video data OV. In some embodiments, the conversion circuit 124 is implemented as a circuit having a frame rate conversion (FRAME RATE conversion) function. In some embodiments, the conversion circuit 124 may adjust the frame rate of the input video data IV up to produce the adjusted video data OV. The overdrive circuit 126 performs an overdrive process according to the adjusted video data OV to generate the driving signal DS. The display panel 140 receives the adjusted video data OV and the driving signal DS to display a corresponding video according to the adjusted video data OV and the driving signal DS.
Reference is made to fig. 2. Fig. 2 is a schematic diagram of unprocessed video data IV0 and driving signal DS 0. For example, in fig. 2, in some related art, the unprocessed video data IV0 includes at least a frame F1, a frame F2, and a frame F3. The frames F1-F3 correspond to display data A, display data B, and display data C, respectively. As previously described, in some embodiments, the display panel 140 is implemented as a liquid crystal display panel. The gray scale Response Time (RT) of the liquid crystal in the lcd panel is slower than that of other lcd panels. The gray scale reaction time is defined as the time for the gray scale to rise from 10% to 90%. If the gray scale response time is slow, the user's feeling will be affected. For example, when the lcd displays a dynamic picture, a user can easily see a motion picture (motion picture) due to the slow gray scale response time of the lcd. In some related art, an overdrive process is used to reduce the occurrence of the smear phenomenon by using the overdrive driving signal DS 0. However, the overdrive program easily generates overshoot (overshoot), thereby generating an inverse ghost.
Reference is made to fig. 3. Fig. 3 is a schematic diagram of processed video data (i.e., adjusted video data OV) and Driving Signals (DS) according to some embodiments of the application. Compared to the related art described above, the conversion circuit 124 of the present application increases the frame rate of the input video data IV. For example, if the conversion circuit 124 increases the frame rate of the input video data IV in fig. 2 by two times to generate the adjusted video data OV in fig. 3, the frame rate of the adjusted video data OV in fig. 3 will be twice the frame rate of the input video data IV in fig. 2. For the example of fig. 2 and 3, the frame F1 of fig. 2 is split into the frame F11 and the frame F12 of fig. 3, and the display data a of fig. 2 is repeatedly displayed twice to become the display data A1 and the display data A2 of fig. 3, the display data A1 corresponds to the frame F11, and the display data A2 corresponds to the frame F12. The frame F2 of fig. 2 is split into and corresponds to the frame F21 and the frame F22 of fig. 3, and the display data B of fig. 2 is repeatedly displayed twice as the display data B1 and the display data B2 of fig. 3, the display data B1 corresponds to the frame F21, and the display data B2 corresponds to the frame F22. The frame F3 of fig. 2 is split into and corresponds to the frame F31 and the frame F32 of fig. 3, and the display data C of fig. 2 is repeatedly displayed twice as the display data C1 and the display data C2 of fig. 3, the display data C1 corresponds to the frame F31, and the display data C2 corresponds to the frame F32. Even though the frame rate of the adjusted video data OV in fig. 3 is higher than that of the input video data IV in fig. 2 through the above adjustment, the display data of the adjusted video data OV in fig. 3 is the same as that of the input video data IV in fig. 2, so that the visual effect observed by the user is unchanged.
The above-described number of frames of the unprocessed video data IV0 and the adjusted video data OV is for illustrative purposes only, and various applicable numbers of frames are within the scope of the present application. For example, the number of frames of the input video data IV may be more than three, while the conversion circuit 124 may increase the frame rate of the input video data IV by more than two times to produce the adjusted video data OV, e.g., three or more times.
On the other hand, the overdrive circuit 126 may output the driving signal DS according to the adjusted video data OV. For example, in FIG. 3, if the display data B2 of the frame F22 (e.g., a dark frame with a low gray level) is different from the display data C1 of the frame 31 (e.g., a bright frame with a high gray level), the overdrive circuit 126 will perform overdrive on the driving signal DS corresponding to the frame F31. For example, the overdrive may be performed at the start time point of the frame F31.
In some embodiments, the overdrive circuit 126 determines the overdrive voltage according to the lookup table LUT stored in the storage circuit 1261 to execute the overdrive process based on the determined overdrive voltage. For example, if the gray level of the display data B2 of the frame F22 is 0 and the gray level of the display data C1 of the frame 31 is 128, the corresponding gray level is 160 (greater than 128) can be determined by the lookup table LUT to output the corresponding overdrive voltage. Pulling the gray scale (brightness) of the display panel 140 from 0 to 160 results in a faster rise of the driving signal DS (overdrive) than pulling the gray scale (brightness) of the display panel 140 from 0 to 128.
The overdrive program is adopted during the picture conversion, so that the gray scale reaction time of the liquid crystal can be quickened. In addition, since the overdrive can only last for a single frame, the overdrive will stop at the end time of frame F31. Accordingly, shortening the time of a single frame in fig. 3 effectively avoids overshoot of the driving signal DS.
The above embodiment has been described taking an example of executing an overdrive program when converting display data of a low gradation into display data of a high gradation, but the present application is not limited thereto. The overdrive program can also be executed when the display data with high gray level is converted into the display data with low gray level, so as to accelerate the gray level reaction time of the liquid crystal.
After determining the adjusted video data OV and the driving signal DS, the display panel 140 can display the corresponding video according to the adjusted video data OV and the driving signal DS. As described above, the display panel 140 may be a liquid crystal display panel. Accordingly, the adjustment video data OV can be used to control the frame rate in the display panel 140, and the driving signal DS can be used to control the rotation degree of the liquid crystal in the display panel 140 to control the transmittance of the liquid crystal. In this way, the backlight module of the display panel 140 can be matched with the rotating liquid crystal to achieve the display function.
Fig. 4 is a schematic diagram of the input video data IV, the unprocessed output video data IV0, and the processed adjusted video signal OV according to some embodiments of the present application.
For example, in fig. 2 and 4, the input video data IV input into the processor 120 includes display data a, display data B, and display data C. If the input video data IV is not subjected to the frame rate increasing process, the video data IV0 input to the display panel 140 also includes the display data a, the display data B, and the display data C. Based on the delay of the electronic components, there will be a delay time DT1 between the video data IV0 input into the display panel 140 and the input video data IV input into the processor 120. As illustrated in fig. 3 and 4, the adjusted video data OV with the increased frame rate includes display data A1, display data A2, display data B1, display data B2, display data C1, and display data C2. As described above, the display data of the adjustment video signal OV processed by the conversion circuit 124 is the same as the display data of the input video data IV. Accordingly, the visual effect observed by the user is unchanged. However, there is a delay time DT2 between the adjusted video signal OV and the input video data IV. The delay time DT2 (e.g., 6-7 milliseconds) is substantially slightly greater than the delay time DT1 (e.g., 2 milliseconds). Since the delay time DT2 is only slightly longer than the delay time DT1, the viewing experience of the user is not affected.
In general, the end time point of the display data of the adjusted video signal OV will be located after the end time point of the corresponding display data of the input video data IV. For example, the end time point T2 of the display data A1 of the adjusted video signal OV falls after the end time point T1 of the corresponding display data a of the input video data IV. In this way, it is ensured that the display data A1 is correctly and completely displayed after the display data a is received.
Reference is made to fig. 5. Fig. 5 is a schematic diagram of a display system 500 according to some embodiments of the application. The main difference between the display system 500 of fig. 5 and the display system 100 of fig. 1 is that the overdrive circuit 146 of the display system 500 of fig. 5 is included in the display panel 140. The operation of overdrive circuit 146 in fig. 5 is similar to the operation of overdrive circuit 126 in fig. 1. For example, the overdrive circuit 146 in fig. 5 includes a storage circuit 1461, and the storage circuit 1461 stores a look-up table LUT. Other components and operations of the display system 500 of fig. 5 are similar to those of the display system 100 of fig. 1, and thus, are not described in detail herein.
Refer to fig. 6. Fig. 6 is a flow chart of a display method 600 according to some embodiments of the application. The display method 600 includes operations S610, S620, and S630.
In some embodiments, the display method 600 is applied to the display system 100 of fig. 1 or the display system 500 of fig. 5, but the application is not limited thereto. For ease of understanding, the display method 600 will be discussed in connection with the display system 100 of FIG. 1 or the display system 500 of FIG. 5.
In operation S610, input video data IV is received through the storage circuit 122. In some embodiments, the input video data IV is from a signal source SS.
In operation S620, the frame rate of the input video data IV is adjusted by the conversion circuit 124 to generate the adjusted video data OV. In some embodiments, the frame rate of the adjusted video data OV is more than twice the frame rate of the input video data IV.
In operation S630, an overdrive program is executed by the overdrive circuit 126 or the overdrive circuit 146 according to the adjusted video data OV to generate the driving signal DS. Accordingly, the display panel 140 can display video according to the adjusted video data OV and the driving signal DS. In some embodiments, overdrive circuit 126 is disposed in processor 120. In some other embodiments, the overdrive circuit 146 is disposed in the display panel 140.
In some embodiments, the display method 600 may be applied to cases where the picture update frequency is low. In some related art, when the frame refresh frequency is low, the overdrive voltage is too large to cause serious reverse image sticking. Through the display method 600, not only the gray-scale response time of the liquid crystal is accelerated, but also the overshoot phenomenon is effectively avoided, and thus the generation of the reverse ghost is avoided under the condition of low picture update frequency.
The various operations of the display method 600 described above are merely examples and are not limited to being performed in the order in which they were presented. The various operations of display method 600 may be added, substituted, omitted, or performed in a different order as appropriate without departing from the manner and scope of operation of the various embodiments of the application.
In summary, the processor and the display method of the present application can accelerate the response time of the display panel and avoid the occurrence of the reverse ghost.
Various functional components and blocks have been disclosed herein. It will be apparent to one of ordinary skill in the art that functional blocks may be implemented by circuits, whether special purpose circuits or general purpose circuits that operate under the control of one or more processors and code instructions, and typically include transistors or other circuit elements that control electrical circuitry corresponding to the functions and operations described herein. As will be further appreciated, the specific structure and interconnection of circuit elements may generally be determined by a compiler (compiler), such as a Register Transfer Language (RTL) compiler. The buffer transfer language compiler operates on a script (script) that is quite similar to the assembly language code (assembly language code), compiling the script into a form for layout or making the final circuit. Indeed, buffer transfer languages are known for their role and purpose in facilitating the design of electronic and digital systems.
Although the present application has been described in terms of the above embodiments, the above embodiments are not intended to limit the present application, and any person skilled in the art should make various modifications and adaptations without departing from the spirit and scope of the present application, so the scope of the present application should be limited only by the claims.

Claims (9)

1. A processor for coupling to a display panel, the processor comprising:
A first storage circuit for storing input video data;
A conversion circuit for receiving the input video data and adjusting a frame rate of the input video data to generate adjusted video data; and
The overdrive circuit is used for executing an overdrive program according to the adjustment video data so as to generate a drive signal, so that the display panel displays video according to the adjustment video data and the drive signal;
wherein when the frame rate is increased by a factor of 2, the first frame of the input video data corresponds to the second frame and the third frame of the adjusted video data.
2. The processor of claim 1, wherein the conversion circuit is further to increase the frame rate of the input video data.
3. The processor of claim 2, wherein the conversion circuit is further to increase the frame rate of the input video data by at least a factor of 2.
4. The processor of claim 1, wherein the overdrive is executed in response to the third frame of the adjusted video data if the third frame of the adjusted video data is different from the second frame of the adjusted video data.
5. The processor of claim 4, wherein the overdrive circuit comprises:
The second storage circuit is used for storing a lookup table, wherein the overdrive circuit is also used for determining overdrive voltage according to the lookup table so as to execute the overdrive program according to the overdrive voltage.
6. A processor for coupling to a display panel, the display panel comprising overdrive circuitry, the processor comprising:
a first storage circuit for storing input video data; and
A conversion circuit for receiving the input video data and adjusting a frame rate of the input video data to generate adjusted video data,
The overdrive circuit is used for executing an overdrive program according to the adjustment video data so as to generate a drive signal, so that the display panel displays video according to the adjustment video data and the drive signal;
wherein when the frame rate is increased by a factor of 2, the first frame of the input video data corresponds to the second frame and the third frame of the adjusted video data.
7. The processor of claim 6, wherein the conversion circuit is further to increase the frame rate of the input video data.
8. A display method, the display method comprising:
Receiving input video data through a first storage circuit;
Adjusting, by a conversion circuit, a frame rate of the input video data to produce adjusted video data, wherein a first frame of the input video data corresponds to a second frame and a third frame of the adjusted video data when the frame rate is increased by a factor of 2; and
And executing an overdrive program by the overdrive circuit according to the adjustment video data so as to generate a drive signal, so that the display panel displays video according to the adjustment video data and the drive signal.
9. The display method of claim 8, wherein adjusting the frame rate of the input video data by the conversion circuit comprises:
the frame rate of the input video data is also used to be increased by the conversion circuit.
CN202010162152.7A 2020-03-10 2020-03-10 Processor and display method Active CN113452872B (en)

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