CN113452872A - Processor and display method - Google Patents
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- CN113452872A CN113452872A CN202010162152.7A CN202010162152A CN113452872A CN 113452872 A CN113452872 A CN 113452872A CN 202010162152 A CN202010162152 A CN 202010162152A CN 113452872 A CN113452872 A CN 113452872A
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- 238000000034 method Methods 0.000 title claims description 28
- 238000006243 chemical reaction Methods 0.000 claims abstract description 29
- 238000003860 storage Methods 0.000 claims abstract description 23
- 230000004044 response Effects 0.000 claims description 12
- 239000004973 liquid crystal related substance Substances 0.000 description 15
- 238000010586 diagram Methods 0.000 description 9
- 230000008569 process Effects 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 238000013515 script Methods 0.000 description 3
- 238000012546 transfer Methods 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- 238000012938 design process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/62—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/268—Signal distribution or switching
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
A processor is coupled to a display panel. The processor comprises a first storage circuit, a conversion circuit and an overdrive circuit. The first storage circuit is used for storing input video data. The conversion circuit is used for receiving input video data and adjusting the frame rate of the input video data to generate adjusted video data. The overdrive circuit is used for executing an overdrive program according to the adjusted video data to generate a driving signal, so that the display panel displays a video according to the adjusted video data and the driving signal.
Description
Technical Field
The present application relates to a circuit technology, and more particularly, to a processor for displaying and a display method.
Background
With the development of technology, displays have been applied to various fields. The gray scale Response Time (RT) of liquid crystals in lcds is slower than other displays. This will affect the user's experience. For example, when the lcd displays a dynamic image, the user can easily see the motion blur due to the slow gray level response time of the liquid crystal. Therefore, the gray scale response time of the liquid crystal is really an important index for the performance of the liquid crystal display.
Disclosure of Invention
Some embodiments of the present application relate to a processor. The processor is coupled to the display panel. The processor comprises a first storage circuit, a conversion circuit and an overdrive circuit. The first storage circuit is used for storing input video data. The conversion circuit is used for receiving input video data and adjusting the frame rate of the input video data to generate adjusted video data. The overdrive circuit is used for executing an overdrive program according to the adjusted video data to generate a driving signal, so that the display panel displays a video according to the adjusted video data and the driving signal.
Some embodiments of the present application relate to a processor. The processor is coupled to the display panel. The display panel includes an overdrive circuit. The processor comprises a first storage circuit and a conversion circuit. The first storage circuit is used for storing input video data. The conversion circuit is used for receiving input video data and adjusting the frame rate of the input video data to generate adjusted video data. The overdrive circuit is used for executing an overdrive program according to the adjusted video data to generate a driving signal, so that the display panel displays a video according to the adjusted video data and the driving signal.
Some embodiments of the present application relate to a display method. The display method comprises the following steps: receiving input video data through a first storage circuit; adjusting a frame rate of input video data through a conversion circuit to generate adjusted video data; and executing an overdrive program through the overdrive circuit according to the adjusted video data to generate a driving signal, so that the display panel displays a video according to the adjusted video data and the driving signal.
In summary, the processor and the display method of the present application can accelerate the response time of the display panel and avoid generating the inverse ghost.
Drawings
In order to make the above and other objects, features, and advantages of the present application more comprehensible, the following description is made with reference to the accompanying drawings:
FIG. 1 is a schematic diagram of a display system according to some embodiments of the present application;
FIG. 2 is a schematic illustration of unprocessed video data and drive signals;
FIG. 3 is a schematic diagram of processed video data and driving signals according to some embodiments of the present application;
FIG. 4 is a schematic diagram of input video data, unprocessed output video data, and processed adjusted video signal according to some embodiments of the present application;
FIG. 5 is a schematic diagram of a display system according to some embodiments of the present application; and
fig. 6 is a flowchart of a display method according to some embodiments of the present application.
Description of the symbols:
100. 500: display system
120: processor with a memory having a plurality of memory cells
122: storage circuit
124: switching circuit
126. 146: overdrive circuit
1261. 1461: storage circuit
140: display panel
600: display method
And SS: signal source
IV 0: frequency data
IV: inputting video data
OV: adjusting video data
DS0, DS: drive signal
LUT: lookup table
F1, F2, F3, F11, F12, F21, F22, F31, F32: frame
A. B, C, A1, A2, B1, B2, C1, C2: displaying data
DT1, DT 2: delay time
T1, T2: point in time
S610, S620, S630: operation of
Detailed Description
The term "coupled," as used herein, may also refer to "electrically coupled," and the term "connected," may also refer to "electrically connected. "coupled" and "connected" may also mean that two or more elements co-operate or interact with each other.
Refer to fig. 1. Fig. 1 is a schematic diagram of a display system 100 according to some embodiments of the present application. For the example of fig. 1, the display system 100 includes a signal source SS, a processor 120, and a display panel 140. The processor 120 includes a storage circuit 122, a conversion circuit 124, and an over drive (over drive) circuit 126. The overdrive circuit 126 includes a storage circuit 1261. In some embodiments, storage circuit 1261 is implemented as a frame buffer. In some embodiments, the display panel 140 is implemented as a Liquid Crystal Display (LCD) panel.
The signal source SS is coupled to the storage circuit 122. The storage circuit 122 is coupled to the conversion circuit 124. The conversion circuit 124 is coupled to the overdrive circuit 126 and the display panel 140. The overdrive circuit 126 is coupled to the display panel 140.
In operation, signal source SS sends out input video data IV. The input video data IV includes video data for display by the display panel 140. The storage circuit 122 stores the input video data IV. The conversion circuit 124 is configured to receive the input video data IV and adjust a frame rate (frame rate) of the input video data IV to generate the adjusted video data OV. In some embodiments, the conversion circuit 124 is implemented in a circuit having a frame rate conversion (frame rate conversion) function. In some embodiments, the conversion circuit 124 may adjust the frame rate of the input video data IV up to generate the adjusted video data OV. The overdrive circuit 126 executes an overdrive process according to the adjusted video data OV to generate the driving signal DS. The display panel 140 receives the adjustment video data OV and the driving signal DS to display a corresponding video according to the adjustment video data OV and the driving signal DS.
Refer to fig. 2. Fig. 2 is a schematic diagram of unprocessed video data IV0 and a driving signal DS 0. Taking the example of fig. 2, in some related art unprocessed video data IV0 includes at least frame F1, frame F2, and frame F3. The frames F1-F3 correspond to the display data A, the display data B, and the display data C, respectively. As previously described, in some embodiments, the display panel 140 is implemented as a liquid crystal display panel. The gray scale Response Time (RT) of the liquid crystal in the lcd panel is slower than that of other panels. The gray scale response time is defined as the time for the gray scale to rise from 10% to 90%. If the gray scale response time is slow, the user's experience will be affected. For example, when the lcd displays a dynamic image, the user can easily see the motion blur due to the slow gray level response time of the liquid crystal. In some related technologies, an overdrive process is used to reduce the occurrence of the smear by using the overdrive drive signal DS 0. However, the overdrive process is prone to overshoot, which in turn generates an inverse ghost.
Refer to fig. 3. Fig. 3 is a schematic diagram of the processed video data (i.e. the adjusted video data OV) and the Driving Signal (DS) according to some embodiments of the present application. Compared with the related art, the conversion circuit 124 of the present application adjusts the frame rate of the input video data IV to be high. For example, if the conversion circuit 124 increases the frame rate of the input video data IV in fig. 2 by two times to generate the adjusted video data OV in fig. 3, the frame rate of the adjusted video data OV in fig. 3 will be twice the frame rate of the input video data IV in fig. 2. In the example of fig. 2 and 3, the frame F1 of fig. 2 is divided into the frame F11 and the frame F12 of fig. 3, the display data a of fig. 2 is repeatedly displayed twice as the display data a1 and the display data a2 of fig. 3, the display data a1 corresponds to the frame F11, and the display data a2 corresponds to the frame F12. The frame F2 of fig. 2 is cut into and corresponds to the frame F21 and the frame F22 of fig. 3, the display data B of fig. 2 is repeatedly displayed twice as the display data B1 and the display data B2 of fig. 3, the display data B1 corresponds to the frame F21, and the display data B2 corresponds to the frame F22. The frame F3 of fig. 2 is cut into and corresponds to the frames F31 and F32 of fig. 3, the display data C of fig. 2 is repeatedly displayed twice as the display data C1 and the display data C2 of fig. 3, the display data C1 corresponds to the frame F31, and the display data C2 corresponds to the frame F32. Even though the frame rate of the adjusted video data OV in fig. 3 is higher than the frame rate of the input video data IV in fig. 2, the display data of the adjusted video data OV in fig. 3 is the same as the display data of the input video data IV in fig. 2, and thus the visual effect viewed by the user is not changed.
The above mentioned unprocessed video data IV0 and the number of frames of the adjusted video data OV are for illustrative purposes only and various applicable frame numbers are within the scope of the present application. For example, the number of frames of the input video data IV may be more than three, and the conversion circuit 124 may increase the frame rate of the input video data IV more than two times to generate the adjusted video data OV, for example, three times or more.
On the other hand, the overdrive circuit 126 may output the driving signal DS according to the adjusted video data OV. For example, as shown in FIG. 3, if the display data B2 (e.g., dark frames with low gray levels) of the frame F22 is different from the display data C1 (e.g., bright frames with high gray levels) of the frame 31, the overdrive circuit 126 will perform an overdrive process on the driving signal DS corresponding to the frame F31. For example, the overdrive may be performed at the start time of frame F31.
In some embodiments, the overdrive circuit 126 determines the overdrive voltage according to the look-up table LUT stored in the storage circuit 1261, so as to execute the overdrive process based on the determined overdrive voltage. For example, if the gray level of the display data B2 of the frame F22 is 0 and the gray level of the display data C1 of the frame 31 is 128, the corresponding gray level can be determined to be 160 (greater than 128) by the look-up table LUT to output the corresponding overdrive voltage. If the gray scale (brightness) of the display panel 140 is pulled from 0 to 160, the rising amplitude of the driving signal DS is faster (overdrive process) than if the gray scale (brightness) of the display panel 140 is pulled from 0 to 128.
And an overdrive program is adopted during picture conversion, so that the gray scale reaction time of the liquid crystal can be shortened. In addition, since the overdrive program can only maintain the time of a single frame, the overdrive program will stop at the end time point of the frame F31. Accordingly, the overshoot of the driving signal DS can be effectively avoided by shortening the time of a single frame in fig. 3.
The above embodiments have been described by taking an example in which the overdrive process is performed when the display data is changed from the low gray scale display data to the high gray scale display data, but the present application is not limited thereto. The overdrive process can also be performed when the display data of high gray scale is converted into the display data of low gray scale, so as to accelerate the gray scale response time of the liquid crystal.
After determining the adjustment video data OV and the driving signal DS, the display panel 140 can display a corresponding video according to the adjustment video data OV and the driving signal DS. As described above, the display panel 140 may be a liquid crystal display panel. Accordingly, the adjustment video data OV can be used to control the frame rate in the display panel 140, and the driving signal DS can be used to control the rotation degree of the liquid crystal in the display panel 140 to control the transmittance of the liquid crystal. In this way, the backlight module of the display panel 140 can cooperate with the rotating liquid crystal to achieve the display function.
Fig. 4 is a schematic diagram of input video data IV, unprocessed output video data IV0, and processed adjusted video signal OV according to some embodiments of the present application.
In the example of fig. 2 and 4, the input video data IV input into the processor 120 includes display data a, display data B, and display data C. If the input video data IV has not been subjected to the frame rate up processing, the video data IV0 input into the display panel 140 also includes display data a, display data B, and display data C. Based on the delay of the electronic components, there will be a delay time TD1 between the video data IV0 input into the display panel 140 and the input video data IV input into the processor 120. In the example of fig. 3 and 4, the frame rate up adjusted video data OV includes display data a1, display data a2, display data B1, display data B2, display data C1, and display data C2. As described above, the display data of the adjusted video signal OV processed by the conversion circuit 124 is the same as the display data of the input video data IV. Accordingly, the visual effect viewed by the user is unchanged. However, there is a delay time TD2 between the adjusted video signal OV and the input video data IV. The delay time TD2 (e.g., 6-7 milliseconds) is substantially slightly greater than the delay time TD1 (e.g., 2 milliseconds). Since the delay time TD2 is only slightly larger than the delay time TD1, the viewing experience of the user is not affected.
In general, the ending time point of the display data of the adjusted video signal OV is located after the ending time point of the corresponding display data of the input video data IV. For example, the ending time point T2 of the display data a1 of the video signal OV falls after the ending time point T1 of the corresponding display data a of the input video data IV. In this way, it is ensured that the display data a1 is correctly and completely displayed after the display data a is received.
Refer to fig. 5. Fig. 5 is a schematic diagram of a display system 500 according to some embodiments of the present application. The main difference between the display system 500 of FIG. 5 and the display system 100 of FIG. 1 is that the overdrive circuit 146 of the display system 500 of FIG. 5 is included in the display panel 140. The operation of the overdrive circuit 146 in FIG. 5 is similar to the operation of the overdrive circuit 124 in FIG. 1. For example, the overdrive circuit 146 in fig. 5 includes a storage circuit 1461, and the storage circuit 1461 stores a look-up table LUT. Other components and operations of the display system 500 of FIG. 5 are similar to those of the display system 100 of FIG. 1, and therefore, are not described again here.
Refer to fig. 6. Fig. 6 is a flow chart of a display method 600 according to some embodiments of the present application. The display method 600 includes operations S610, S620, and S630.
In some embodiments, the display method 600 is applied to the display system 100 of fig. 1 or the display system 500 of fig. 5, but the application is not limited thereto. For ease of understanding, the display method 600 will be discussed in conjunction with the display system 100 of FIG. 1 or the display system 500 of FIG. 5.
In operation S610, input video data IV is received through the storage circuit 122. In some embodiments, the input video data IV is from a signal source SS.
In operation S620, the frame rate of the input video data IV is adjusted by the conversion circuit 124 to generate the adjusted video data OV. In some embodiments, the frame rate of the adjusted video data OV is more than twice the frame rate of the input video data IV.
In operation S630, the overdrive circuit 126 or 146 performs an overdrive process according to the adjusted video data OV to generate the driving signal DS. Accordingly, the display panel 140 can display video according to the adjustment video data OV and the driving signal DS. In some embodiments, the overdrive circuit 126 is disposed in the processor 120. In some other embodiments, the overdrive circuit 146 is disposed in the display panel 140.
In some embodiments, the display method 600 can be applied to a case where the frequency of screen update is low. In some related technologies, when the frame refresh frequency is low, the overdrive voltage is too high, which may cause serious inverse image sticking. By the display method 600, the gray scale response time of the liquid crystal can be accelerated, and the overshoot phenomenon can be effectively avoided to avoid the generation of the inverse ghost image under the condition of low frame update frequency.
The operations of the display method 600 described above are merely examples and are not limited to being performed in the order of the examples. The various operations of the display method 600 may be suitably added, substituted, omitted, or performed in a different order without departing from the manner of operation and scope of the various embodiments of the present application.
In summary, the processor and the display method of the present application can accelerate the response time of the display panel and avoid generating the inverse ghost.
Various functional components and blocks have been disclosed herein. It will be apparent to those of ordinary skill in the art that functional blocks may be implemented by circuits (whether dedicated or general purpose circuits that operate under the control of one or more processors and coded instructions), which generally comprise transistors or other circuit elements that control electrical circuits in accordance with the functions and operations described herein. As will be further appreciated, the specific structure and interconnections of the circuit elements may generally be determined by a compiler, such as a Register Transfer Language (RTL) compiler. The buffer delivery language compiler operates on scripts (scripts) that are fairly similar to assembly language code (assembly language code) and compiles the scripts into a form for layout or fabrication of the final circuit. Indeed, register transfer languages are known for their role and purpose in facilitating the design process of electronic and digital systems.
Although the present application has disclosed the above embodiments, the above embodiments are not intended to limit the present application, and any person skilled in the art should make various modifications and adjustments without departing from the spirit and scope of the present application, therefore, the protection scope of the present application should be subject to the claims.
Claims (10)
1. A processor coupled to a display panel, the processor comprising:
a first storage circuit for storing input video data;
the conversion circuit is used for receiving the input video data and adjusting the frame rate of the input video data to generate adjusted video data; and
and the overdrive circuit is used for executing an overdrive program according to the adjusted video data to generate a driving signal so that the display panel displays a video according to the adjusted video data and the driving signal.
2. The processor of claim 1, wherein the conversion circuit is further to adjust the frame rate of the input video data high.
3. The processor of claim 2, wherein the conversion circuit is further to increase the frame rate of the input video data by at least a factor of 2.
4. The processor of claim 3, wherein a first frame of the input video data corresponds to a second frame and a third frame of the adjusted video data when the frame rate is adjusted up to 2 times.
5. The processor of claim 4, wherein the overdrive is performed in response to the third frame of the adjusted video data if the third frame of the adjusted video data is different from the second frame of the adjusted video data.
6. The processor of claim 5, wherein the overdrive circuit comprises:
the second storage circuit is used for storing a lookup table, wherein the overdrive circuit is further used for determining overdrive voltage according to the lookup table so as to execute the overdrive program according to the overdrive voltage.
7. A processor coupled to a display panel, the display panel comprising an overdrive circuit, the processor comprising:
a first storage circuit for storing input video data; and
a conversion circuit for receiving the input video data and adjusting a frame rate of the input video data to generate adjusted video data,
the overdrive circuit is used for executing an overdrive program according to the adjusted video data to generate a driving signal, so that the display panel displays a video according to the adjusted video data and the driving signal.
8. The processor of claim 7, wherein the conversion circuit is further to adjust the frame rate of the input video data high.
9. A display method, comprising:
receiving input video data through a first storage circuit;
adjusting, by a conversion circuit, a frame rate of the input video data to produce adjusted video data; and
and executing an overdrive program by an overdrive circuit according to the adjusted video data to generate a driving signal, so that the display panel displays a video according to the adjusted video data and the driving signal.
10. The display method of claim 9, wherein adjusting, by the conversion circuit, the frame rate of the input video data comprises:
the conversion circuit is further configured to increase the frame rate of the input video data.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010162152.7A CN113452872B (en) | 2020-03-10 | 2020-03-10 | Processor and display method |
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| CN202010162152.7A CN113452872B (en) | 2020-03-10 | 2020-03-10 | Processor and display method |
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| CN113452872B (en) | 2024-05-14 |
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