CN114974149B - Control circuit and control method applied to display panel - Google Patents
Control circuit and control method applied to display panel Download PDFInfo
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- CN114974149B CN114974149B CN202110191282.8A CN202110191282A CN114974149B CN 114974149 B CN114974149 B CN 114974149B CN 202110191282 A CN202110191282 A CN 202110191282A CN 114974149 B CN114974149 B CN 114974149B
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- 238000000034 method Methods 0.000 title claims description 21
- 238000012545 processing Methods 0.000 claims abstract description 55
- 230000005540 biological transmission Effects 0.000 claims abstract description 6
- 238000010586 diagram Methods 0.000 description 15
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 210000004556 brain Anatomy 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000002688 persistence Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0257—Reduction of after-image effects
Abstract
The invention discloses a control circuit applied to a display panel, which comprises a receiving interface, an image processing circuit and a transmitting interface. The receiving interface is used for receiving image data, wherein the image data has an unfixed frame rate; the image processing circuit is used for receiving the image data from the receiving interface and performing frequency multiplication operation on the image data according to the frame rate of the image data to generate output image data, wherein the frame rate of the output image data is positive integer multiple of the image data; and the transmission interface is used for receiving the output image data from the image processing circuit and transmitting the output image data to the display panel.
Description
Technical Field
The invention relates to a control circuit and a control method applied to a display panel.
Background
The display presented by a liquid crystal display may be generally referred to as a hold-TYPE DISPLAY display, in which the display is updated every 16.67 milliseconds (ms) for 60 updates per second (60 Hz), while the currently displayed display is stationary until the display is updated. One of the greatest drawbacks of conventional lcds is motion blur (motion blur), which is caused by the fact that eyes have a current expected position according to the speed of moving objects when tracking the objects, but because the time for updating the display of the lcd is discontinuous, there is an error between the actual position of the objects and the expected position of the brain at a specific point in time. On the other hand, because the human eyes have vision persistence and dynamic compensation, the brain can connect pictures in the process of tracking objects, and the effect similar to mathematical integration is achieved, so that if the picture update frequency is not high enough and the picture remains in a single position for too long, the effect of dynamic smear can be seen after the brain compensation is finished.
In the prior art, there is a method for solving the motion blur, such as inserting a compensation frame or inserting a black frame between two frames, however, since the lcd adopts a line-by-line (row) scanning method when displaying a frame, and the response time of the lcd may not be fast enough, the method may increase the calculation amount of the processing circuit, and there is a problem that the pixel synchronization is also generated, that is, the picture effects above and below the screen may not be consistent.
In addition, in some applications, the rate at which the image source generates the image data is not fixed, so some of the current lcds employ variable update rate (variable REFRESH RATE) display, i.e., the frame rate (FRAME RATE) of the image being displayed by the lcd varies with the rate of the received image data, i.e., does not have a fixed frame rate. In this case, how to effectively cope with the motion blur is an important issue.
Disclosure of Invention
Therefore, one of the objectives of the present invention is to provide a control circuit for a liquid crystal display, which can drive a display panel in a frequency doubling manner under the condition that the frame rate of image data is not fixed, so as to solve the problems in the prior art.
In one embodiment of the present invention, a control circuit for a display panel is disclosed, which includes a receiving interface, an image processing circuit and a transmitting interface. The receiving interface is used for receiving image data, wherein the image data has an unfixed frame rate; the image processing circuit is used for receiving the image data from the receiving interface and performing frequency multiplication operation on the image data according to the frame rate of the image data to generate output image data, wherein the frame rate of the output image data is positive integer multiple of the image data; and the transmission interface is used for receiving the output image data from the image processing circuit and transmitting the output image data to the display panel.
In another embodiment of the present invention, a control method applied to a display panel is disclosed, which includes the following steps: receiving image data, wherein the image data has a non-fixed frame rate; performing frequency multiplication operation on the image data according to the frame rate of the image data to generate output image data, wherein the frame rate of the output image data is positive integer multiple of the image data; and transmitting the output image data to the display panel.
Drawings
Fig. 1 is a schematic diagram of an electronic device according to an embodiment of the invention.
FIG. 2 is a timing diagram illustrating the operation of a control circuit according to one embodiment of the present invention.
Fig. 3 is a timing diagram illustrating operation of a control circuit according to another embodiment of the present invention.
Fig. 4 is a timing diagram illustrating operation of a control circuit according to another embodiment of the present invention.
Fig. 5 is a timing diagram illustrating operation of a control circuit according to another embodiment of the present invention.
Fig. 6 is a timing diagram illustrating operation of a control circuit according to another embodiment of the present invention.
Fig. 7 is a timing diagram illustrating operation of a control circuit according to another embodiment of the present invention.
Fig. 8 is a timing diagram illustrating operation of a control circuit according to another embodiment of the present invention.
Detailed Description
Fig. 1 is a schematic diagram of an electronic device 100 according to an embodiment of the invention. As shown in fig. 1, the electronic device 100 includes an image generating circuit 110, a control circuit 120 and a display panel 130. In the present embodiment, the image generating circuit 110 may be a graphics processor (Graphics Processing Unit, GPU) for generating the image data Din, and the format of the generated image data Din conforms to the specification of the Display Port (DP) or the high-definition multimedia interface (High Definition Multimedia Interface, HDMI), but the invention is not limited thereto. The control circuit 120 includes a receiving interface 122, an image processing circuit 124, a transmitting interface 126 and a backlight control circuit 128, wherein the receiving interface 122 is used for receiving the image data Din from the image generating circuit 110 and then transmitting the image data Din to the image processing circuit 124 for image processing, and the image processing circuit 124 can adjust the brightness, color, frame rate/update rate or other formats of the received image data Din to generate output image data Dout to the transmitting interface 126 for being transmitted to the display panel 130 for display; in addition, the backlight control circuit 128 is used for generating a control signal Vc to control the brightness of the display panel 130, wherein the control signal Vc can be a pulse-width modulation (PWM) signal. In the present embodiment, the output image data Dout can be any standard panel signal, such as Low Voltage differential signal (Low Voltage DIFFERENTIAL SIGNALING, LVDS), V-by-One, embedded display port (Embedded Display Port, eDP) …, etc. The display panel 130 is a liquid crystal display panel, and the display panel 130 includes a timing controller 132, a gate driver 133, a source driver 134, a pixel array 136 and a backlight module 138, wherein the timing controller 132 receives the output image data Dout from the control circuit 120 and generates corresponding gate driving signals and source driving signals to the gate driver 133 and the source driver 134 for controlling the pixel array 136 to display an image; in addition, the backlight module 138 receives the control signal Vc to display the corresponding brightness.
The electronic device 100 shown in fig. 1 supports a display mode with a variable new rate (variable REFRESH RATE), that is, the frame rate of the output image data Dout generated by the control circuit 120 varies with the frame rate of the image data Din generated by the graphics processor 110. In one example, since the time for generating each frame by the image generating circuit 110 is not fixed, the control circuit 120 is designed to support a larger frame rate range, such as 48 Hz-144 Hz or higher, and 240Hz, so that the user can feel that the image frame has a better flow rate. However, although the control circuit 120 can support a larger frame rate, the frame rate of the image data Din outputted from the image generating circuit 110 is generally about 60Hz, so the present embodiment proposes a control method that can adjust the frame rate of the image data Din by a frequency multiplication manner to generate the output image data Dout under the condition that the frame rate of the image data Din outputted from the image generating circuit 110 is stably lower than the frame rate supported by the control circuit 120, so as to solve the problem of motion blur described in the prior art. The specific embodiments are described below.
Fig. 2 is a timing diagram of the operation of the control circuit 120 according to one embodiment of the invention. Referring to fig. 2, assuming that the frame rate of the image data Din generated by the image generating circuit 110 is 'f' (the unit may be the frame per second (fps) or the hertz (Hz)), the control circuit 120 may directly perform the frequency doubling processing on the image data Din after receiving the image data Din, that is, the frame rate of the output image data Dout is '2*f' (that is, the time difference between the two adjacent vertical synchronization signals Vsync of the output image data Dout is half of the time difference between the two adjacent vertical synchronization signals Vsync of the image data Din); or the image processing circuit 124 may directly perform frequency multiplication processing on the image data Din, i.e. the frame rate of the output image data Dout is '3*f' (i.e. the time difference between two adjacent vertical synchronization signals Vsync of the output image data Dout is one third of the time difference between two adjacent vertical synchronization signals Vsync of the image data Din); or the image processing circuit 124 may directly perform N-frequency multiplication on the image data Din, where N is any suitable positive integer, so long as the frame rate of the output image data Dout is lower than the highest frame rate supported by the control circuit 120 and the display panel 130.
In the embodiment of fig. 2, the image processing circuit 124 directly copies the image data when performing the frequency doubling operation, for example, when receiving the frame F1, the image processing circuit 124 directly transmits the content corresponding to the active area in the frame F1 to the display panel 130 twice, so that the output image data Dout includes two frames F1 '(frequency-doubled frames), wherein the content of the active area of each frame F1' (i.e. the portion displayed in the pixel array 136) is identical to the content of the active area of the frame F1; similarly, when the frame F2 is received, the image processing circuit 124 directly transmits the content corresponding to the active region in the frame F2 to the display panel 130 twice, so that the output image data Dout includes two frames F2 '(frequency-doubled frames), wherein the content of the active region of each frame F2' is identical to the content of the active region of the frame F2. In addition, taking frequency multiplication as an example, when the frame F1 is received, the image processing circuit 124 directly transmits the content of the active area of the frame F1 three times to the display panel 130, so that the output image data Dout includes three frames F1 "(frequency-multiplied frames), wherein the content of the active area of each frame F1″ is identical to the content of the active area of the frame F1; similarly, when the frame F2 is received, the image processing circuit 124 directly transmits the content of the active area of the frame F2 three times to the display panel 130, so that the output image data Dout includes three frames F3 "(frequency-doubled frames). In the control method of the present embodiment, the image data Din is directly subjected to the frequency multiplication process to generate the output image data Dout, and since the pixels in the pixel array 136 generally cannot reach the required brightness once due to the reaction speed of the liquid crystal (i.e. the pixel electrodes in the pixels cannot reach the required target voltage level directly in one period), the color/brightness of the display panel 130 can be more accurate by directly performing the frequency multiplication process on the image data Din to drive the pixel electrodes to the same target voltage level multiple times.
In addition, in one embodiment, the operation of multiplying the frequency of the image data Din to generate the output image data Dout may be performed by reducing the content of the front shoulder region (front porch) (refer to fig. 6), or by changing the frequency of the clock signal used to transmit the output image data Dout.
Fig. 3 is a timing diagram illustrating an operation of the control circuit 120 according to another embodiment of the invention, wherein fig. 3 is a frequency doubling example, but the invention is not limited thereto. Referring to fig. 3, assuming that the image data Din generated by the image generating circuit 110 sequentially includes frames F1 to F5, wherein the frame rates of the frames F1 to F5 are 48Hz, 60Hz, 48Hz, respectively, the image processing circuit 124 can directly perform the frequency doubling processing on the image data Din, that is, the output image data Dout sequentially includes the frames F1'(96Hz)、F1'(96Hz)、F2'(96Hz)、F2'(96Hz)、F3'(120Hz)、F3'(120Hz)、F4'(120Hz)、F4'(120Hz)、F5'(96Hz)、F5'(96Hz)., by the control method of the present embodiment, the output image data Dout can be dynamically generated according to the frame rate of the image data Din under the condition that the frame rate of the image data Din is not fixed
Fig. 4 is a timing diagram illustrating an operation of the control circuit 120 according to another embodiment of the invention, wherein fig. 4 is a frequency doubling example, but the invention is not limited thereto. Referring to fig. 4, assuming that the image data Din generated by the image generating circuit 110 sequentially includes frames F1 to F5, wherein the frame rates of the frames F1 to F5 are 48Hz, 60Hz, 48Hz, respectively, the image processing circuit 124 performs a frequency doubling process on the image data Din and performs an operation of inserting a black frame, that is, the output image data Dout sequentially includes black frames (96 Hz), F1' (96 Hz), black frames (96 Hz), F2' (96 Hz), black frames (120 Hz), F3' (120 Hz), black frames (120 Hz), F4' (120 Hz), black frames (96 Hz), and F5' (96 Hz). By the control method of the embodiment, under the condition that the frame rate of the image data Din is not fixed, the output image data Dout can be dynamically generated according to the frame rate of the image data Din, and the operation of inserting a black picture is carried out on repeated frames so as to reduce the dynamic blurring caused by persistence of vision.
It should be noted that the black frame shown in fig. 4 is not necessarily a full black frame, as long as the brightness of the black frame is far lower than the brightness of the frames F1 to F5.
In one embodiment, if the image processing circuit 124 performs N-frequency multiplication processing on a frame and performs an operation of inserting a black frame to generate N frequency-multiplied frames, where N is any positive integer greater than one, the first frequency-multiplied frame of the N frequency-multiplied frames is a black frame, and the content of the active region of the last frequency-multiplied frame of the N frequency-multiplied frames is the same as the content of the active region of the frame.
Fig. 5 is a timing diagram illustrating an operation of the control circuit 120 according to another embodiment of the invention, wherein fig. 5 is a frequency doubling example, but the invention is not limited thereto. Referring to fig. 5, assuming that the image data Din generated by the image generating circuit 110 sequentially includes frames F1 to F5, wherein the frame rates of the frames F1 to F5 are 48Hz, 60Hz, and 48Hz, respectively, the image processing circuit 124 can directly perform the frequency doubling processing on the image data Din, that is, the output image data Dout sequentially includes the frame F1'(96Hz)、F1'(96Hz)、F2'(96Hz)、F2'(96Hz)、F3'(120Hz)、F3'(120Hz)、F4'(120Hz)、F4'(120Hz)、F5'(96Hz)、F5'(96Hz)., the backlight control module 128 in the control circuit 120 generates the control signal Vc to adopt the first backlight mode or the second backlight mode for different frames, wherein the first backlight mode is to completely turn off the backlight module 138 or control the backlight module 138 to generate very low brightness, and the second backlight mode is to generate normal brightness. Specifically, when the display panel 130 displays the first appearing frame F1', the backlight control module 128 generates the control signal Vc to make the backlight module 138 operate in the first backlight mode, i.e. the first appearing frame F1' can be regarded as a black frame; when the display panel 130 displays the second frame F1', the backlight control module 128 generates the control signal Vc to enable the backlight module 138 to operate in the second backlight mode, i.e. the display panel 130 normally displays the second frame F1'. Based on the same operation, when the display panel 130 displays the first appearing frames F2', F3', F4', F5', the backlight control module 128 generates the control signal Vc to make the backlight module 138 operate in the first backlight mode, i.e. the first appearing frames F2', F3', F4', F5' can be regarded as black; when the display panel 130 displays the second appearing frames F2', F3', F4', F5', the backlight control module 128 generates the control signal Vc to enable the backlight module 138 to operate in the second backlight mode, i.e. the display panel 130 normally displays the second appearing frames F2', F3', F4', F5'.
In one embodiment, if the image processing circuit 124 performs N times the frequency of a frame and performs an operation of inserting a black frame to generate N times the frequency of the frame, where N is any positive integer greater than one, when the transmitting interface 126 transmits a first time-multiplied frame of the N times the frequency of the frame to the display panel 130, the backlight control module 128 generates the control signal Vc to control the backlight module 137 to operate in the first backlight mode; and when the transmission interface 126 transmits the last doubled frame of the N doubled frames to the display panel 130, the backlight control module 128 generates a control signal Vc to control the backlight module 138 to operate in the second backlight mode.
In one embodiment, the backlight control method shown in fig. 5 may be a stroboscopic backlight (stroboscopic backlight) control method, specifically, referring to fig. 6, each complete frame includes a vertical synchronization signal Vsync, a back shoulder (back porch, BP) area, an active area (i.e. the content displayed on the pixel array 136), and a front shoulder (front porch, FP) area in sequence, and when the display panel 130 displays the first appearing frame F1', the backlight control module 128 generates a control signal Vc to make the brightness of the backlight module 138 be 0 or very low so that the first appearing frame F1' may be regarded as a black screen; then, when the display panel 130 displays the second frame F1', the backlight control module 128 generates the control signal Vc such that the backlight module 138 controls the backlight module 138 to briefly generate the brightness for the display panel 130 to display the second frame F1' after the pixel array 136 of the display panel 130 completely receives the driving signal of the second frame F1'.
Fig. 7 is a timing diagram illustrating an operation of the control circuit 120 according to another embodiment of the invention, wherein fig. 7 is a frequency doubling example, but the invention is not limited thereto. Referring to fig. 7, first, before transmitting the frame F1, the image generating circuit 110 notifies the control circuit 120 of the frame rate of the frame F1 to be transmitted next, for example, 48Hz, for the control circuit 120 to set the current frame rate (i.e., 96 Hz), and after a delay time of internal operation, the image processing circuit 124 in the control circuit 120 sequentially outputs two frames F1' with 96Hz frame rate. Since the frame rate of the frame F2 is the same as the frame rate of the frame F1, the image generating circuit 110 does not inform the control circuit 120 of the frame rate of the frame F2 to be transmitted next, and the image processing circuit 124 continues to use the previous frame rate (i.e., 96 Hz) to sequentially output two frames F2' with 96Hz frame rate. Then, before transmitting the frame F3, the image generating circuit 110 notifies the control circuit 120 of the frame rate of the frame F3 to be transmitted next, for example, 60Hz, for the control circuit 120 to set the current frame rate (i.e., 120 Hz), and after a delay time of an internal operation, the image processing circuit 124 in the control circuit 120 sequentially outputs two frames F3' with the frame rate of 120 Hz. Since the frame rate of the frame F4 is the same as the frame rate of the frame F3, the image generating circuit 110 does not inform the control circuit 120 of the frame rate of the frame F4 to be transmitted next, and the image processing circuit 124 continues to use the previous frame rate (i.e., 120 Hz) to sequentially output two frames F4' with the frame rate of 120 Hz. Then, before transmitting the frame F5, the image generating circuit 110 notifies the control circuit 120 of the frame rate of the frame F5 to be transmitted next, for example, 48Hz, for the control circuit 120 to set the current frame rate (i.e., 96 Hz), and after a delay time of an internal operation, the image processing circuit 124 in the control circuit 120 sequentially outputs two frames F5' with the frame rate of 120 Hz.
In the embodiment of fig. 7, the image generation circuit 110 only notifies the control circuit 120 when there is a change in the frame rate of the generated frame, however, this feature is not a limitation of the present invention. In other embodiments, the image generation circuit 110 may inform the control circuit 120 of the frame rate of the next frame to be transmitted before transmitting each frame, and these design variations are within the scope of the present invention.
It should be noted that the embodiment shown in fig. 7 may also apply the method of inserting the black frame shown in fig. 4 and 5, i.e. the first appearing frame F1 'to F5' in the output image data Dout shown in fig. 7 is replaced by the black frame shown in fig. 4, or as shown in fig. 5, when the display panel 130 displays the first appearing frame F1 'to F5', the backlight control module 128 generates the control signal Vc to make the backlight module 138 operate in the first backlight mode, i.e. the first appearing frame F1 'to F5' can be regarded as the black frame; when the display panel 130 displays the second frame F1 'to F5', the backlight control module 128 generates the control signal Vc to enable the backlight module 138 to operate in the second backlight mode, i.e. the display panel 130 normally displays the second frame F1 'to F5'.
Fig. 8 is a timing diagram illustrating an operation of the control circuit 120 according to another embodiment of the invention, wherein fig. 8 is a frequency doubling example, but the invention is not limited thereto. Referring to fig. 8, first, the image generating circuit 110 transmits the frame F1 to the control circuit 120, the image processing circuit 124 temporarily stores the frame F1 in an internal buffer, and waits until the frame F1 is transmitted (e.g. the next vertical synchronization signal Vsync is received), the image processing circuit 124 starts measuring the frame rate (e.g. 48 Hz) of the frame F1 for setting the current frame rate (i.e. 96 Hz), and after a delay time of an internal operation, the image processing circuit 124 in the control circuit 120 sequentially outputs two frames F1' with 96 Hz. Then, the image generating circuit 110 transmits the frame F2 to the control circuit 120, and the image processing circuit 124 temporarily stores the frame F2 in an internal buffer, and waits until the frame F2 is completely transmitted, the image processing circuit 124 starts measuring the frame rate (e.g., 48 Hz) of the frame F2 for setting the current frame rate (i.e., 96 Hz), and after a delay time of an internal operation, the image processing circuit 124 in the control circuit 120 sequentially outputs two frames F2' with the frame rate of 96 Hz. Similarly, the image generating circuit 110 transmits the frame F3 to the control circuit 120, and the image processing circuit 124 temporarily stores the frame F3 in an internal buffer, and waits until the frame F3 is transmitted, the image processing circuit 124 starts measuring the frame rate (e.g., 60 Hz) of the frame F3 for setting the current frame rate (i.e., 120 Hz), and after a delay time of an internal operation, the image processing circuit 124 in the control circuit 120 sequentially outputs two frames F3' with the frame rate of 120 Hz. As described above, based on the similar operation, the image processing circuit 124 sequentially outputs two frames F4 having a frame rate of 120Hz after the content of the frame F4 is completely received, and sequentially outputs two frames F5' having a frame rate of 96Hz after the content of the frame F5 is completely received.
It should be noted that the embodiment shown in fig. 8 can also be applied to the method of inserting the black frame shown in fig. 4 and 5, i.e. the first occurrence of the frames F1 'to F5' in the output image data Dout shown in fig. 8 is replaced by the black frame shown in fig. 4, or as shown in fig. 5, when the display panel 130 displays the first occurrence of the frames F1 'to F5', the backlight control module 128 generates the control signal Vc to make the backlight module 138 operate in the first backlight mode, i.e. the first occurrence of the frames F1 'to F5' can be regarded as the black frame; when the display panel 130 displays the second frame F1 'to F5', the backlight control module 128 generates the control signal Vc to enable the backlight module 138 to operate in the second backlight mode, i.e. the display panel 130 normally displays the second frame F1 'to F5'.
It should be noted that, in the above embodiment, it is assumed that the frame rate of the image data Din outputted by the image generating circuit 110 is stably lower than the frame rate supported by the control circuit 120, so that the frame rate of the image data Din is adjusted by frequency multiplication to generate the output image data Dout, so as to solve the problem of motion blur described in the prior art. However, if the image processing circuit 124 determines that the currently received image data Din does not meet the frequency doubling criteria, for example, the frame rate of a portion of the frames in the image data Din is close to or higher than half the frame rate supported by the control circuit 120, the image processing circuit 124 may stop the frequency doubling operation, i.e. the frame rate of the output image data Dout is the same as the frame rate of the image data Din.
Briefly summarized, in the control circuit and the control method applied to the display panel, the dynamic smear problem of the liquid crystal display panel on display can be effectively reduced by performing frequency multiplication operation on the image data according to the frame rate of the image data to generate output image data and inserting a black picture, so as to improve the display quality.
The foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Reference numerals illustrate:
100 electronic device
110 Image generating circuit
120 Control circuit
122 Receive interface
124 Image processing circuit
126 Transfer interface
128 Backlight control module
130 Display panel
132 Timing controller
133 Door actuator
134 Source driver
136 Pixel array
138 Backlight module
BP posterior shoulder region
FP anterior shoulder area
Din, image data
Dout, output image data
F1 to F5 frames
F1 '-F5' frame
F1 'to F5': frame
Vc control signal
Vsync vertical synchronization signal
Claims (8)
1. A control circuit for a display panel, comprising:
a receiving interface for receiving image data, wherein the image data has a non-fixed frame rate;
The image processing circuit is coupled to the receiving interface and is used for receiving the image data from the receiving interface and performing frequency multiplication operation on the image data according to the frame rate of the image data to generate output image data, wherein the frame rate of the output image data is positive integer multiple of the image data; and
The transmission interface is coupled with the image processing circuit and used for receiving the output image data from the image processing circuit and transmitting the output image data to the display panel;
the image data comprises a first frame, and the image processing circuit performs frequency multiplication operation on the first frame to generate N frequency-multiplied first frames, wherein N is a positive integer greater than one;
The first frame after frequency multiplication in the first frame after frequency multiplication is a black picture, and the content of the active area of the last first frame after frequency multiplication in the first frame after frequency multiplication is the same as the content of the active area of the first frame.
2. The control circuit of claim 1, wherein the content of the active region of each frequency doubled first frame is the same as the content of the active region of the first frame.
3. The control circuit of claim 2, wherein the image data comprises a second frame having a frame rate different from a frame rate of the first frame, the image processing circuit performing a frequency doubling operation on the second frame to generate N frequency doubled second frames, wherein a content of an active region of each frequency doubled second frame is identical to a content of an active region of the second frame.
4. The control circuit of claim 1, further comprising:
the backlight control module is used for generating a control signal to control the brightness of the backlight module of the display panel;
When the transmission interface transmits a first frequency multiplied first frame of the N frequency multiplied first frames to the display panel, the backlight control module generates the control signal to control the backlight module to operate in a first backlight mode; and when the transmission interface transmits the last frequency multiplied first frame of the N frequency multiplied first frames to the display panel, the backlight control module generates the control signal to control the backlight module to operate in a second backlight mode different from the first backlight mode, wherein the brightness of the first backlight mode is lower than that of the second backlight mode.
5. The control circuit of claim 1, wherein the receiving interface receives a notification to obtain a frame rate of the first frame before starting to receive the first frame, and the image processing circuit multiplies the first frame according to the frame rate of the first frame to generate the N multiplied first frames, and sequentially transmits the N multiplied first frames to the display panel.
6. The control circuit of claim 5, wherein the image processing circuit starts generating a first one of the N multiplied first frames before the entire content of the first frame has been received, and transmits the first multiplied first frame to the display panel.
7. The control circuit of claim 1, wherein the image processing circuit measures a frame rate of the first frame after receiving the entire content of the first frame, performs a frequency doubling operation on the first frame according to the frame rate of the first frame to generate the N frequency-doubled first frames, and sequentially transmits the N frequency-doubled first frames to the display panel.
8. A control method applied to a display panel, comprising:
Receiving image data, wherein the image data has a non-fixed frame rate;
performing frequency multiplication operation on the image data according to the frame rate of the image data to generate output image data, wherein the frame rate of the output image data is a positive integer multiple of the image data; and
Transmitting the output image data to the display panel;
the image data comprises a first frame, and N first frames after frequency multiplication are generated after frequency multiplication operation is carried out, wherein N is a positive integer greater than one;
The first frame after frequency multiplication in the first frame after frequency multiplication is a black picture, and the content of the active area of the last first frame after frequency multiplication in the first frame after frequency multiplication is the same as the content of the active area of the first frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110191282.8A CN114974149B (en) | 2021-02-19 | 2021-02-19 | Control circuit and control method applied to display panel |
Applications Claiming Priority (1)
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| JP2004159191A (en) * | 2002-11-07 | 2004-06-03 | Seiko Epson Corp | Conversion of frame rate in accordance with image data |
| CN101241676A (en) * | 2007-02-07 | 2008-08-13 | 奇美电子股份有限公司 | Method for improving video data display with dual-boundary problem |
| CN104715728A (en) * | 2013-12-13 | 2015-06-17 | 三星显示有限公司 | Display device, controller, and related operating method |
| CN208903641U (en) * | 2018-09-26 | 2019-05-24 | 中强光电股份有限公司 | Projection arrangement |
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| JP4762343B2 (en) * | 2009-12-28 | 2011-08-31 | 株式会社東芝 | Image quality adjusting apparatus and image quality adjusting method |
| US20150002734A1 (en) * | 2013-07-01 | 2015-01-01 | Motorola Mobility Llc | Electronic Device with Modulated Light Flash Operation for Rolling Shutter Image Sensor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004159191A (en) * | 2002-11-07 | 2004-06-03 | Seiko Epson Corp | Conversion of frame rate in accordance with image data |
| CN101241676A (en) * | 2007-02-07 | 2008-08-13 | 奇美电子股份有限公司 | Method for improving video data display with dual-boundary problem |
| CN104715728A (en) * | 2013-12-13 | 2015-06-17 | 三星显示有限公司 | Display device, controller, and related operating method |
| CN208903641U (en) * | 2018-09-26 | 2019-05-24 | 中强光电股份有限公司 | Projection arrangement |
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