CN113452333B - Differential amplifier and laser drive circuit - Google Patents
Differential amplifier and laser drive circuit Download PDFInfo
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- CN113452333B CN113452333B CN202111023749.4A CN202111023749A CN113452333B CN 113452333 B CN113452333 B CN 113452333B CN 202111023749 A CN202111023749 A CN 202111023749A CN 113452333 B CN113452333 B CN 113452333B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/4508—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using bipolar transistors as the active amplifying circuit
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
- H01S5/042—Electrical excitation ; Circuits therefor
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45542—Indexing scheme relating to differential amplifiers the IC comprising bias stabilisation means, e.g. DC level stabilisation, and temperature coefficient dependent control, e.g. by DC level shifting
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Abstract
The application provides a differential amplifier and a drive circuit of a laser, wherein the differential amplifier comprises a differential circuit and a control circuit, the current output end of a differential pair transistor in the differential circuit is connected with an MOS (metal oxide semiconductor) resistor as a degeneration resistor, the control circuit generates a grid voltage for controlling the resistance value of the MOS resistor according to the size of tail current and the size of output current of a first transistor in the differential pair transistor, the grid voltage can be adjusted and changed along with the change of the tail current and the output current of the first transistor in a self-adaptive manner, the resistance value of the MOS resistor in an MOS resistor unit can be accurately adjusted, so that under the condition of different tail currents and different input voltages, the relation between the output current of the differential amplifier and the tail current is accurately controlled to be a preset relation, and the linearity of the output current is ensured.
Description
Technical Field
The invention relates to the technical field of amplifier circuit design, in particular to a differential amplifier and a laser driving circuit.
Background
The driving circuit of the laser is generally formed by a differential amplifier, which amplifies and outputs an input differential signal to provide a driving voltage for the laser. For the triode differential circuit amplifier, the linearity of the output current is affected by increasing the input voltage range of the triode differential circuit amplifier, but the differential amplifier is required to have a larger input voltage range in many application scenes. In order to increase the input voltage range and not affect the linearity of the output current, a resistor called a degeneration resistor may be used in series with the emitter of the input differential pair transistor. The size of the degeneration resistor affects not only the linearity of the output current of the differential amplifier, but also the output current range, and thus the driving efficiency of the laser driving circuit.
Therefore, the size of the degeneration resistance is critical to the performance of the differential amplifier, i.e., wide input voltage range and high output current linearity. At present, most of differential amplifiers use MOSFETs as adjustable resistors (hereinafter referred to as MOS resistors), and the gate voltage of the MOS resistor is adjusted to adjust the resistance of the MOS resistor, so that the differential amplifier can ensure the linearity of the output current under different input voltages.
For a laser driving circuit capable of adjusting output current, tail current of a differential amplifier needs to be adjusted in a large range, and in order to ensure that the differential amplifier still has high linearity under different tail currents, the precision of grid voltage of an MOS resistor is very high. However, the gate voltage obtained by the conventional VDAC (analog-to-digital converter) has a precision that cannot meet the requirement.
Disclosure of Invention
Based on this, the application provides a differential amplifier and a driving circuit of a laser to solve the problem that in the prior art, the control accuracy of an MOS resistor in the differential amplifier is not high.
A differential amplifier, comprising:
the differential amplification circuit comprises a differential pair transistor consisting of a first transistor and a second transistor, an MOS (metal oxide semiconductor) resistance unit and a tail current unit, wherein the MOS resistance unit is connected between current output ends of the first transistor and the second transistor and is grounded through the tail current unit;
the control circuit is configured to generate a gate voltage for controlling the resistance of the MOS resistor in the MOS resistor unit according to the magnitude of the output tail current of the tail current unit and the magnitude of the output current of the first transistor, so as to control the magnitude relation between the output current of the first transistor and the output tail current of the tail current unit to be a preset relation.
In some embodiments, the differential amplifier further comprises a first differential signal input unit and a second differential signal input unit;
the first differential signal input unit comprises a first direct current power supply and a first alternating current power supply which are sequentially connected between the control end and the grounding end of the first transistor, and the polarity of the first direct current power supply is the same as that of the first alternating current power supply;
the second differential signal input unit comprises a second direct current power supply and a second alternating current power supply which are sequentially connected between the control end and the grounding end of the second transistor, and the polarity of the second direct current power supply is opposite to that of the second alternating current power supply;
the first direct current power supply and the second direct current power supply have the same polarity and the same amplitude, and the second alternating current power supply and the first alternating current power supply have the same amplitude.
In some embodiments, the MOS resistance unit comprises a first MOS resistance, and the tail current unit comprises a first tail current source and a second tail current source;
the control end of the first MOS resistor receives the grid voltage;
the first end of the first MOS resistor is connected with the current output end of the first transistor and is grounded through the first tail current source;
the second end of the first MOS resistor is connected with the current output end of the second transistor and is grounded through the second tail current source, and the output current of the first tail current source is used as the output tail current of the tail current unit.
In some embodiments, the MOS resistance unit includes a second MOS resistance and a third MOS resistance, and the tail current unit includes a third tail current source;
the grid electrodes of the second MOS resistor and the third MOS resistor receive the grid voltage;
the first end of the second MOS resistor is grounded through the third tail current source, and the second end of the second MOS resistor is connected with the current output end of the first transistor;
the first end of the third MOS resistor is grounded through the third tail current source, and the second end of the third MOS resistor is connected with the current output end of the second transistor;
and the output current of the third tail current source is the output tail current of the tail current unit.
In some embodiments, the control circuit includes a reference circuit, an error amplification circuit, and a replica circuit of the differential amplification circuit;
the reference circuit sets a reference current representing the magnitude of the copying output tail current source according to the magnitude of the copying tail current output by a copying tail current unit in the copying circuit and the preset relationship, wherein the magnitude relationship between the reference current and the copying output tail current is the preset relationship;
the error amplifying circuit is used for amplifying an error value between the reference signal and the output current of the copying first transistor in the copying circuit so as to output the grid voltage, and the grid voltage is used as the MOS resistance grid voltage of the copying MOS resistance unit in the copying circuit.
In some embodiments, the replica circuit has the same structure as the differential amplifier circuit, and includes a replica first transistor corresponding to the first transistor, a replica second transistor provided corresponding to the second transistor, a replica MOS resistance unit corresponding to the MOS resistance unit, and a replica tail current unit corresponding to the tail current unit;
the output current of the first copying transistor is the current of the output current of the first copying transistor, which is reduced according to a preset proportion;
the output current of the second duplicate transistor is the current of the output current of the second transistor reduced according to the preset proportion;
the size of the MOS resistor in the copying MOS resistor unit is the size of the MOS resistor in the MOS resistor unit reduced according to the preset proportion;
and the copied output tail current of the copied tail current unit is the current of the output tail current of the tail current unit reduced according to the preset proportion.
In some embodiments, the differential amplification circuit further comprises a first resistor and a second resistor, the replica circuit further comprises a replica first resistor corresponding to the first resistor and a replica second resistor corresponding to the second resistor;
the first end of the first resistor is connected with a power supply, the second end of the first resistor is connected with the current input end of the first transistor, the control end of the first transistor is a first differential input end of the differential amplifier, and the current output end of the first resistor is a first differential output end of the differential amplifier;
the first end of the second resistor is connected with the power supply, the second end of the second resistor is connected with the current input end of the second transistor, the control end of the first transistor is a second differential input end of the differential amplifier, and the current output end of the first transistor is a second differential output end of the differential amplifier;
the resistance value of the first copied resistor is the resistance value of the first resistor reduced according to the preset proportion, and the resistance value of the second copied resistor is the resistance value of the second resistor reduced according to the preset proportion.
In some embodiments, the reference circuit comprises a third resistor and a reference current source;
the first end of the third resistor is connected with the first end of the first replica resistor, and the second end of the third resistor is grounded through the reference current source;
the resistance value of the third resistor is the same as that of the copied first resistor, and the output current of the reference current source is the reference current;
the second end of the third resistor outputs the representation signal of the reference current to the first input end of the error amplifying circuit, and the second end of the copied first resistor outputs the representation signal of the output current of the copied first transistor to the second input end of the error amplifying circuit.
In some embodiments, the error amplification circuit includes an error amplifier and a capacitor;
the inverting input end of the error amplifier is a first input end of the error amplifying circuit and is used for receiving the representation signal of the reference current, and the non-inverting input end of the error amplifier is a second input end of the error amplifying circuit and is used for receiving the representation signal of the output current of the first copying transistor;
the capacitor is connected between the output end of the error amplifier and a grounding end, and the voltage on the capacitor is the grid voltage.
A driver circuit for a laser comprising a differential amplifier as claimed in any preceding claim.
In the drive circuit of differential amplifier and laser that this application provided, the current output end of the differential pair transistor in the differential circuit is connected with MOS resistance as degeneration resistance, control circuit produces the grid voltage who is used for controlling MOS resistance value according to the size of tail current and the output current's of the first transistor in the differential pair transistor size, grid voltage can be along with tail current and the output current's of first transistor change and the adjustment change of self-adaptation, MOS resistance value in the regulation MOS resistance unit that can be accurate to under different tail current circumstances and different input voltage circumstances, the relation between the output current of accurate control differential amplifier and the tail current is predetermined relation, output current's linearity has been guaranteed.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of a differential amplifier according to a first embodiment of the present application;
FIG. 2 is a schematic diagram of a differential amplifier according to a second embodiment of the present application;
FIG. 3 is a schematic diagram of a differential amplifier according to a third embodiment of the present application;
fig. 4 is a schematic diagram of a control circuit in a differential amplifier according to the present application.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are set forth in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, a first resistance may be referred to as a second resistance, and similarly, a second resistance may be referred to as a first resistance, without departing from the scope of the present application. The first resistance and the second resistance are both resistances, but they are not the same resistance.
It is to be understood that "connection" in the following embodiments is to be understood as "electrical connection", "communication connection", and the like if the connected circuits, modules, units, and the like have communication of electrical signals or data with each other.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.
Fig. 1 is a schematic circuit diagram of a differential amplifier provided according to a first embodiment of the present invention, and the differential amplifier mainly includes a differential amplifier circuit and a control circuit 3, where the differential amplifier circuit further includes a differential pair transistor formed by a first transistor Q1 and a second transistor Q2, a MOS resistor unit 1 formed by a MOS resistor, and a tail current unit 2 formed by a tail current source. The MOS resistor unit 1 is connected between the current output terminals of the first transistor Q1 and the second transistor Q2, and is grounded through the tail current unit 2. The control circuit 3 generates a gate voltage Vg for controlling the resistance of the MOS resistor in the MOS resistor unit 1 according to the magnitude of the output tail current Iail of the tail current unit 2 and the magnitude of the output current I1 of the first transistor Q1, so as to control the magnitude relationship between the output current I1 of the first transistor Q1 and the output tail current Iail output by the tail current unit 2 to be a preset relationship. The MOS resistor is actually a MOSFET (metal oxide field effect transistor), and the MOSFET operates in a linear region through the gate voltage control of the MOSFET, so that the MOSFET can be equivalent to an adjustable resistor with a resistance value adjusted by the gate voltage, and the resistor is referred to as a MOS resistor in this application. In the present application, the MOS resistor in the MOS resistor unit 1 serves as a degeneration resistor of the differential amplifier, and therefore, the relationship between the output current I1 of the first transistor Q1 and the output tail current Iail is controlled to be a preset relationship by adjusting the resistance value of the MOS resistor, where the preset relationship refers to a preset desired relationship, for example, the desired I1 is a times the output tail current Iail, where a is a value between 0 and 1 (including 0 and 1).
The differential amplifier circuit in this embodiment further includes a first resistor R1 and a second resistor R2, wherein a first terminal of the first resistor R1 is connected (coupled) to the power supply VDD terminal of the differential amplifier, a second terminal is connected to the current input terminal of the first transistor Q1, a first terminal of the second resistor R2 is connected (coupled) to the power supply VDD terminal of the differential amplifier, and a second terminal is connected to the current input terminal of the second transistor Q2. In this embodiment, the differential amplifier circuit further includes a bias transistor Qbias, a current output terminal of which is connected to the first terminal of the first resistor and the first terminal of the second resistor, respectively, and a current input terminal of which is connected to the control terminal of the first resistor and to the power supply VDD. The bias transistor Qbias is a bipolar transistor in this embodiment for providing a bias current to the first transistor Q1 and the second transistor Q2. In the embodiment, the first transistor Q1 and the second transistor Q2 are symmetrically disposed, the first resistor R1 and the second resistor R2 are also symmetrically disposed, the resistance of the first resistor R1 is the same as that of the second resistor R2, and the structures and parameters of the first transistor Q1 and the second transistor Q2 are the same.
The control terminal of the first transistor Q1 is used as a first differential input terminal of the differential amplifier, the current input terminal of the first transistor Q1 is used as a first differential output terminal of the differential amplifier, the control terminal of the second transistor Q2 is used as a second differential input terminal of the differential amplifier, the current input terminal of the second transistor Q2 is used as a second differential output terminal of the differential amplifier, and the voltage between the first differential output terminal and the second differential output terminal is the differential output voltage Vo. In addition, the differential circuit in the present embodiment further includes a first differential signal input unit and a second differential signal input unit to provide a first differential input signal and a second differential input signal to the control terminal of the first transistor Q1 and the control terminal of the second transistor Q2, respectively. The first differential signal input unit includes a first DC power supply DC1 and a first AC power supply AC1 sequentially connected between the control terminal of the first transistor Q1 and the ground terminal, wherein the first DC power supply DC1 and the first AC power supply AC1 have the same polarity, that is, the control terminal of the first transistor Q1 receives a first differential signal, which is the sum of the DC voltage output by the first DC power supply DC1 and the AC voltage output by the first AC power supply AC 1. The second differential signal input unit includes a second DC power supply DC2 and a second AC power supply AC2 sequentially connected between the control terminal of the second transistor Q2 and the ground terminal, wherein the polarity of the second DC power supply DC2 is opposite to that of the second AC power supply AC2, and is the same as the polarity of the first DC voltage DC1, that is, the second differential signal received by the control terminal of the second transistor Q2 is the difference between the DC voltage output by the second DC power supply DC2 and the AC voltage output by the second AC power supply AC 2. In addition, the amplitude of the alternating current voltage output by the first alternating current power supply AC1 is equal to that of the alternating current voltage output by the second alternating current power supply AC2, and the amplitude of the first direct current power supply DC1 is equal to that of the second direct current power supply DC 2. In other embodiments, the first differential signal input unit and the second differential signal input unit may share the same DC power source, for example, the first DC power source DC1 is shared by both differential signal input units, and the second DC power source DC2 in the second differential signal input unit needs to be removed, and the second AC power source AC2 is also connected to the first DC power source DC 1.
In the present embodiment, the first transistor Q1 and the second transistor Q2 are Bipolar Junction Transistors (BJTs), such as NPN bipolar junction transistors. The current output terminals of the first transistor Q1 and the second transistor Q2 are emitters, the current input terminals are collectors, and the control terminals are bases. In other embodiments, the first transistor Q1 and the second transistor Q2 may be MOSFETs, such as NPN MOSFETs, and the current output terminal of the first transistor Q1 and the second transistor Q2 is a source, the current input terminal is a drain, and the control terminal is a gate.
In this embodiment, the preset relationship refers to that the output current I1 is a multiple of the output tail current Iail, and the specific implementation steps of the control circuit 3 generating the gate voltage Vg for controlling the MOS resistor resistance in the MOS resistor unit 1 according to the magnitude of the output tail current Iail of the tail current unit 2 and the magnitude of the output current I1 of the first transistor Q1 include: generating a first proportional signal V1 of the output tail current Iail according to the magnitude of the tail current Iail and the value of a, where V1= k a Iail, and acquiring a second proportional signal V2 for characterizing the current I1 and proportional to the current I1, where V2= k I1, then amplifying according to an error value between the first proportional signal V1 and the second proportional signal V2 to obtain a gate voltage Vg, controlling the MOS resistor resistance in the MOS resistor unit 1 through the gate voltage Vg, and finally controlling the magnitude of the first proportional signal V2 to be equal to the magnitude of the first proportional signal V1, i.e. controlling the output tail current Iail of the output current I1 by a times is achieved, where a may have a value range of [20%,80% ]. It should be noted that V1= k × a × Iail indicates that a tail current characterizing parameter k times the output tail current Iail may be obtained first, and then the first comparison signal is obtained according to the tail current characterizing parameter, where if the tail current characterizing parameter is a subsequent copied tail current Iail', the coefficient k is a ratio of the tail current characterizing parameter to the output tail current.
In the differential amplifier provided by the application, the control circuit generates a gate voltage for controlling the resistance value of the MOS resistor in the MOS resistor unit according to the magnitude of the output tail current and the magnitude of the output current of the first transistor. The gate voltage can output self-adaptive adjustment changes along with changes of the tail current and the output current of the first transistor, and the MOS resistor resistance value in the MOS resistor unit can be accurately adjusted, so that the relation between the output current of the first transistor and the output tail current is accurately controlled to be a preset relation under different tail currents and different input voltages, and the linearity of the output current is ensured.
Referring to fig. 2, which is a schematic structural diagram of a differential amplifier according to a second embodiment of the present application, a specific configuration of the MOS resistor unit 1 and the tail current unit 2 is shown in the second embodiment. The MOS resistor unit 1 includes a first MOS resistor M1, and the tail current unit 2 includes a first tail current source and a second tail current source, where the first tail current source outputs a first output tail current Iail1, and the second tail current source outputs a second output tail current Iail2, where the first output tail current source and the second output tail current source have the same structure and parameters. The control terminal (gate terminal) of the first MOS resistor M1 receives the gate voltage Vg, and the first terminal (source terminal) of the first MOS resistor M1 is connected to the current output terminal of the first transistor Q1 and grounded through the first output tail current source. A second terminal (drain terminal) of the first MOS resistor M2 is connected to the current output terminal of the second transistor Q2 and is grounded via a second tail current source, wherein the first output tail current Iail serves as the tail current output by the tail current unit 2.
Referring to fig. 3, which is a schematic structural diagram of a differential amplifier according to a third embodiment of the present application, another specific configuration of the MOS resistor unit 1 and the tail current unit 2 is shown in the third embodiment. The MOS resistor unit 1 comprises a second MOS resistor M2 and a third MOS resistor M3, and the tail current unit 2 comprises a third tail current source. The gate terminals of the second MOS resistor M2 and the third MOS resistor M3 both receive the gate voltage Vg, the first terminal (source terminal) of the second MOS resistor M2 is grounded through a third tail current source, the second terminal (drain terminal) is connected to the current output terminal of the first transistor Q1, the first terminal (source terminal) of the third MOS resistor M3 is grounded through the third tail current source, and the second terminal (drain terminal) is connected to the current output terminal of the second transistor Q2. In this embodiment, the output tail current of the third tail current source is the output tail current Iail output by the tail current unit 2.
As shown in fig. 1 to 3, ideally, when the base voltage of the first transistor Q1 is high, the output current I1 of the first transistor Q2 is equal to the output tail current Iail, and the output current I2 of the second transistor Q2 is equal to 0. However, in practical operation of the conventional differential amplifier, when the base voltage of the first transistor Q1 is high, the second transistor Q2 is difficult to turn off completely (the current I2 cannot be reduced to 0 absolutely) for different output tail currents Iail, i.e. the current I1 and the current I2 are not completely equal to the ratio of the output tail currents Iail to 0, and the linearity of the output current of the differential amplifier is difficult to guarantee for different output tail currents Iail. In addition, since the resistance of the MOS resistor varies nonlinearly with factors such as bias conditions, process variations, and temperature, fig. 4 provides a schematic diagram of a specific implementation circuit of the control circuit in the differential amplifier according to the present application in order to further ensure and improve the linearity of the output current of the differential amplifier under different tail currents and input voltage ranges.
Referring to fig. 4, the control circuit in fig. 1 to 3 may further include a replica circuit 31 of a differential amplification circuit, a reference circuit 32, and an error amplification circuit 33. The replica circuit 31 has the same structure as that of the differential amplifier provided according to any embodiment of the present application (for example, in the differential amplifier corresponding to fig. 1 to fig. 3), and the replica circuit 31 is scaled according to parameters of corresponding components in the differential amplifier circuit, for example, in order to reduce power consumption of the control circuit 3, the replica circuit 31 can be obtained after reducing the current of each component in the differential amplifier circuit and the size of the MOS resistor according to a preset scale. Therefore, according to the structure of the differential amplifier circuit in fig. 1 to 3, in the present embodiment, the replica circuit 31 includes a replica first transistor Q1 'corresponding to the first transistor Q1, a replica second transistor Q2' provided corresponding to the second transistor Q2, a replica MOS resistance unit 1 'corresponding to the MOS resistance unit 1, and a replica tail current unit 2' corresponding to the tail current unit 2. The output current of the replica first transistor Q1 'is the current of the output current of the first transistor Q1 reduced by the preset proportion, the output current of the replica second transistor Q2' is the current of the output current of the second transistor Q2 reduced by the preset proportion, the size of the MOS resistor in the replica MOS resistor unit 1 'is the size of the MOS resistor in the MOS resistor unit 1 reduced by the preset proportion, and the tail current output by the replica tail current unit 2' is the current of the output current of the tail current unit 2 reduced by the preset proportion.
In addition, in the present embodiment, the replica circuit further includes a replica first resistor R1 'corresponding to the first resistor R1 in the differential circuit, and a replica second resistor R2' corresponding to the second resistor R2 in the differential circuit, wherein the resistance of the replica first resistor R1 'is the reduced resistance of the first resistor R1 according to the predetermined ratio, and the resistance of the replica second resistor R2' is the reduced resistance of the second resistor R2 according to the predetermined ratio. Furthermore, the replica circuit 31 further includes a replica bias tube Qbias 'of the bias tube Qbias in the differential circuit, and similarly, the output current of the replica bias tube Qbias' is the current of the bias tube Qbias reduced by the predetermined ratio.
The reference circuit 32 sets a reference current Iref representing the magnitude of the replica tail current source Iail 'according to the magnitude of the replica tail current Iail' output by the replica tail current unit 2 'and the preset relationship, where the magnitude relationship between the reference current Iref and the replica tail current Iail' is the preset relationship, i.e., Iref = a Iail ', and Iail' is a current reduced by Iail according to a preset ratio, and if the preset ratio is k, the reference current Iref = k a Iail, and Iref corresponds to the first ratio signal V1. When the output current I1 '= k × I1 of the first transistor Q1' is copied, the output current I1 'of the first transistor Q1' corresponds to the second proportional signal V2.
In this embodiment, the reference circuit 32 includes a third resistor R3 and a reference current source, a first end of the third resistor R3 is connected to a first end of the replica first resistor R1 ', a second end of the third resistor R3 is grounded through the reference current source, a resistance of the third resistor R3 is the same as a resistance of the replica first resistor R1', and an output current of the reference current source is the reference current Iref. The second terminal of the third resistor R3 outputs a signal indicative of the reference current Iref (a signal proportional to the reference current Iref) to the first input terminal of the error amplifier circuit 33, and the second terminal of the replica first resistor R1 'outputs a signal indicative of the output current I1' of the replica first transistor Q1 '(a signal proportional to the output current I1') to the second input terminal of the error amplifier circuit 33.
The error amplifying circuit 33 is configured to amplify an error value between the reference current Iref and the output current I1 'to output a gate voltage Vg, and use the gate voltage Vg as a MOS resistor gate voltage of the replica MOS resistor unit 1'. Further, in the present embodiment, the error amplifying circuit includes an error amplifier and a capacitor C,
the inverting input terminal of the error amplifier is the first input terminal of the error amplifying circuit 33 and is configured to receive the characterization signal of the reference current Iref, and the non-inverting input terminal of the error amplifier is the second input terminal of the error amplifying circuit 33 and is configured to receive the characterization signal of the output current I1'. The capacitor C is connected between the output end of the error amplifier and the ground end, and the voltage on the capacitor C is the gate voltage Vg.
Referring to fig. 4, in the replica circuit 31, the control terminals of the replica first transistor Q1 'and the replica second transistor Q2' both receive a fixed dc voltage provided by a dc power supply, the dc voltage received by the control terminal of the replica first transistor Q1 'is the maximum value of the first differential input signal received by the control terminal of the first transistor Q1, and the dc voltage received by the control terminal of the replica second transistor Q2' is the minimum value of the second differential input signal received by the control terminal of the second transistor Q2, so that the replica first transistor Q1 'is in an on state and the replica second transistor Q2' is in an off state. If the reference current characterization signal is Vref (signal at the inverting input of the error amplifier) and the characterization signal of the output current I1' is VR1, the control loop of the control circuit 3 will make Vo + = Vref (Vo + is signal at the non-inverting input of the error amplifier), so that the following relationship holds:
Vref=Vo+；
Vo+=Vb`-I1`*R1`；
Vref=Vb`-Iref*R3；
vb 'is the voltage at the current output end of the replica bias tube Qbias', R1 'is the resistance of the replica first resistor R1', and R3 is the resistance of the third resistor R3. Therefore, it can be seen from the above relationship that the control circuit 3 finally controls the output current I1 'to a × Iail', and controls the MOS resistor resistance in the MOS resistor unit 1 through the Vg generated in this way, so as to control the output current I1 to a × Iail. Therefore, the MOS resistor in the MOS resistor unit 1 can be controlled by the gate voltage generated by the control circuit 3, so that the output current of the differential amplifier ranges from a × Iail to (1-a) × Iail, that is, the resistance value of the MOS resistor is adjusted to a suitable value by the precise gate voltage of the MOS resistor, so as to ensure the linearity of the output current of the differential amplifier.
Therefore, the control circuit collects the characterization signals of the tail current of the differential amplification circuit through the copy circuit of the differential amplification circuit, collects the characterization signals of the output current of the first transistor, generates the grid voltage according to the collected characterization signals, accurately controls the resistance value of the MOS resistor in the MOS resistor unit, and can avoid the nonlinear influence of process deviation and temperature deviation on the MOS resistor.
In addition, the present application further provides a driving circuit of a laser, which mainly includes the differential amplifier provided in any embodiment of the present application, wherein a light emitting diode of the laser is connected between a first differential output terminal and a second differential output terminal of the differential amplifier, and dimming control is performed on the light emitting diode by adjusting the magnitude of the output tail current Iail.
In the description herein, references to the description of "some embodiments," "other embodiments," "desired embodiments," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (9)
1. A differential amplifier, comprising:
the differential amplification circuit comprises a differential pair transistor consisting of a first transistor and a second transistor, an MOS (metal oxide semiconductor) resistance unit and a tail current unit, wherein the MOS resistance unit is connected between current output ends of the first transistor and the second transistor and is grounded through the tail current unit;
the control circuit is configured to generate a gate voltage for controlling the resistance value of the MOS resistor in the MOS resistor unit according to the magnitude of the output tail current of the tail current unit and the magnitude of the output current of the first transistor so as to control the magnitude relation between the output current of the first transistor and the output tail current of the tail current unit to be a preset relation;
the control circuit comprises a reference circuit, an error amplifying circuit and a copy circuit of the differential amplifying circuit;
the reference circuit sets a reference current representing the magnitude of the copying output tail current source according to the magnitude of the copying output tail current output by a copying tail current unit in the copying circuit and the preset relationship, wherein the magnitude relationship between the reference current and the copying output tail current is the preset relationship;
the error amplifying circuit is used for amplifying an error value between the reference current and the output current of the copying first transistor in the copying circuit so as to output the grid voltage, and the grid voltage is used as the MOS resistance grid voltage of the copying MOS resistance unit in the copying circuit.
2. The differential amplifier according to claim 1, further comprising a first differential signal input unit and a second differential signal input unit;
the first differential signal input unit comprises a first direct current power supply and a first alternating current power supply which are sequentially connected between the control end and the grounding end of the first transistor, and the polarity of the first direct current power supply is the same as that of the first alternating current power supply;
the second differential signal input unit comprises a second direct current power supply and a second alternating current power supply which are sequentially connected between the control end and the grounding end of the second transistor, and the polarity of the second direct current power supply is opposite to that of the second alternating current power supply;
the first direct current power supply and the second direct current power supply have the same polarity and the same amplitude, and the second alternating current power supply and the first alternating current power supply have the same amplitude.
3. The differential amplifier of claim 1, wherein the MOS resistance unit comprises a first MOS resistance, and the tail current unit comprises a first tail current source and a second tail current source;
the control end of the first MOS resistor receives the grid voltage;
the first end of the first MOS resistor is connected with the current output end of the first transistor and is grounded through the first tail current source;
the second end of the first MOS resistor is connected with the current output end of the second transistor and is grounded through the second tail current source, and the output tail current of the first tail current source is used as the output tail current of the tail current unit.
4. The differential amplifier of claim 1, wherein the MOS resistance unit comprises a second MOS resistance and a third MOS resistance, and the tail current unit comprises a third tail current source;
the grid electrodes of the second MOS resistor and the third MOS resistor receive the grid voltage;
the first end of the second MOS resistor is grounded through the third tail current source, and the second end of the second MOS resistor is connected with the current output end of the first transistor;
the first end of the third MOS resistor is grounded through the third tail current source, and the second end of the third MOS resistor is connected with the current output end of the second transistor;
and the output current of the third tail current source is the output tail current of the tail current unit.
5. The differential amplifier according to claim 1, wherein the replica circuit has the same configuration as the differential amplifier circuit, and includes a replica first transistor corresponding to the first transistor, a replica second transistor provided corresponding to the second transistor, a replica MOS resistance unit corresponding to the MOS resistance unit, and a replica tail current unit corresponding to the tail current unit;
the output current of the first copying transistor is the current of the output current of the first copying transistor, which is reduced according to a preset proportion;
the output current of the second duplicate transistor is the current of the output current of the second transistor reduced according to the preset proportion;
the size of the MOS resistor in the copying MOS resistor unit is the size of the MOS resistor in the MOS resistor unit reduced according to the preset proportion;
and the copied output tail current of the copied tail current unit is the current of the output tail current of the tail current unit reduced according to the preset proportion.
6. The differential amplifier of claim 5, wherein the differential amplifying circuit further comprises a first resistor and a second resistor, the replica circuit further comprising a replica first resistor corresponding to the first resistor and a replica second resistor corresponding to the second resistor;
the first end of the first resistor is connected with a power supply, the second end of the first resistor is connected with the current input end of the first transistor, the control end of the first transistor is a first differential input end of the differential amplifier, and the current output end of the first resistor is a first differential output end of the differential amplifier;
the first end of the second resistor is connected with the power supply, the second end of the second resistor is connected with the current input end of the second transistor, the control end of the first transistor is a second differential input end of the differential amplifier, and the current output end of the first transistor is a second differential output end of the differential amplifier;
the resistance value of the first copied resistor is the resistance value of the first resistor reduced according to the preset proportion, and the resistance value of the second copied resistor is the resistance value of the second resistor reduced according to the preset proportion.
7. The differential amplifier of claim 6, wherein the reference circuit comprises a third resistor and a reference current source;
the first end of the third resistor is connected with the first end of the first replica resistor, and the second end of the third resistor is grounded through the reference current source;
the resistance value of the third resistor is the same as that of the copied first resistor, and the output current of the reference current source is the reference current;
the second end of the third resistor outputs the representation signal of the reference current to the first input end of the error amplifying circuit, and the second end of the copied first resistor outputs the representation signal of the output current of the copied first transistor to the second input end of the error amplifying circuit.
8. The differential amplifier of claim 7, wherein the error amplification circuit comprises an error amplifier and a capacitor;
the inverting input end of the error amplifier is a first input end of the error amplifying circuit and is used for receiving the representation signal of the reference current, and the non-inverting input end of the error amplifier is a second input end of the error amplifying circuit and is used for receiving the representation signal of the output current of the first copying transistor;
the capacitor is connected between the output end of the error amplifier and a grounding end, and the voltage on the capacitor is the grid voltage.
9. A driver circuit for a laser comprising a differential amplifier as claimed in any one of claims 1 to 8.
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| CN202111023749.4A CN113452333B (en) | 2021-09-02 | 2021-09-02 | Differential amplifier and laser drive circuit |
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| CN101553822A (en) * | 2006-02-13 | 2009-10-07 | 德克萨斯仪器股份有限公司 | Differential amplifier with over-voltage protection and method |
| CN203872141U (en) * | 2014-05-22 | 2014-10-08 | 华南理工大学 | Large-dynamic range variable gain amplifier |
| CN109845097A (en) * | 2016-09-16 | 2019-06-04 | 高通股份有限公司 | Variable gain amplifier with the degeneration resistance and capacitor that are coupled |
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| KR100664309B1 (en) * | 2005-02-18 | 2007-01-04 | 삼성전자주식회사 | Variable gain differential amplifier, variable degeneration impedance controlling device used in the same, and variable degeneration impedance controlling method |
| KR101742343B1 (en) * | 2009-11-30 | 2017-05-31 | 에스티마이크로일렉트로닉스 에스.알.엘. | Driving method for obtaining a gain linear variation of a transconductance amplifier and corresponding driving circuit |
| JP5868885B2 (en) * | 2013-03-07 | 2016-02-24 | 株式会社東芝 | Variable gain amplifier circuit |
| CN213186054U (en) * | 2020-08-04 | 2021-05-11 | 长沙泰科阳微电子有限公司 | Differential amplifier based on negative impedance compensation |
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| CN101553822A (en) * | 2006-02-13 | 2009-10-07 | 德克萨斯仪器股份有限公司 | Differential amplifier with over-voltage protection and method |
| CN203872141U (en) * | 2014-05-22 | 2014-10-08 | 华南理工大学 | Large-dynamic range variable gain amplifier |
| CN109845097A (en) * | 2016-09-16 | 2019-06-04 | 高通股份有限公司 | Variable gain amplifier with the degeneration resistance and capacitor that are coupled |
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