CN113451455B - Preparation method of LED epitaxy, LED epitaxy structure and LED chip - Google Patents
Preparation method of LED epitaxy, LED epitaxy structure and LED chip Download PDFInfo
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- CN113451455B CN113451455B CN202011351538.9A CN202011351538A CN113451455B CN 113451455 B CN113451455 B CN 113451455B CN 202011351538 A CN202011351538 A CN 202011351538A CN 113451455 B CN113451455 B CN 113451455B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H—ELECTRICITY
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H—ELECTRICITY
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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- H—ELECTRICITY
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
- H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
- H01L33/325—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen characterised by the doping materials
Abstract
The invention discloses a preparation method of LED epitaxy, an LED epitaxy structure and an LED chip. The method comprises the following steps: providing a substrate; growing a first semiconductor layer on the substrate; growing a multi-quantum well light-emitting layer on the first semiconductor layer, wherein the multi-quantum well light-emitting layer comprises InGaN potential well layers and GaN barrier layers which are alternately stacked, and the thickness of each InGaN potential well layer is 1.5-3 nm; and growing a second semiconductor layer on the multiple quantum well light-emitting layer. The invention can realize the increase of In component In the InGaN well layer at lower growth temperature by reducing the thickness of the InGaN well layer. The invention adopts the ultrathin InGaN well layer, can reduce the stress caused by the lattice mismatch of the InGaN well layer and the GaN barrier layer, improves the polarization, effectively increases the overlapping area of electron and hole wave functions, and finally obtains the GaN-based LED with high internal quantum efficiency in a long wave band.
Description
Technical Field
The present invention relates to the field of semiconductors, and in particular, to a method for manufacturing a Light-Emitting Diode (LED) epitaxy, an LED epitaxy structure, and an LED chip.
Background
At present, mainstream GaN (gallium nitride) -based Micro (Micro) and Mini LED (Mini LED) are both of a structure for realizing light emission based on a multi-Quantum Well (MQW for short), a light emitting region of the multi-Quantum Well is formed by periodically and alternately growing an InGaN (indium gallium nitride) Well layer (Well) and a GaN Barrier layer (Barrier), and the light emitting region of the multi-Quantum Well is a core region for radiation composite light emission of carriers. The InGaN well layer has smaller width and narrower band gap, and can form an energy band structure of a quantum well with a GaN barrier layer in a multi-quantum well light emitting region, and the structure can enable electrons and holes injected into an active region to be limited in an approximately two-dimensional space to achieve radiation recombination light emitting. The effective increase of the overlap of the wave functions of electrons and holes is one of the effective ways for improving the radiation recombination luminous efficiency of the electrons and the holes in the quantum wells at present.
However, as the wavelength required for the device increases, the quantum efficiency of the GaN-based Micro or Mini LED device decreases significantly. This is because lattice mismatch exists between an InGaN Well layer (Well) and a GaN Barrier layer (Barrier) constituting a multi-quantum Well light emitting region, and when a wavelength increases, an In component increases and lattice mismatch between InGaN/GaN increases, so that stress In the multi-quantum Well light emitting region increases, a polarization effect also increases, an overlap region of electron and hole wave functions decreases, and light emitting efficiency is finally affected. Meanwhile, poor miscibility between InN and GaN makes In incorporation difficult, and too high In composition causes fluctuation of In composition In the InGaN well layer, resulting In deterioration of the heterojunction interface. Therefore, it is difficult to obtain high-efficiency high In composition GaN-based Micro and Mini LEDs.
Accordingly, the prior art is yet to be improved and developed.
Disclosure of Invention
In view of the defects of the prior art, the invention aims to provide a preparation method of an LED epitaxy and an LED epitaxy structure, aiming at solving the problem that high-efficiency GaN-based Micro and Mini LEDs with high In components are difficult to obtain In the prior art.
The technical scheme of the invention is as follows:
a method of LED epitaxial fabrication, wherein the method comprises:
providing a substrate;
growing a first semiconductor layer on the substrate;
growing a multi-quantum well light emitting layer on the first semiconductor layer, wherein the multi-quantum well light emitting layer comprises InGaN potential well layers and GaN potential barrier layers which are alternately stacked, and the thickness of the InGaN potential well layers is 1.5-3 nm;
and growing a second semiconductor layer on the multiple quantum well light-emitting layer.
Optionally, the growth temperature of the InGaN well layer is less than 730 ℃.
Optionally, the growth pressure of the InGaN well layer is greater than 400mbar, and the carrier gas is pure nitrogen.
Optionally, the thickness of the GaN barrier layer is 10-15 nm, and the growth temperature of the GaN barrier layer is greater than 880 ℃.
Optionally, the growth pressure of the GaN barrier layer is greater than 400mbar, and the carrier gas is pure nitrogen.
Optionally, the alternating period of the InGaN well layer and the GaN barrier layer is 9 or less.
An LED epitaxial structure, wherein the LED epitaxial structure comprises:
the semiconductor device includes a first semiconductor layer, a second semiconductor layer and a multiple quantum well light emitting layer;
the multiple quantum well light emitting layer is arranged between the first semiconductor layer and the second semiconductor layer;
the multi-quantum well light-emitting layer comprises InGaN well layers and GaN barrier layers which are alternately stacked, and the thickness of each InGaN well layer is 1.5-3 nm.
Optionally, the molar content of In the InGaN well layer is 28-35%.
Optionally, the alternating period of the InGaN well layer and the GaN barrier layer is 9 or less.
Optionally, the first semiconductor layer includes an undoped GaN buffer layer, a u-type GaN layer on the undoped GaN buffer layer, and an n-type GaN layer on the u-type GaN layer, and the multiple quantum well light-emitting layer is on the n-type GaN layer;
the second semiconductor layer comprises a p-type AlGaN electron blocking layer positioned on the multiple quantum well light-emitting layer and a p-type GaN layer positioned on the p-type AlGaN electron blocking layer.
An LED chip comprises a first electrode, a second electrode and the LED epitaxial structure, wherein the first electrode is arranged on a first semiconductor layer, and the second electrode is arranged on a second semiconductor layer.
Has the advantages that: according to the invention, the thickness of the InGaN well layer is reduced and set to be 1.5-3 nm, so that the increase of In components In the InGaN well layer can be realized at a lower growth temperature, and the epitaxial growth of the GaN-based Micro or Mini LED In a long wave band (greater than 550nm) is realized. In the invention, based on a thin InGaN well layer (with the thickness of 1.5-3 nm), the growth temperature of the InGaN well layer can be reduced from the main flow growth temperature of less than 750 ℃ to less than 730 ℃, and the molar content of an In component In the InGaN well layer can be increased to 28-35%. In addition, the LED epitaxial structure (namely the GaN-based Micro or Mini LED) with high internal quantum efficiency (more than 50%) in a long wave band (more than 550nm) is finally obtained by adopting the ultrathin InGaN well layer, so that the stress caused by lattice mismatch of the InGaN well layer and the GaN barrier layer can be reduced, and the polarization is improved.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing an LED epitaxy according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a multiple quantum well light emitting layer in an embodiment of the invention.
FIG. 3 is a comparison of InGaN/GaN Multiple Quantum Well (MQW) growth temperature curves for mainstream LED epitaxy and InGaN/GaN Multiple Quantum Well (MQW) growth temperature curves for inventive LED epitaxy.
Fig. 4 is another schematic flow chart of a method for manufacturing an LED epitaxy according to an embodiment of the present invention.
Detailed Description
The invention provides a preparation method of an LED epitaxy, an LED epitaxy structure and an LED chip, and the invention is further described in detail below in order to make the purpose, technical scheme and effect of the invention clearer and clearer. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The embodiment of the invention provides a preparation method of LED epitaxy, as shown in FIG. 1, the method comprises the following steps:
s10, providing a substrate;
s20, growing a first semiconductor layer on the substrate;
s30, growing a multi-quantum well light-emitting layer on the first semiconductor layer, wherein the multi-quantum well light-emitting layer comprises InGaN well layers and GaN barrier layers (shown in figure 2) which are alternately stacked, and the thickness of each InGaN well layer is 1.5-3 nm;
and S40, growing a second semiconductor layer on the multiple quantum well light-emitting layer.
In the multi-quantum well light-emitting layer, the thickness of each InGaN well layer is 1.5 to 3nm, and the thickness of each InGaN well layer may be the same thickness in the thickness range, or may be different thicknesses in the thickness range, as long as the thickness of each InGaN well layer is within the range. Other process parameters, such as growth temperature, growth pressure, etc., other than thickness, are similar to those described above.
In the embodiment, the thickness of the InGaN well layer is reduced and set to be 1.5-3 nm, so that the increase of In components In the InGaN well layer can be realized at a lower growth temperature, and the epitaxial growth of the LED In a long-wave band (greater than 550nm) is realized. In this embodiment, based on the thin InGaN well layer, the growth temperature of the InGaN well layer may be reduced, and since the growth temperature of the InN material is lower and the bond energy is weaker, the reduction of the growth temperature may increase the content of the In component In the InGaN well layer. Based on a thin InGaN well layer (with a thickness of 1.5-3 nm), the growth temperature of the InGaN well layer can be reduced from a main flow growth temperature of less than 750 ℃ to less than 730 ℃, and the molar content of an In component In the InGaN well layer grown In the temperature range can be increased to 28-35%, as shown In FIG. 3. Furthermore, the growth temperature of the InGaN well layer is 700-730 ℃. Of course, the temperature range for growing the InGaN well layer is not limited to 730-700 ℃, and may be below 700 ℃.
In addition, the ultra-thin InGaN well layer is adopted in the embodiment, stress caused by lattice mismatch of the InGaN well layer and the GaN barrier layer can be reduced, polarization is improved, so that an overlapping area of electron and hole wave functions is effectively increased, and finally the LED epitaxial structure with high internal quantum efficiency (more than 50%) in a long wave band (more than 550nm) is obtained, and the LED epitaxial structure can be a GaN-based Micro or Mini LED.
In one embodiment, the growth pressure of the InGaN well layer is greater than 400mbar and the carrier gas is pure nitrogen. Furthermore, the growth pressure of the InGaN well layer is 400-500 mbar, for example, 400mbar, 450mbar or 500mbar, and the like, and the InGaN well layer grown in the pressure range has better interface quality to improve the photoelectric performance of the product. The pressure range of the InGaN well layer grown by the growth method is not limited to 400-500 mbar, and can be more than 500mbar, such as 600 mbar.
In one embodiment, the GaN barrier layer has a thickness of 10 to 15nm, for example, 10nm, 14nm, or 15 nm.
In one embodiment, the GaN barrier layer is grown at a temperature greater than 880 ℃. Furthermore, the growth temperature of the GaN barrier layer is 880-940 ℃, for example 900 ℃, 920 ℃ or 940 ℃, etc. The GaN barrier layer with the temperature range can ensure that the layer has better crystal quality. Of course, the temperature range for growing the GaN barrier layer may not be limited to 880-940 ℃, or may be 940 ℃ or higher, such as 1000 ℃.
In one embodiment, the GaN barrier layer is grown at a pressure greater than 400mbar and the carrier gas is pure nitrogen. Furthermore, the growth pressure of the GaN barrier layer is 400-600 mbar, for example, 400mbar, 450mbar or 600mbar, and the like, and the GaN barrier layer grown in the pressure range has a better interface to form a steep interface quality with the InGaN well layer, so that carriers are limited in the well to emit light. Of course, the pressure range for growing the GaN barrier layer may not be limited to 400 to 600mbar, or may be 600mbar or more, for example, 700mbar or the like.
In one embodiment, the InGaN well layers and GaN barrier layers have an alternation period of 9 or less, as shown in fig. 2. Note that one period is constituted by one InGaN well layer and one GaN barrier layer located on the InGaN well layer. Further, the alternation period of the InGaN well layer and the GaN barrier layer is 6 to 9, for example, 6, 7, or 8.
In one embodiment, the substrate may be a sapphire substrate. Easy to manufacture and obtain.
In one embodiment, the first semiconductor layer includes an n-type GaN layer.
In one embodiment, the first semiconductor layer includes an undoped GaN buffer layer, a u-type GaN layer on the undoped GaN buffer layer, and an n-type GaN layer on the u-type GaN layer, and the multiple quantum well light emitting layer is on the n-type GaN layer.
In one embodiment, the second semiconductor layer includes a p-type GaN layer.
In one embodiment, the second semiconductor layer includes a p-type AlGaN (aluminum gallium nitride) electron blocking layer on the multiple quantum well light emitting layer, and a p-type GaN layer on the p-type AlGaN electron blocking layer.
In one embodiment, the LED epitaxial structure is specifically composed of a substrate, an undoped GaN buffer layer, a u-type GaN layer, an n-type GaN layer, a multi-quantum well light-emitting layer, a p-type AlGaN electron blocking layer and a p-type GaN layer which are sequentially stacked; as shown in fig. 4, the method for preparing the LED epitaxy specifically includes the following steps:
providing a substrate;
growing an undoped GaN buffer layer on the substrate;
growing a u-type GaN layer (which can be recorded as a u-GaN layer) on the undoped GaN buffer layer;
growing an n-type GaN layer (can be recorded as an n-GaN layer) on the u-type GaN layer;
growing a multi-quantum well light-emitting layer on the n-type GaN layer, wherein the multi-quantum well light-emitting layer comprises InGaN well layers and GaN barrier layers (which can be recorded as InGaN/GaN MQW layers) which are alternately stacked;
growing a p-type AlGaN electron blocking layer (which can be recorded as a p-AlGaN layer) on the multiple quantum well light-emitting layer;
and growing a p-type GaN layer (which can be recorded as a p-GaN layer) on the p-type AlGaN electron blocking layer to obtain the LED epitaxial structure.
The embodiment of the invention provides an LED epitaxial structure, wherein the LED epitaxial structure comprises:
the semiconductor device includes a first semiconductor layer, a second semiconductor layer and a multiple quantum well light emitting layer;
the multiple quantum well light emitting layer is arranged between the first semiconductor layer and the second semiconductor layer;
the multi-quantum well light-emitting layer comprises InGaN well layers and GaN barrier layers which are alternately stacked, and the thickness of each InGaN well layer is 1.5-3 nm.
In one embodiment, the InGaN well layer and GaN barrier layer have an alternation period of 9 or less.
In one embodiment, the first semiconductor layer includes an n-type GaN layer.
In one embodiment, the first semiconductor layer includes an undoped GaN buffer layer, a u-type GaN layer on the undoped GaN buffer layer, and an n-type GaN layer on the u-type GaN layer, and the multiple quantum well light emitting layer is on the n-type GaN layer.
In one embodiment, the second semiconductor layer includes a p-type GaN layer.
In one embodiment, the second semiconductor layer includes a p-type AlGaN electron blocking layer on the multiple quantum well light emitting layer, and a p-type GaN layer on the p-type AlGaN electron blocking layer.
In one embodiment, the LED epitaxial structure specifically includes:
a substrate;
an undoped GaN buffer layer on the substrate;
a u-type GaN layer on the undoped GaN buffer layer;
the n-type GaN layer is positioned on the u-type GaN layer;
the multiple quantum well light-emitting layer is positioned on the n-type GaN layer;
the p-type AlGaN electron blocking layer is positioned on the multiple quantum well light-emitting layer;
a p-type GaN layer on the p-type AlGaN electron blocking layer.
Further relevant details regarding the LED epitaxial structure are given above and will not be described in detail here.
The embodiment of the invention provides an LED chip, which comprises a first electrode, a second electrode and the LED epitaxial structure, wherein the first electrode is arranged on a first semiconductor layer, and the second electrode is arranged on a second semiconductor layer. The embodiment adopts the LED epitaxial structure, so that the high internal quantum efficiency of the LED chip is realized.
In summary, according to the preparation method of the LED epitaxy and the LED epitaxy structure provided by the invention, the thickness of the InGaN well layer is reduced and set to be 1.5-3 nm, so that the increase of In components In the InGaN well layer can be realized at a lower growth temperature, and the epitaxial growth of the GaN-based Micro or Mini LED In a long-wave band (greater than 550nm) is realized. In the invention, based on a thin InGaN well layer (with the thickness of 1.5-3 nm), the growth temperature of the InGaN well layer can be reduced from the main flow growth temperature of less than 750 ℃ to less than 730 ℃, and the molar content of an In component In the InGaN well layer can be increased to 28-35%. In addition, the invention adopts the ultrathin InGaN well layer, can reduce the stress caused by the lattice mismatch of the InGaN well layer and the GaN barrier layer, and improves the polarization, thereby effectively increasing the overlapping area of electron and hole wave functions, and finally obtaining the LED epitaxial structure with high internal quantum efficiency (more than 50%) in a long wave band (more than 550 nm).
It is to be understood that the invention is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the invention as defined by the appended claims.
Claims (7)
1. A preparation method of LED epitaxy is characterized by comprising the following steps:
providing a substrate;
growing a first semiconductor layer on the substrate;
growing a multi-quantum well light-emitting layer on the first semiconductor layer, wherein the multi-quantum well light-emitting layer comprises InGaN potential well layers and GaN barrier layers which are alternately stacked, and the thickness of each InGaN potential well layer is 1.5-3 nm;
growing a second semiconductor layer on the multiple quantum well light emitting layer; the growth temperature of the InGaN well layer is less than 700 ℃; the molar content of In the InGaN potential well layer is 28-35%; the alternating period of the InGaN well layer and the GaN barrier layer is 7, 8 or 9; the growth pressure of the InGaN potential well layer is greater than 400 mbar; the growth temperature of the GaN barrier layer is higher than 880 ℃; the growth pressure of the GaN barrier layer is greater than 400 mbar.
2. The method for preparing LED epitaxy according to claim 1, wherein the carrier gas used for growing the InGaN well layer is pure nitrogen.
3. The epitaxial LED preparation method of claim 1, wherein the GaN barrier layer has a thickness of 10-15 nm.
4. The method for LED epitaxy as claimed in claim 1, wherein the carrier gas used for growth of the GaN barrier layer is pure nitrogen.
5. An LED epitaxial structure, comprising:
the semiconductor device includes a first semiconductor layer, a second semiconductor layer and a multiple quantum well light emitting layer;
the multiple quantum well light emitting layer is arranged between the first semiconductor layer and the second semiconductor layer;
the multi-quantum well light-emitting layer comprises InGaN potential well layers and GaN potential barrier layers which are alternately stacked, and the thickness of each InGaN potential well layer is 1.5-3 nm; the molar content of In the InGaN potential well layer is 28-35%; the alternating period of the InGaN well layers and the GaN barrier layers is 7, 8 or 9.
6. The LED epitaxial structure of claim 5, wherein the first semiconductor layer comprises an undoped GaN buffer layer, a u-type GaN layer on the undoped GaN buffer layer, and an n-type GaN layer on the u-type GaN layer, the multiple quantum well light emitting layer being on the n-type GaN layer;
the second semiconductor layer comprises a p-type AlGaN electron blocking layer positioned on the multiple quantum well light-emitting layer and a p-type GaN layer positioned on the p-type AlGaN electron blocking layer.
7. An LED chip, comprising a first electrode, a second electrode and the LED epitaxial structure of any one of claims 5 to 6, wherein the first electrode is disposed on the first semiconductor layer, and the second electrode is disposed on the second semiconductor layer.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004008551A1 (en) * | 2002-07-16 | 2004-01-22 | Nitride Semiconductors Co.,Ltd. | Gallium nitride-based compound semiconductor device |
| JP2011223043A (en) * | 2011-08-09 | 2011-11-04 | Sumitomo Electric Ind Ltd | Semiconductor light-emitting device and method of manufacturing the semiconductor light-emitting device |
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| CN101488550B (en) * | 2009-02-27 | 2010-10-13 | 上海蓝光科技有限公司 | Manufacturing method for LED in high In ingredient multiple InGaN/GaN quantum wells structure |
| CN103137807A (en) * | 2013-02-22 | 2013-06-05 | 中国科学院半导体研究所 | Green ray light-emitting diode (LED) epitaxial structure with stress relief layer and production method thereof |
| CN104701432A (en) * | 2015-03-20 | 2015-06-10 | 映瑞光电科技(上海)有限公司 | GaN-based LED epitaxial structure and preparation method thereof |
| CN105161583A (en) * | 2015-06-24 | 2015-12-16 | 广西盛和电子科技股份有限公司 | GaN-based UV semiconductor LED and manufacturing method thereof |
| CN105720159B (en) * | 2016-03-09 | 2018-01-09 | 太原理工大学 | A kind of preparation method of high-luminous-efficiency GaN-based LED epitaxial wafer |
| CN106206879A (en) * | 2016-08-30 | 2016-12-07 | 扬州中科半导体照明有限公司 | A kind of epitaxial growth technology of nitride semiconductor photogenerator |
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| WO2004008551A1 (en) * | 2002-07-16 | 2004-01-22 | Nitride Semiconductors Co.,Ltd. | Gallium nitride-based compound semiconductor device |
| JP2011223043A (en) * | 2011-08-09 | 2011-11-04 | Sumitomo Electric Ind Ltd | Semiconductor light-emitting device and method of manufacturing the semiconductor light-emitting device |
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