CN113451134B - Method for forming semiconductor device - Google Patents
Method for forming semiconductor device Download PDFInfo
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- CN113451134B CN113451134B CN202010231966.1A CN202010231966A CN113451134B CN 113451134 B CN113451134 B CN 113451134B CN 202010231966 A CN202010231966 A CN 202010231966A CN 113451134 B CN113451134 B CN 113451134B
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 84
- 238000012937 correction Methods 0.000 claims abstract description 33
- 238000012360 testing method Methods 0.000 claims description 91
- 229920002120 photoresistant polymer Polymers 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 28
- 238000001312 dry etching Methods 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 184
- 239000000463 material Substances 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- 238000012876 topography Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
Abstract
The invention discloses a method for forming a semiconductor device, which comprises the steps of providing a device layout, and respectively scanning source and drain plug slot patterns in a threshold area around each initial gate plug slot pattern so as to obtain density parameters of each initial gate plug slot pattern; respectively compensating each initial grid plug groove pattern according to the density parameters to obtain a grid plug groove correction pattern, wherein the characteristic size of the grid plug groove correction pattern is reduced along with the increase of the density parameters; and etching the flat layer and the dielectric layer to form a grid plug groove. By adopting the scheme, the etching rate of the dielectric layer and the flat layer is smaller in the area with larger density of the source-drain plug grooves, so that the problem of over-etching when the grid plug grooves are formed by etching is avoided. In the area with smaller density of the source-drain plug grooves, the etching rate of the dielectric layer and the flat layer is higher, so that the problem of insufficient etching when the grid plug grooves are formed by etching is avoided. Thus, the morphology of the finally formed gate plug groove is more uniform.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and in particular, to a method for forming a semiconductor device.
Background
In the semiconductor manufacturing process, transferring the pattern on the mask to the semiconductor chip through photolithography and etching steps is a very important and complicated process.
The size of the post-lithographic feature size is characterized by the post-lithographic feature size (after develop inspection critical dimension, ADI CD), and the size of the ADI CD directly affects the post-etch feature size (after Etch inspection critical dimension, AEI CD). Before etching, a dielectric layer and a planarization layer are deposited, a patterned photoresist layer is formed on the planarization layer, and then the planarization layer and thus the dielectric layer are etched with the patterned photoresist layer.
The density of the source-drain plug grooves formed in the dielectric layer below the flat layer is different, so that a source-drain plug groove sparse region and a source-drain plug groove dense region can be formed in the dielectric layer. The dense area of the source and drain plug grooves is thinner than the flat layer formed on the dielectric layer when the flat layer material is deposited because the dense area of the source and drain plug grooves is denser (part of the flat layer material enters the source and drain plug grooves when the flat layer is deposited), and the sparse area of the source and drain plug grooves is thicker than the flat layer formed on the dielectric layer when the flat layer material is deposited because the sparse area of the source and drain plug grooves is thinner. Therefore, there is a problem in that over-etching or under-etching occurs when the gate plug groove is formed by etching, because the thickness of the planarization layer is not uniform, and because the process window for forming the gate plug groove is insufficient.
Both the over-etching and under-etching described above affect the uniformity of the semiconductor device, and thus the device performance is also degraded.
Disclosure of Invention
The invention aims to solve the problems of over-etching or insufficient etching in the prior art when a grid plug groove is formed by etching, and the performance of a semiconductor device is affected.
The invention provides a method for forming a semiconductor device, which can avoid the problems of over-etching or insufficient etching when a grid plug groove is formed by etching.
To solve the above technical problems, an embodiment of the present invention discloses a method for forming a semiconductor device, including:
providing a substrate;
providing a device layout, wherein the device layout comprises a source-drain plug slot pattern and an initial grid plug slot pattern;
forming a gate structure and a dielectric layer covering the top and the side of the gate structure on the substrate, wherein the dielectric layer is provided with source-drain plug grooves which are positioned at two sides of the gate structure and correspond to the source-drain plug groove patterns;
forming a flat layer in the source drain plug groove and on the dielectric layer, wherein the thickness of the flat layer on the dielectric layer is different;
scanning the source and drain plug slot patterns in the threshold area around each initial gate plug slot pattern on the device layout respectively, so as to obtain density parameters of each initial gate plug slot pattern;
respectively compensating each initial grid plug groove pattern according to the density parameters to obtain a grid plug groove correction pattern, wherein the characteristic size of the grid plug groove correction pattern is reduced along with the increase of the density parameters;
forming a patterned photoresist layer on the planar layer based on the gate plug trench correction pattern;
and etching the flat layer and the dielectric layer by taking the patterned photoresist layer as a mask, and forming a gate plug groove positioned on the gate structure in the dielectric layer.
Optionally, the method for scanning the source and drain plug slot patterns in the threshold area around each initial gate plug slot pattern to obtain the density parameter of each initial gate plug slot pattern includes:
scanning the source drain plug slot patterns in the threshold area of the initial gate plug slot patterns by taking each edge point of the initial gate plug slot patterns as a scanning center and using a threshold scanning radius to obtain scanning source drain plug slot patterns corresponding to each initial gate plug slot pattern;
and obtaining the density parameter of each initial grid electrode plug groove pattern according to the ratio of the area of each scanning source drain plug groove pattern to the area of the corresponding threshold region.
Alternatively to this, the method may comprise,
wherein ,Di The density parameter of the ith initial grid plug groove pattern is i, wherein i is an integer greater than or equal to 2;
the area of the scanning source drain plug groove pattern corresponding to the ith initial gate plug groove pattern is the area of the scanning source drain plug groove pattern, and n is an integer greater than or equal to 1;
D total i is the area of the threshold region corresponding to the ith initial gate plug slot pattern;
the scanning source drain plug groove pattern corresponding to the ith initial grid plug groove pattern comprises n sub-scanning source drain plug grooves; f (k) i The area of the source and drain plug grooves is scanned for the kth sub-corresponding to the ith initial grid plug groove pattern, and k is an integer greater than or equal to 1 and less than or equal to n.
Alternatively, when the i-th initial gate plug trench pattern has a square projected shape on the substrate,
wherein R is a threshold scanning radius;
is the feature size of the ith initial gate plug trench pattern.
Optionally, according to the density parameter, compensating each initial gate plug slot pattern, and obtaining the gate plug slot correction pattern includes:
acquiring compensation amounts of the initial gate plug slot patterns according to density parameters of the initial gate plug slot patterns in different areas;
obtaining a grid plug groove correction pattern according to each initial grid plug groove pattern and the corresponding compensation quantity;
wherein ,
for the feature size of the ith initial gate plug trench pattern,
D i for the density parameter of the ith initial gate plug trench pattern,
f(D i ) For the compensation amount corresponding to the ith initial gate plug slot pattern,
and correcting the characteristic dimension of the pattern for the ith grid plug slot, wherein i is an integer greater than or equal to 2.
Optionally, the method for obtaining the compensation amount of each initial gate plug slot pattern according to the density parameters of the initial gate plug slot patterns in different regions includes:
acquiring the slope of a curve function of the density parameter of the initial gate plug slot pattern of different areas along with the position change of the initial gate plug slot pattern;
acquiring zero compensation initial gate plug slot patterns from the initial gate plug slot patterns in different areas;
acquiring a zero compensation point density parameter corresponding to the zero compensation initial grid plug slot pattern;
acquiring compensation amounts of the initial gate plug slot patterns according to the slope, the density parameters of the initial gate plug slot patterns and the density parameters of the zero compensation area;
f(D i )＝-|k|(D i -D i0 )
wherein k is the slope and d_i0 is zero.
Optionally, the method for obtaining the zero compensation initial gate plug slot pattern includes:
providing a test substrate;
forming a test gate structure and a test medium layer covering the top and the side of the test gate structure on the test substrate, wherein the test medium layer is provided with test source-drain plug grooves positioned on two sides of the test gate structure;
forming a test flat layer in the test source drain plug groove and on the test dielectric layer, wherein the thickness of the test flat layer on the test dielectric layer is different;
forming a test photoresist layer on the test planarization layer based on the initial gate plug slot pattern;
etching the test flat layer and the test dielectric layer by taking the test photoresist layer as a mask, and forming a test gate plug groove positioned on the test gate structure in the test dielectric layer;
acquiring a zero compensation test gate plug groove according to the shapes of the test gate plug grooves in different areas;
and obtaining a corresponding zero compensation initial gate plug groove pattern according to the zero compensation test gate plug groove.
Optionally, etching conditions of the test flat layer and the test dielectric layer by using the test photoresist layer as a mask are identical to etching conditions of the flat layer and the dielectric layer by using the patterned photoresist layer as a mask.
Optionally, the process of etching the test flat layer and the test dielectric layer by using the test photoresist layer as a mask is an anisotropic dry etching process, and the process of etching the flat layer and the dielectric layer by using the patterned photoresist layer as a mask is an anisotropic dry etching process;
the etching conditions include etching gas, gas flow, chamber pressure, source rf power, and bias power.
Optionally, the projection shape of the initial gate plug groove pattern on the substrate is any one of a polygon, an ellipse and a rectangle.
The beneficial effects of the invention are as follows:
and scanning the source and drain plug slot patterns in the threshold area around each initial gate plug slot pattern on the device layout, thereby obtaining the density parameters of each initial gate plug slot pattern. And then respectively compensating each initial grid plug groove pattern according to the density parameters to obtain a grid plug groove correction pattern. And the feature size of the gate plug trench modification pattern decreases with increasing density parameter. And forming a patterned photoresist layer according to the grid plug groove correction pattern, and etching the flat layer and the dielectric layer to form the grid plug groove. That is, in the region where the density of the source-drain plug grooves is large, by reducing the feature size of the gate plug groove correction pattern, the rate of etching the dielectric layer and the planarizing layer can be reduced, so that the problem of overetching occurring when forming the gate plug groove by etching can be avoided. In the region with smaller density of the source and drain plug grooves, the characteristic size of the grid plug groove correction pattern is increased, so that the speed of etching the dielectric layer and the flat layer can be increased, and the problem of insufficient etching when the grid plug grooves are formed by etching can be avoided. Thus, although the regions of the source-drain plug trenches having a larger density have a difference from the planar layer thickness on the dielectric layer of the regions of the source-drain plug trenches having a smaller density, the end points of the etched dielectric layer and the planar layer are the same. This results in a more uniform topography of the resulting gate plug and better performance of the semiconductor device.
Drawings
Fig. 1 and 2 are schematic structural views of a semiconductor device;
fig. 3 is a flowchart of a method for forming a semiconductor device according to an embodiment of the present invention;
fig. 4 and fig. 5 are schematic structural diagrams of device layouts corresponding to a method for forming a semiconductor device according to an embodiment of the present invention;
fig. 6 to 7 are schematic structural diagrams corresponding to a method for forming a semiconductor device according to an embodiment of the present invention;
fig. 8 to 9 are schematic views of another structure corresponding to the method for forming a semiconductor device according to an embodiment of the present invention.
Detailed Description
Further advantages and effects of the present invention will become apparent to those skilled in the art from the disclosure of the present specification, by describing the embodiments of the present invention with specific examples. While the description of the invention will be described in connection with the preferred embodiments, it is not intended to limit the inventive features to the implementation. Rather, the purpose of the invention described in connection with the embodiments is to cover other alternatives or modifications, which may be extended by the claims based on the invention. The following description contains many specific details for the purpose of providing a thorough understanding of the present invention. The invention may be practiced without these specific details. Furthermore, some specific details are omitted from the description in order to avoid obscuring the invention. It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.
It should be noted that in this specification, like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present embodiment, it should be noted that the azimuth or positional relationship indicated by the terms "upper", "lower", "inner", "bottom", etc. are based on the azimuth or positional relationship shown in the drawings, or the azimuth or positional relationship in which the inventive product is conventionally put in use, are merely for convenience of describing the present invention and simplifying the description, and are not indicative or implying that the apparatus or element to be referred to must have a specific azimuth, be configured and operated in a specific azimuth, and therefore should not be construed as limiting the present invention.
The terms "first," "second," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.
In the description of the present embodiment, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present embodiment can be understood in a specific case by those of ordinary skill in the art.
As described in the background art, the existing semiconductor device is greatly affected by over-etching and under-etching.
For example, in the semiconductor device shown in fig. 1 and 2, a gate structure 4 is formed on a substrate 1, a dielectric layer 2 is formed to cover the top and side of the gate structure 4, and a source-drain plug trench 6 corresponding to the source-drain plug trench pattern is formed in the dielectric layer 2 and located on both sides of the gate structure 4. And forming a flat layer 3 in the source drain plug groove 6 and on the dielectric layer 2. A patterned photoresist layer 5 is formed on the planarization layer 3. The thickness of the planarization layer 3 on the dielectric layer 2 is different.
Specifically, the difference in thickness of the planarization layer 3 on the dielectric layer 2 is due to the difference in density of the source-drain plug grooves 6 formed in the dielectric layer 2 under the planarization layer 3, so that a sparse region of the source-drain plug grooves and a dense region of the source-drain plug grooves are formed in the dielectric layer 2. As shown in fig. 1, in the dense source-drain plug grooves, the flat layer 3 formed on the dielectric layer 2 when the flat layer material is deposited is thinner (part of the flat layer material enters the source-drain plug grooves 6 when the flat layer 3 is deposited) because the source-drain plug grooves are denser; as shown in fig. 2, in the sparse region of the source-drain plug grooves, the source-drain plug grooves are sparse, so that the flat layer material is deposited to form a thicker flat layer 3 on the medium 2. Therefore, the thickness of the flat layer 3 is not uniform.
Also, because of the difference in thickness of the planarization layer 3, when the planarization layer 3 and the dielectric layer 2 are etched using the patterned photoresist layer 5 as a mask, when a gate plug groove on the gate structure 4 is formed in the dielectric layer 2, the area corresponding to the thinner planarization layer 3 has a higher etching speed, and the over-etching condition exists, whereas the area corresponding to the thicker planarization layer 3 has a lower etching speed, and the under-etching condition occurs.
The over etching and the under etching occur in the same device, which results in poor uniformity of the formed gate plug grooves and poor performance of the semiconductor device.
The dielectric layer 2 is further formed with a protective layer 21 covering the top of the gate structure 4 and extending to both sides of the gate structure 4 at a position on the top of the gate structure 4. Further, at least part of the source drain plug trench 6 penetrates the protection layer 21.
The invention provides a method for forming a semiconductor device, which aims to solve the problem that over-etching or insufficient etching exists when a grid plug groove is formed by etching in the prior art and influence the performance of the semiconductor device. Specifically, as shown in fig. 3, the method for forming a semiconductor device provided by the present invention includes:
step S1: providing a substrate;
step S2: providing a device layout, wherein the device layout comprises a source-drain plug slot pattern and an initial grid plug slot pattern;
step S3: forming a gate structure and a dielectric layer covering the top and the side of the gate structure on a substrate, wherein the dielectric layer is provided with source-drain plug grooves which are positioned on two sides of the gate structure and correspond to source-drain plug groove patterns;
step S4: forming a flat layer in the source drain plug groove and on the dielectric layer, wherein the thickness of the flat layer on the dielectric layer is different;
step S5: scanning source and drain plug slot patterns in a threshold area around each initial gate plug slot pattern on a device layout respectively, so as to obtain density parameters of each initial gate plug slot pattern;
step S6: respectively compensating each initial grid plug groove pattern according to the density parameters to obtain a grid plug groove correction pattern, wherein the characteristic size of the grid plug groove correction pattern is reduced along with the increase of the density parameters;
step S7: forming a patterned photoresist layer on the planarization layer based on the gate plug trench correction pattern;
step S8: and etching the flat layer and the dielectric layer by taking the patterned photoresist layer as a mask, and forming a grid plug groove positioned on the grid structure in the dielectric layer.
In the area with larger density of the source and drain plug grooves, the method can reduce the speed of etching the dielectric layer and the flat layer by reducing the characteristic size of the grid plug groove correction pattern, thereby avoiding the problem of over etching when the grid plug groove is formed by etching. In the region with smaller density of the source and drain plug grooves, the characteristic size of the grid plug groove correction pattern is increased, so that the speed of etching the dielectric layer and the flat layer can be increased, and the problem of insufficient etching when the grid plug grooves are formed by etching can be avoided. Thus, although the regions of the source-drain plug trenches having a larger density have a difference from the planar layer thickness on the dielectric layer of the regions of the source-drain plug trenches having a smaller density, the end points of the etched dielectric layer and the planar layer are the same. This results in a more uniform topography of the resulting gate plug and better performance of the semiconductor device.
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
The method for adjusting the process window according to the embodiment of the present invention is specifically described below with reference to fig. 4 to 9.
Referring first to fig. 6 and 7, a substrate 1 is provided.
The material of the substrate 1 in this embodiment includes, but is not limited to, silicon, germanium, silicon germanium, or the like, which is not particularly limited in this embodiment. In addition, an isolation structure or other structures may be formed in the substrate 1, which is not particularly limited in this embodiment.
Referring to fig. 4, a device layout 7 is provided, the device layout 7 including a source drain plug trench pattern 61 and an initial gate plug trench pattern 41.
Referring to fig. 6 and 7, a gate structure 4 and a dielectric layer 2 covering the top and sides of the gate structure 4 are formed on a substrate 1, and the dielectric layer 2 has source and drain plug trenches 6 therein corresponding to the source and drain plug trench patterns 61 on both sides of the gate structure 4.
Preferably, the dielectric layer 2 in this embodiment is an oxide layer, and may specifically be a material such as silicon oxide or silicon dioxide, which is not limited in this embodiment.
With continued reference to fig. 6 and 7, a planarization layer 3 is formed in the source drain plug trench 6 and on the dielectric layer 2, and the planarization layer 3 on the dielectric layer 2 has a difference in thickness.
Specifically, in this embodiment, the planarization layer 3 is a spin-on carbon layer (SOC), and those skilled in the art may select other planarization layer materials according to actual needs, which is not specifically limited in this embodiment.
The difference in thickness of the planarization layer 3 on the dielectric layer 2 means that the thickness of the planarization layer 3 corresponding to the region where the source drain plug trench 6 is sparse and the region where the source drain plug trench 6 is dense is specifically different. For example, in fig. 6, the source-drain plug grooves 6 are dense, the planarization layer 3 is thinner, and in fig. 7, the source-drain plug grooves 6 are sparse, and the planarization layer 3 is thicker.
Referring to fig. 5, on the device layout 7, the source-drain plug trench 6 patterns in the threshold region around each initial gate plug trench pattern 41 are scanned, respectively, so as to obtain the density parameters of each initial gate plug trench pattern 41.
Specifically, the density parameter of the initial gate plug trench pattern 41 in this embodiment refers to the ratio of the sum of the areas of the source and drain plug trench patterns to the area of the threshold region in the area around the initial gate plug trench pattern 41.
The size of the threshold area can be determined by one skilled in the art according to actual requirements, and the threshold area size is different for devices of different sizes.
The upper half of fig. 4 and 5 shows a region a where the density of the source-drain plug grooves 6 is high, and the lower half of fig. 4 shows a region B where the density of the source-drain plug grooves 6 is low.
It should be noted that, fig. 4 and fig. 5 only schematically illustrate a method for forming the semiconductor device according to this embodiment by taking one initial gate plug slot pattern 41 as an example, and in fact, a plurality of initial gate plug slot patterns 41 may be included in the device layout 7, and the method is the same for each initial gate plug slot pattern 41.
In this embodiment, the initial gate plug trench pattern 41 is only schematically shown as a square, and in this embodiment, the initial gate plug trench pattern 41 is taken as a square as an example. In fact, in other embodiments of the present invention, the projected shape of the initial gate plug trench pattern 41 on the substrate 1 is polygonal, elliptical, or rectangular.
More specifically, in this embodiment, the method for scanning the source-drain plug trench patterns 61 around the threshold region of each initial gate plug trench pattern 41 to obtain the density parameter of each initial gate plug trench pattern 41 includes the following steps:
firstly, scanning source-drain plug slot patterns 61 in a threshold area of an initial gate plug slot pattern 41 with each edge point of the initial gate plug slot pattern 41 as a scanning center and a threshold scanning radius to obtain scanned source-drain plug slot patterns 61a corresponding to each initial gate plug slot pattern 41;
then, the density parameter of each initial gate plug pattern 41 is obtained from the ratio of the area of each scan source drain plug pattern 61a to the area of the corresponding threshold region.
More specifically, the method comprises the steps of, wherein ,Di The density parameter of the i-th initial gate plug pattern 41 is i, which is an integer of 2 or more.
The area of the scan source drain plug pattern 61a corresponding to the i-th initial gate plug pattern 41 is set to be n, which is an integer of 1 or more.
D total i is the area of the threshold region corresponding to the i-th initial gate plug trench pattern 41.
The scan source drain plug slot pattern 61a corresponding to the i-th initial gate plug slot pattern 41 includes n sub-scan source drain plug slots 6; f (k) i The area of the kth sub-scanning source-drain plug slot corresponding to the ith initial gate plug slot pattern 41 is k, which is an integer greater than or equal to 1 and less than or equal to n.
And when the projection shape of the ith initial gate plug groove pattern 41 on the substrate 1 is square,
wherein R is a threshold scanning radius;
is the feature size of the i-th initial gate plug trench pattern 41.
When the projected shape of the substrate 1 is another shape, the initial gate plug pattern 41 is different from the projected shape in that the area size of the threshold region is square. For example, when the projection shape of the initial gate plug groove pattern 41 on the substrate 1 is rectangular, the size of the threshold region is an area that can be decomposed into four rectangles and one ellipse; when the projected shape of the initial gate plug groove pattern 41 on the substrate 1 is circular, the size of the threshold region is the area of the circular ring on the circular periphery side. The size of the threshold area can be calculated according to different shapes by those skilled in the art, and this embodiment will not be described herein.
With continued reference to fig. 5, each initial gate plug trench pattern 41 is compensated according to the density parameter to obtain a gate plug trench correction pattern 42, and the feature size of the gate plug trench correction pattern 42 decreases with the increase of the density parameter.
That is, in the threshold region, the larger the area ratio of the source-drain plug trench pattern 61 means the greater the density of the source-drain plug trenches 6 and the thinner the planarization layer 3. The thinner the planarization layer 3, the shorter the time required for etching, and the problem of over-etching is likely to occur when the gate plug groove is etched. Therefore, the feature size of the gate plug trench correction pattern 42 is reduced, and the time for etching the dielectric layer 2 and the planarization layer 3 can be prolonged, so that the problem of overetching during the etching of the gate plug trench can be avoided.
Further, in the threshold region, the smaller the area ratio of the source-drain plug trench pattern 61, the smaller the density of the source-drain plug trenches 6, the more sparse, and the thicker the planarization layer 3. The thicker the planarization layer 3, the longer the etching time is, and the problem of insufficient etching is likely to occur when the gate plug groove is etched. Therefore, the feature size of the gate plug trench correction pattern 42 is increased, and the time for etching the dielectric layer 2 and the planarization layer 3 can be shortened, so that the problem of insufficient etching during the formation of the gate plug trench by etching can be avoided.
Specifically, in this embodiment, according to the density parameter, the method for compensating each initial gate plug trench pattern 41 to obtain the gate plug trench correction pattern 42 includes the following steps:
first, the compensation amount of each initial gate plug pattern 41 is obtained according to the density parameters of the initial gate plug pattern 41 in different regions.
Specifically, the compensation amount can be understood as a difference between areas of the initial gate plug trench pattern 41 and the gate plug trench correction pattern 42, and a hatched portion on the circumferential side of the initial gate plug trench pattern 41 in fig. 5.
Then, the gate plug trench correction pattern 42 is obtained from each of the initial gate plug trench patterns 41 and the corresponding compensation amounts.
More specifically, the process is carried out, wherein ,/>D for the feature size of the ith initial gate plug trench pattern 41 i For the density parameter of the ith initial gate plug pattern 41, f (D i ) Compensation amount corresponding to the ith initial gate plug slot pattern 41, +.>The feature size of the pattern 42 is corrected for the ith gate plug trench, i being an integer of 2 or more.
It should be noted that, in the present embodiment, the method for obtaining the compensation amount of each initial gate plug pattern 41 according to the density parameters of the initial gate plug pattern 41 in different regions includes the following steps:
firstly, the slope of the curve function of the density parameter of the initial grid plug groove pattern of different areas along with the position change of the initial grid plug groove pattern is obtained.
Next, a zero-compensation initial gate plug slot pattern is obtained in the initial gate plug slot pattern 41 of the different region.
And then, acquiring a zero compensation point density parameter corresponding to the zero compensation initial grid plug slot pattern.
Then, the compensation amount of each initial gate plug pattern 41 is obtained according to the slope, the density parameter of each initial gate plug pattern 41, and the zero compensation area density parameter.
Specifically, f (D i )＝-|k|(D i -D i0 ) Wherein k is the slope, D i0 The zero compensation point density parameter.
It should be further noted that, in this embodiment, the method for obtaining the zero compensation initial gate plug slot pattern includes:
a test substrate is provided.
Specifically, the materials and structures of the test substrate are not substantially different from those of the substrate 1, and the present embodiment is not described herein.
And forming a test gate structure and a test dielectric layer covering the top and the side parts of the test gate structure on the test substrate, wherein the test dielectric layer is provided with test source drain plug grooves positioned on two sides of the test gate structure.
And forming a test flat layer in the test source drain plug groove and on the test dielectric layer, wherein the thickness of the test flat layer on the test dielectric layer is different.
A test photoresist layer is formed on the test planarization layer based on the initial gate plug trench pattern.
And etching the test flat layer and the test dielectric layer by taking the test photoresist layer as a mask, and forming a test gate plug groove positioned on the test gate structure in the test dielectric layer.
Acquiring a zero compensation test gate plug groove according to the shapes of the test gate plug grooves in different areas;
and obtaining a corresponding zero compensation initial gate plug groove pattern according to the zero compensation test gate plug groove.
Specifically, the etching conditions of the test flat layer and the test dielectric layer by using the test photoresist layer as a mask are identical to the etching conditions of the flat layer 3 and the dielectric layer 2 by using the patterned photoresist layer as a mask.
The process of etching the test flat layer and the test dielectric layer by using the test photoresist layer as a mask is an anisotropic dry etching process, and the process of etching the flat layer 3 and the dielectric layer 2 by using the patterned photoresist layer 5 as a mask is an anisotropic dry etching process.
Preferably, the etching conditions in this embodiment include etching gas, gas flow, chamber pressure, source rf power, and bias power.
Referring to fig. 4, 5, 6 and 7, a patterned photoresist layer 5 is formed on the planarization layer 3 based on the gate plug trench correction pattern 42.
Further, the patterned photoresist layer 5 is used as a mask to etch the planarization layer 3 and the dielectric layer 2, and a gate plug groove on the gate structure 4 is formed in the dielectric layer 2.
In this embodiment, as shown in fig. 8 and 9, a protective layer 21 is further formed in the dielectric layer 2 to cover the gate structure 4.
Further, the source-drain plug trench 6 may penetrate the protection layer 21, and the gate plug trench may also penetrate the protection layer 21.
Preferably, the material of the protective layer 21 in this embodiment may be silicon nitride or other materials, which is not specifically limited in this embodiment.
By adopting the scheme, the source and drain plug slot patterns in the threshold area around each initial gate plug slot pattern are scanned on the device layout respectively, so that the density parameters of each initial gate plug slot pattern are obtained. By obtaining the density parameter, the ratio of the sum of the areas of the source drain plug groove patterns in the threshold area to the area of the threshold area can be obtained. And then respectively compensating each initial grid plug groove pattern according to the density parameters to obtain a grid plug groove correction pattern. And the feature size of the gate plug trench modification pattern decreases with increasing density parameter. And forming a patterned photoresist layer according to the grid plug groove correction pattern, and etching the flat layer and the dielectric layer to form the grid plug groove. That is, in the region where the density of the source-drain plug grooves is large, by reducing the feature size of the gate plug groove correction pattern, the rate of etching the dielectric layer and the planarizing layer can be reduced, so that the problem of overetching occurring when forming the gate plug groove by etching can be avoided. In the region with smaller density of the source and drain plug grooves, the characteristic size of the grid plug groove correction pattern is increased, so that the speed of etching the dielectric layer and the flat layer can be increased, and the problem of insufficient etching when the grid plug grooves are formed by etching can be avoided. Thus, although the regions of the source-drain plug trenches having a larger density have a difference from the planar layer thickness on the dielectric layer of the regions of the source-drain plug trenches having a smaller density, the end points of the etched dielectric layer and the planar layer are the same. This results in a more uniform topography of the resulting gate plug and better performance of the semiconductor device.
While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing is a further detailed description of the invention with reference to specific embodiments, and it is not intended to limit the practice of the invention to those descriptions. Various changes in form and detail may be made therein by those skilled in the art, including a few simple inferences or alternatives, without departing from the spirit and scope of the present invention.
Claims (9)
1. A method of forming a semiconductor device, comprising:
providing a substrate;
providing a device layout, wherein the device layout comprises a source-drain plug slot pattern and an initial grid plug slot pattern;
forming a gate structure and a dielectric layer covering the top and the side of the gate structure on the substrate, wherein the dielectric layer is provided with source-drain plug grooves which are positioned at two sides of the gate structure and correspond to the source-drain plug groove patterns;
forming a flat layer in the source drain plug groove and on the dielectric layer, wherein the thickness of the flat layer on the dielectric layer is different;
scanning the source and drain plug slot patterns in the threshold area around each initial gate plug slot pattern on the device layout respectively, so as to obtain density parameters of each initial gate plug slot pattern;
respectively compensating each initial grid plug groove pattern according to the density parameters to obtain a grid plug groove correction pattern, wherein the characteristic size of the grid plug groove correction pattern is reduced along with the increase of the density parameters;
forming a patterned photoresist layer on the planar layer based on the gate plug trench correction pattern;
etching the flat layer and the dielectric layer by taking the patterned photoresist layer as a mask, and forming a gate plug groove positioned on the gate structure in the dielectric layer;
the method for respectively scanning the source and drain plug slot patterns in the threshold area around each initial gate plug slot pattern so as to obtain the density parameter of each initial gate plug slot pattern comprises the following steps:
scanning the source drain plug slot patterns in the threshold area of the initial gate plug slot patterns by taking each edge point of the initial gate plug slot patterns as a scanning center and using a threshold scanning radius to obtain scanning source drain plug slot patterns corresponding to each initial gate plug slot pattern;
and obtaining the density parameter of each initial grid electrode plug groove pattern according to the ratio of the area of each scanning source drain plug groove pattern to the area of the corresponding threshold region.
2. The method of forming a semiconductor device according to claim 1, wherein,
wherein ,Di The density parameter of the ith initial grid plug groove pattern is i, wherein i is an integer greater than or equal to 2;
the area of the scanning source drain plug groove pattern corresponding to the ith initial gate plug groove pattern is the area of the scanning source drain plug groove pattern, and n is an integer greater than or equal to 1;
D total i is the area of the threshold region corresponding to the ith initial gate plug slot pattern;
the scanning source drain plug groove pattern corresponding to the ith initial grid plug groove pattern comprises n sub-scanning source drain plug grooves; f (k) i The area of the source and drain plug grooves is scanned for the kth sub-corresponding to the ith initial grid plug groove pattern, and k is an integer greater than or equal to 1 and less than or equal to n.
3. The method of forming a semiconductor device of claim 2, wherein when the projected shape of the ith initial gate plug trench pattern on the substrate is square,
wherein R is a threshold scanning radius;
is the feature size of the ith initial gate plug trench pattern.
4. The method of forming a semiconductor device of claim 1, wherein compensating each of said initial gate plug trench patterns based on said density parameter, respectively, to obtain said gate plug trench correction pattern comprises:
acquiring compensation amounts of the initial gate plug slot patterns according to density parameters of the initial gate plug slot patterns in different areas;
obtaining a grid plug groove correction pattern according to each initial grid plug groove pattern and the corresponding compensation quantity;
wherein ,for the feature size of the ith initial gate plug trench pattern, D i For the density parameter of the ith initial gate plug pattern, f (D i ) Compensation amount corresponding to the ith initial gate plug slot pattern, < >>And correcting the characteristic dimension of the pattern for the ith grid plug slot, wherein i is an integer greater than or equal to 2.
5. The method of forming a semiconductor device of claim 4, wherein the method of obtaining the compensation amount of each of the initial gate plug trench patterns according to the density parameters of the initial gate plug trench patterns of different regions comprises:
acquiring the slope of a curve function of the density parameter of the initial gate plug slot pattern of different areas along with the position change of the initial gate plug slot pattern;
acquiring zero compensation initial gate plug slot patterns from the initial gate plug slot patterns in different areas;
acquiring a zero compensation point density parameter corresponding to the zero compensation initial grid plug slot pattern;
acquiring compensation amounts of the initial gate plug slot patterns according to the slope, the density parameters of the initial gate plug slot patterns and the zero compensation point density parameters;
f(D i )＝-|k|(D i -D i0 )
wherein k is the slope, D i0 And (5) the compensation point density parameter is zero.
6. The method of forming a semiconductor device of claim 5, wherein the method of obtaining the zero-compensation initial gate plug trench pattern comprises:
providing a test substrate;
forming a test gate structure and a test medium layer covering the top and the side of the test gate structure on the test substrate, wherein the test medium layer is provided with test source-drain plug grooves positioned on two sides of the test gate structure;
forming a test flat layer in the test source drain plug groove and on the test dielectric layer, wherein the thickness of the test flat layer on the test dielectric layer is different;
forming a test photoresist layer on the test planarization layer based on the initial gate plug slot pattern;
etching the test flat layer and the test dielectric layer by taking the test photoresist layer as a mask, and forming a test gate plug groove positioned on the test gate structure in the test dielectric layer;
acquiring a zero compensation test gate plug groove according to the shapes of the test gate plug grooves in different areas;
and obtaining a corresponding zero compensation initial gate plug groove pattern according to the zero compensation test gate plug groove.
7. The method of claim 6, wherein etching conditions for etching the test planarization layer and the test dielectric layer using the test photoresist layer as a mask are identical to etching conditions for etching the planarization layer and the dielectric layer using the patterned photoresist layer as a mask.
8. The method of claim 7, wherein the process of etching the test planarization layer and the test dielectric layer using the test photoresist layer as a mask is an anisotropic dry etching process, and the process of etching the planarization layer and the dielectric layer using the patterned photoresist layer as a mask is an anisotropic dry etching process;
the etching conditions include etching gas, gas flow, chamber pressure, source rf power, and bias power.
9. The method of forming a semiconductor device of claim 1, wherein a projected shape of said initial gate plug trench pattern on said substrate is any one of polygonal, elliptical, rectangular.
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| US5789300A (en) * | 1997-02-25 | 1998-08-04 | Advanced Micro Devices, Inc. | Method of making IGFETs in densely and sparsely populated areas of a substrate |
| US5804498A (en) * | 1995-06-23 | 1998-09-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making an underlayer to reduce pattern sensitivity of ozone-TEOS |
| US6489083B1 (en) * | 2000-10-02 | 2002-12-03 | Motorola, Inc. | Selective sizing of features to compensate for resist thickness variations in semiconductor devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5804498A (en) * | 1995-06-23 | 1998-09-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making an underlayer to reduce pattern sensitivity of ozone-TEOS |
| US5789300A (en) * | 1997-02-25 | 1998-08-04 | Advanced Micro Devices, Inc. | Method of making IGFETs in densely and sparsely populated areas of a substrate |
| US6489083B1 (en) * | 2000-10-02 | 2002-12-03 | Motorola, Inc. | Selective sizing of features to compensate for resist thickness variations in semiconductor devices |
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