CN113496948B - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the same Download PDFInfo
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- CN113496948B CN113496948B CN202010190883.2A CN202010190883A CN113496948B CN 113496948 B CN113496948 B CN 113496948B CN 202010190883 A CN202010190883 A CN 202010190883A CN 113496948 B CN113496948 B CN 113496948B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 97
- 238000000034 method Methods 0.000 title claims abstract description 56
- 238000005530 etching Methods 0.000 claims abstract description 32
- 238000002955 isolation Methods 0.000 claims description 58
- 239000000758 substrate Substances 0.000 claims description 35
- 230000004888 barrier function Effects 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 13
- 230000008569 process Effects 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 230000008021 deposition Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 125000004122 cyclic group Chemical group 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention provides a semiconductor device and a forming method thereof, wherein the forming method of the semiconductor device comprises the following steps: forming an initial gate structure crossing the fin part on the first region, the second region and the cutting region; forming a mask layer with a mask opening on the initial gate structure, wherein the mask opening also extends to a fin part adjacent to the cutting region; etching part of the initial gate structure at the bottom of the mask opening by taking the mask layer as a mask to form an initial trench; forming a side wall on the side wall of the initial groove; and etching the initial gate structure at the bottom of the initial trench by taking the side wall and the mask layer as masks, so that the initial trench forms a gate cutting trench, and the gate cutting trench divides the initial gate structure into gate structures positioned at two sides of the gate cutting trench. By adopting the scheme, the position of the initial groove is limited by using the mask layer with the mask opening, the position of the grid cutting groove is limited by using the side wall, the grid cutting groove cannot displace, the stress on the fin parts at two sides is equal, and the performance of the semiconductor device is better.
Description
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor device and a method for forming the same.
Background
As critical dimensions of semiconductor devices decrease, fin field effect transistors (finfets) are increasingly being used in place of planar devices in integrated circuit fabrication processes. In a FinFET, a gate barrier formed in a gate is important, and the gate barrier is related to the performance of the device such as leakage current, driving current, and the like.
Therefore, in the manufacturing process of a semiconductor integrated circuit, etching a metal gate to form a gate cutting trench is a very important step. The location and width of the gate cut trench determines the location and size of the gate barrier, which in turn affects the performance of the semiconductor device.
Currently, in the process of etching a metal gate to form a gate cutting trench, there is a problem that a position where the gate cutting trench is finally formed is offset from a position where the gate cutting trench is initially set, so that distances from the gate cutting trench to fin portions on two sides are not equal, and therefore, voltage of a device is affected due to stress influence, and performance of a semiconductor device is further affected.
Disclosure of Invention
The invention aims to solve the problem that in the prior art, the semiconductor device has poor performance due to the influence of stress on the device voltage caused by unequal distances from a finally formed gate cutting groove to fin parts on two sides.
The invention provides a semiconductor device and a forming method thereof, wherein the semiconductor device formed by the forming method of the semiconductor device has symmetrical distances from a grid cutting groove to fin parts on two sides, and the semiconductor device has better performance.
To solve the above technical problems, an embodiment of the present invention discloses a method for forming a semiconductor device, including: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region, a second region and a cutting region positioned between the first region and the second region;
forming a plurality of discrete fin portions on the first region and the second region of the semiconductor substrate, respectively;
forming an initial gate structure crossing the fin portion on the first region, the second region and the cutting region;
forming a mask layer on the initial gate structure, wherein the mask layer is provided with a mask opening positioned on a cutting region, and the mask opening also extends to the fin part adjacent to the cutting region;
etching part of the initial gate structure at the bottom of the mask opening by taking the mask layer as a mask, forming an initial groove in the initial gate structure, wherein the bottom surface of the initial groove exposes part of the top surface of the fin part;
forming a side wall on the side wall of the initial groove, wherein the side wall is positioned on the top surface of part of the fin part;
and etching the initial gate structure at the bottom of the initial trench by taking the side wall and the mask layer as masks so as to enable the initial trench to form a gate cutting trench, wherein the gate cutting trench divides the initial gate structure into gate structures positioned at two sides of the gate cutting trench.
Optionally, the method further comprises: after forming a grid electrode cutting groove, removing the side wall; and after the side wall is removed, forming a gate barrier in the gate cutting groove.
Optionally, the method further comprises: forming an isolation structure on the semiconductor substrate at the side part of the fin part before forming the initial gate structure; after forming the initial gate structure, the initial gate structure is also located on the isolation structure; etching the isolation structure with partial thickness at the bottom of the gate cutting groove before removing the side wall, and forming an isolation opening in the isolation structure; the gate barrier is also formed in the isolation opening.
Optionally, the initial gate structure is etched by an anisotropic dry etching process to form the initial trench.
Optionally, the process of etching the initial gate structure at the bottom of the initial trench with the sidewall and the mask layer as masks includes: wet etching process.
Optionally, the method for etching the isolation structure with a partial thickness of the bottom of the gate cutting trench to form the isolation opening includes: and (5) circularly etching.
Optionally, the material of the side wall includes silicon nitride or silicon oxide.
Optionally, the thickness of the side wall is 20 to 50 angstroms.
Optionally, the bottom surface of the initial trench is flush with the top surface of the fin.
Optionally, the material of the gate barrier includes silicon nitride or silicon oxide.
Optionally, the isolation opening has a depth of 100 angstroms to 200 angstroms.
Optionally, the initial gate structure is a metal gate structure or a dummy gate structure.
The embodiment of the invention also discloses a semiconductor device, which comprises:
a semiconductor substrate including a first region, a second region, and a dicing region between the first region and the second region;
a plurality of discrete fins located on the first region and the second region of the semiconductor substrate;
and the gate structure is respectively positioned on the first region and the second region and spans the fin part, and the gate cutting groove is positioned on the cutting region and exposes one side wall and the top surface of the adjacent fin part.
Optionally, the method further comprises: and the side wall is positioned on the side wall at the top of the gate cutting groove and is positioned on the top surface of part of the fin part.
Optionally, the material of the side wall includes silicon nitride or silicon oxide.
Optionally, the thickness of the side wall is 20 to 50 angstroms.
Optionally, the method further comprises: and the gate barrier is positioned in the gate cutting groove and is contacted with the side part of the adjacent fin part.
Optionally, the method further comprises: an isolation structure formed on the semiconductor substrate at the side part of the fin part, wherein an isolation opening which is positioned on the cutting area and is communicated with the grid cutting groove is formed in the isolation structure; the grid structure is also positioned on the isolation structure; the gate barrier is also located in the isolation opening.
The invention has the beneficial effects that: according to the method for forming the semiconductor device, the mask layer with the mask opening is formed on the initial gate structure, and then the mask layer is used as a mask to etch part of the initial gate structure at the bottom of the mask opening, so that the initial groove is formed, the position of the initial groove is limited by the mask layer and cannot move, and the width of the initial groove in the direction perpendicular to the semiconductor substrate cannot change. And forming a side wall on the side wall of the initial trench, and etching the initial gate structure at the bottom of the initial trench by taking the side wall and the mask layer as masks, so that the initial trench forms a gate cutting trench. The position of the formed grid cutting groove is not moved due to the limitation of the side wall, and the width of the grid cutting groove in the direction vertical to the semiconductor substrate is not changed. Therefore, the distance from the gate cutting groove to the fin parts and the gate structure on two sides is symmetrical. Further, the stress of the grid cutting groove on the fin parts on the two sides is equal to that of the grid structure, the voltage between the grid cutting groove and the fin parts on the two sides is also equal, the semiconductor device cannot be affected by the stress and the voltage difference, and the performance is better.
Drawings
Fig. 1 is a schematic configuration view of a forming method of a semiconductor device;
fig. 2 is a flowchart of a method for forming a semiconductor device according to an embodiment of the present invention;
fig. 3 to 8 are schematic structural views corresponding to a method for forming a semiconductor device according to an embodiment of the present invention.
Detailed Description
Further advantages and effects of the present invention will become apparent to those skilled in the art from the disclosure of the present specification, by describing the embodiments of the present invention with specific examples. While the description of the invention will be described in connection with the preferred embodiments, it is not intended to limit the inventive features to the implementation. Rather, the purpose of the invention described in connection with the embodiments is to cover other alternatives or modifications, which may be extended by the claims based on the invention. The following description contains many specific details for the purpose of providing a thorough understanding of the present invention. The invention may be practiced without these specific details. Furthermore, some specific details are omitted from the description in order to avoid obscuring the invention. It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.
It should be noted that in this specification, like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present embodiment, it should be noted that the azimuth or positional relationship indicated by the terms "upper", "lower", "inner", "bottom", etc. are based on the azimuth or positional relationship shown in the drawings, or the azimuth or positional relationship in which the inventive product is conventionally put in use, are merely for convenience of describing the present invention and simplifying the description, and are not indicative or implying that the apparatus or element to be referred to must have a specific azimuth, be configured and operated in a specific azimuth, and therefore should not be construed as limiting the present invention.
The terms "first," "second," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.
In the description of the present embodiment, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present embodiment can be understood in a specific case by those of ordinary skill in the art.
As described in the background art, in the process of etching a metal gate to form a gate cutting trench, there is a problem that a position where the gate cutting trench is finally formed is deviated from a position where the gate cutting trench is initially set. Specifically, the method of forming a semiconductor device in the prior art is as follows: providing a semiconductor substrate, forming a plurality of discrete fin portions on the semiconductor substrate, and forming an initial gate structure across the fin portions. The initial gate structure is then etched to form a gate cut trench, and gate structures located on both sides of the gate cut trench, and a gate barrier is deposited within the gate cut trench.
As shown in fig. 1, the offset of the initial gate structure 5 in forming the gate structure 53 may shift the gate cutting trench position, so that the distance between the gate barrier 9 and the fin portions 4 on both sides is not equal. Thus, the stress of the fin 4 on both sides of the gate barrier 9 on the gate barrier 9 is different, and the voltage between the fin 4 and the gate barrier 9 is also different, which affects the performance of the semiconductor device.
To solve the above-mentioned problems, an embodiment of the present invention provides a method for forming a semiconductor device, specifically, a flowchart of a method for forming a semiconductor device shown in fig. 2, the method for forming a semiconductor device includes the following steps:
step S1: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region, a second region and a cutting region positioned between the first region and the second region;
step S2: forming a plurality of discrete fin portions on the first region and the second region of the semiconductor substrate respectively;
step S3: forming an initial gate structure crossing the fin part on the first region, the second region and the cutting region;
step S4: forming a mask layer on the initial gate structure, wherein the mask layer is provided with a mask opening positioned on the cutting region, and the mask opening also extends to a fin part adjacent to the cutting region;
step S5: etching part of the initial gate structure at the bottom of the mask opening by taking the mask layer as a mask, forming an initial trench in the initial gate structure, and exposing the top surface of part of the fin part from the bottom surface of the initial trench;
step S6: forming a side wall on the side wall of the initial groove, wherein the side wall is positioned on the top surface of part of the fin part;
step S7: and etching the initial gate structure at the bottom of the initial trench by taking the side wall and the mask layer as masks, so that the initial trench forms a gate cutting trench, and the gate cutting trench divides the initial gate structure into gate structures positioned at two sides of the gate cutting trench.
The semiconductor device formed by the method has the advantages that the distances from the gate cutting groove to the fin parts on the two sides are equal, the stress of the fin parts on the gate barrier is the same, the voltages between the fin parts and the gate barrier are also the same, and the performance of the semiconductor device is better.
The method for forming a semiconductor device according to the present embodiment is specifically described below with reference to structural diagrams corresponding to the method for forming a semiconductor device shown in fig. 3 to 8.
As shown in fig. 3, a semiconductor substrate (not shown in the drawing) is provided, which includes a first region 1, a second region 2, and a dicing region 3 located between the first region 1 and the second region 2.
The materials of the semiconductor substrate in this embodiment include, but are not limited to, silicon oxide, germanium, and other commonly used materials of semiconductor substrates, which are not exemplified herein.
With continued reference to fig. 3, a number of discrete fins 4 are formed on the first region 1 and the second region 2, respectively, of the semiconductor substrate.
In this embodiment, the isolation structure 8 is further formed on the semiconductor substrate at the side of the fin portion 4.
Specifically, the isolation structure 8 includes, but is not limited to, a shallow trench isolation structure (STI, shallow Trench Isolation) or other isolation structures, which is not particularly limited in this embodiment.
With continued reference to fig. 3, an initial gate structure 5 is formed across the fin 4 over the first region 1, the second region 2 and the cut region 3.
Note that the initial gate structure 5 in this embodiment is located on the isolation structure 8.
With continued reference to fig. 3, a mask layer 6 is formed over the initial gate structure 5, the mask layer 6 having mask openings 61 therein located over the cut regions 3, and the mask openings 61 also extending over the fins 4 adjacent to the cut regions 3.
Specifically, in this embodiment, the method for forming the mask opening 61 includes, but is not limited to, forming a photoresist layer 62 on the mask layer 6, forming a photoresist layer opening 63 on the photoresist layer 62, extending the photoresist layer opening 63 to the fin portion 4 adjacent to the dicing area 3, and etching the mask layer 6 at the bottom of the photoresist layer opening 63 by using the photoresist layer 62 as a pattern to form the mask opening 61 in the mask layer 6, as shown in fig. 3.
Referring to fig. 4, a portion of the initial gate structure 5 at the bottom of the mask opening 61 is etched using the mask layer 6 as a mask, an initial trench 51 is formed in the initial gate structure 5, and a bottom surface of the initial trench 51 exposes a top surface of a portion of the fin 4.
Preferably, the present embodiment etches the initial gate structure 5 by an anisotropic dry etching process to form the initial trench 51.
It should be noted that, in this embodiment, the bottom surface of the initial trench 51 is flush with the top surface of the fin 4.
In this embodiment, the bottom surface of the initial trench 51 exposing the top surface of the fin portion 4 means that the initial trench 51 may expose the right side of the top of the fin portion 4 located at the left side of the cutting region 3 in fig. 4, and the left side of the top of the fin portion 4 is covered by the initial gate structure 5; and the left side of the top of the fin 4 to the right of the cut region 3 is exposed and the right side of the top of the fin 4 is covered by the initial gate structure 5.
Referring to fig. 5, a sidewall 7 is formed on the sidewalls of the initial trench 51 and the mask opening 61, and the sidewall 7 is located on the top surface of a portion of the fin 4.
Preferably, in this embodiment, the material of the side wall 7 includes silicon nitride or silicon oxide. And the thickness of the sidewall 7 is 20 to 50 a. Specifically, the thickness of the sidewall 7 may be 20 a, 25 a, 30 a, 35 a, 40 a, 45 a, 50 a, or other values, which are not limited in this embodiment.
It should be noted that before forming the sidewall 7 by the sidewalls of the initial trench 51 and the mask opening 61, the photoresist layer 62 is removed.
Referring to fig. 6, the initial gate structure 5 at the bottom of the initial trench 51 is etched using the sidewall 7 and the mask layer 6 as a mask, so that the initial trench 51 forms a gate cutting trench 52, and the gate cutting trench 52 divides the initial gate structure 5 into gate structures 53 located at both sides of the gate cutting trench 52.
Note that the gate structure 53 in this embodiment is a metal gate structure or a dummy gate structure.
Note that the gate cutting trench 52 in the present embodiment is a structure formed in the initial gate structure 5 for cutting the initial gate structure 5 into the gate structure 53. And the gate cutting trench 52 penetrates the initial gate structure 5 in a direction perpendicular to the semiconductor substrate.
Preferably, in this embodiment, the process of etching the initial gate structure 5 at the bottom of the initial trench 51 by using the sidewall 7 and the mask layer 6 as masks includes a wet etching process.
In this embodiment, a wet etching process with a relatively high selection ratio is adopted, when the initial gate structure 5 at the bottom of the initial trench 51 is etched, the initial gate structure 5 at the bottom of the initial trench 51 can be well removed, and meanwhile, the fin portion 4 below the initial gate structure 5 is less affected, so that the etching of the fin portion 4 can be reduced or avoided.
Referring to fig. 7, the isolation structure 8 of a partial thickness of the bottom of the gate cutting trench 52 is etched, and an isolation opening 81 is formed in the isolation structure 8.
Preferably, in this embodiment, the method for etching the isolation structure 8 with a partial thickness of the bottom of the gate cutting trench 52 to form the isolation opening 81 includes: and (5) circularly etching.
Specifically, the method of cyclic etching in the present application includes, but is not limited to: first, a first deposition step is performed to form a deposition layer protecting the fin portion 4, the mask layer 6 and the sidewalls of the sidewall 7 on the inner surfaces of the mask layer 6 and the gate cutting trench 52, and the inner surface of the sidewall 7, and then a first etching step is performed to etch the isolation structure 8 at the bottom of the gate cutting trench 52, and the isolation structure 8 is etched down to a certain depth. The first deposition step and the first etching step are then repeated to form isolation openings 81 in the isolation structures 8.
Further, the first deposition step may employ a gas for generating a polymer deposition layer, such as C4F8, and the first etching step may employ an etching-based gas, such as SF6, which may be specifically selected as needed.
In this embodiment, a cyclic etching manner is adopted, fin portions 4 on two sides of an isolation opening 81 can be protected from being etched, and the isolation structure 8 is etched step by step and circularly, so that the isolation opening 81 with a good shape can be obtained, filling of a subsequent gate barrier 9 is facilitated, process quality is improved, and the isolation opening 81 with a special shape as shown in fig. 7 can be obtained for manufacturing the gate barrier 9 with the special shape.
Preferably, the isolation opening 81 has a depth of 100 angstroms to 200 angstroms.
The depth of the isolation opening 81 refers to the distance between the bottom of the isolation opening 81 and the plane in which the top of the isolation opening 81 is located. The depth of the isolation opening 81 may be 100 a, 120 a, 140 a, 160 a, 180 a, 200 a, or other values, which are not particularly limited in this embodiment.
Referring to fig. 8, after forming the gate cutting trench 52, the side wall 7 is removed; after removal of the side walls 7, gate barriers 9 are formed in the gate cutting trenches 52.
Note that the gate barrier 9 in this embodiment is also formed in the isolation opening 81.
Preferably, the material of the gate barrier 9 comprises silicon nitride or silicon oxide.
According to the method for forming the semiconductor device, the mask layer with the mask opening is formed on the initial gate structure, and then the mask layer is used as a mask to etch part of the initial gate structure at the bottom of the mask opening, so that the initial groove is formed, the position of the initial groove is limited by the mask layer and cannot move, and the width of the initial groove in the direction perpendicular to the semiconductor substrate cannot change. And forming a side wall on the side wall of the initial trench, and etching the initial gate structure at the bottom of the initial trench by taking the side wall and the mask layer as masks, so that the initial trench forms a gate cutting trench. The position of the formed grid cutting groove is not moved due to the limitation of the side wall, and the width of the grid cutting groove in the direction vertical to the semiconductor substrate is not changed. Therefore, the distance from the gate cutting groove to the fin parts and the gate structure on two sides is symmetrical. Further, the stress of the grid cutting groove on the fin parts on the two sides is equal to that of the grid structure, the voltage between the grid cutting groove and the fin parts on the two sides is also equal, the semiconductor device cannot be affected by the stress and the voltage difference, and the performance is better.
Based on the above method for forming a semiconductor device, the present embodiment also provides a semiconductor device, specifically, as shown in fig. 7 and 8. The semiconductor device provided in this embodiment includes:
a semiconductor substrate comprising a first region 1, a second region 2 and a dicing region 3 located between the first region 1 and the second region 2.
The materials of the semiconductor substrate include, but are not limited to, silicon oxide, germanium, and other commonly used materials of semiconductor substrates, to name a few.
The semiconductor device provided in this embodiment further comprises a number of discrete fins 4 located on the first region 1 and the second region 2 of the semiconductor substrate.
The semiconductor device provided in this embodiment further includes a gate structure 53 crossing the fin 4 and located on the first region 1 and the second region 2, respectively, a gate cutting trench 52 located on the cutting region 3, and the gate cutting trench 52 exposes a side wall and a top surface of the adjacent fin 4.
Referring to fig. 7, the semiconductor device provided in this embodiment further includes a sidewall 7 located on a top sidewall of the gate cutting trench and located on a top surface of a portion of the fin 4.
Preferably, the material of the side wall 7 includes silicon nitride or silicon oxide. And the thickness of the sidewall 7 is 20 to 50 a.
Referring to fig. 8, the semiconductor device provided in this embodiment further includes a gate barrier 9 located in the gate cutting trench, and the gate barrier 9 is in contact with the adjacent fin 4 side.
With continued reference to fig. 8, the semiconductor device provided in this embodiment further includes forming an isolation structure 8 on the semiconductor substrate located on the side of the fin portion 4, where the isolation structure 8 has an isolation opening 81 located on the cutting region 3 and penetrating the gate cutting trench; the gate structure is also located on the isolation structure 8; the gate barrier 9 is also located in the isolation opening 81.
The semiconductor device provided by the invention is limited by the side wall, so that the position of the formed grid cutting groove cannot be moved, and the width of the grid cutting groove in the direction vertical to the semiconductor substrate cannot be changed. Therefore, the distance from the gate cutting groove to the fin parts and the gate structure on two sides is symmetrical. Further, the stress of the grid cutting groove on the fin parts on the two sides is equal to that of the grid structure, the voltage between the grid cutting groove and the fin parts on the two sides is also equal, the semiconductor device cannot be affected by the stress and the voltage difference, and the performance is better.
While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing is a further detailed description of the invention with reference to specific embodiments, and it is not intended to limit the practice of the invention to those descriptions. Various changes in form and detail may be made therein by those skilled in the art, including a few simple inferences or alternatives, without departing from the spirit and scope of the present invention.
Claims (18)
1. A method of forming a semiconductor device, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region, a second region and a cutting region positioned between the first region and the second region;
forming a plurality of discrete fin portions on the first region and the second region of the semiconductor substrate, respectively;
forming an initial gate structure crossing the fin portion on the first region, the second region and the cutting region;
forming a mask layer on the initial gate structure, wherein the mask layer is provided with a mask opening positioned on a cutting region, and the mask opening also extends to the fin part adjacent to the cutting region;
etching part of the initial gate structure at the bottom of the mask opening by taking the mask layer as a mask, forming an initial groove in the initial gate structure, wherein the bottom surface of the initial groove exposes part of the top surface of the fin part;
forming a side wall on the side wall of the initial groove, wherein the side wall is positioned on the top surface of part of the fin part;
and etching the initial gate structure at the bottom of the initial trench by taking the side wall and the mask layer as masks so as to enable the initial trench to form a gate cutting trench, wherein the gate cutting trench divides the initial gate structure into gate structures positioned at two sides of the gate cutting trench.
2. The method of forming a semiconductor device according to claim 1, further comprising: after forming a grid electrode cutting groove, removing the side wall; and after the side wall is removed, forming a gate barrier in the gate cutting groove.
3. The method of forming a semiconductor device according to claim 2, further comprising: forming an isolation structure on the semiconductor substrate at the side part of the fin part before forming the initial gate structure; after forming the initial gate structure, the initial gate structure is also located on the isolation structure; etching the isolation structure with partial thickness at the bottom of the gate cutting groove before removing the side wall, and forming an isolation opening in the isolation structure; the gate barrier is also formed in the isolation opening.
4. The method of forming a semiconductor device of claim 1, wherein the initial gate structure is etched by an anisotropic dry etching process to form the initial trench.
5. The method of claim 1, wherein the etching the initial gate structure at the bottom of the initial trench with the sidewall and the mask layer as masks comprises a wet etching process.
6. The method of forming a semiconductor device of claim 3, wherein etching the isolation structure of a partial thickness of the gate cutting trench bottom to form the isolation opening comprises: and (5) circularly etching.
7. The method of forming a semiconductor device of claim 1, wherein the sidewall material comprises silicon nitride or silicon oxide.
8. The method of forming a semiconductor device of claim 1, wherein a thickness of said sidewall is between 20 angstroms and 50 angstroms.
9. The method of forming a semiconductor device of claim 1, wherein a bottom surface of the initial trench is flush with a top surface of the fin.
10. The method of forming a semiconductor device of claim 2, wherein the gate-blocking material comprises silicon nitride or silicon oxide.
11. The method of forming a semiconductor device of claim 3, wherein the isolation opening has a depth of 100 angstroms to 200 angstroms.
12. The method of forming a semiconductor device of claim 1, wherein the gate structure is a metal gate structure or a dummy gate structure.
13. A semiconductor device formed according to the method of forming a semiconductor device according to any one of claims 1 to 12, comprising:
a semiconductor substrate including a first region, a second region, and a dicing region between the first region and the second region;
a plurality of discrete fins located on the first region and the second region of the semiconductor substrate;
and the gate structure is respectively positioned on the first region and the second region and spans the fin part, and the gate cutting groove is positioned on the cutting region and exposes one side wall and the top surface of the adjacent fin part.
14. The semiconductor device according to claim 13, further comprising: and the side wall is positioned on the side wall at the top of the gate cutting groove and is positioned on the top surface of part of the fin part.
15. The semiconductor device of claim 14, wherein the material of the sidewall comprises silicon nitride or silicon oxide.
16. The semiconductor device of claim 14, wherein the sidewall is between 20 angstroms and 50 angstroms thick.
17. The semiconductor device according to claim 13, further comprising: and the gate barrier is positioned in the gate cutting groove and is contacted with the side part of the adjacent fin part.
18. The semiconductor device according to claim 17, further comprising: an isolation structure formed on the semiconductor substrate at the side of the fin part, wherein the isolation structure is provided with an isolation opening which is positioned on the cutting area and penetrates through the grid cutting groove; the grid structure is also positioned on the isolation structure; the gate barrier is also located in the isolation opening.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US10176995B1 (en) * | 2017-08-09 | 2019-01-08 | Globalfoundries Inc. | Methods, apparatus and system for gate cut process using a stress material in a finFET device |
| CN109216354A (en) * | 2017-06-29 | 2019-01-15 | 台湾积体电路制造股份有限公司 | Metal gate structure cutting technique |
| CN109830438A (en) * | 2017-11-23 | 2019-05-31 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109216354A (en) * | 2017-06-29 | 2019-01-15 | 台湾积体电路制造股份有限公司 | Metal gate structure cutting technique |
| US10176995B1 (en) * | 2017-08-09 | 2019-01-08 | Globalfoundries Inc. | Methods, apparatus and system for gate cut process using a stress material in a finFET device |
| CN109830438A (en) * | 2017-11-23 | 2019-05-31 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
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