CN116525534A

CN116525534A - Method for manufacturing semiconductor structure

Info

Publication number: CN116525534A
Application number: CN202210251268.7A
Authority: CN
Inventors: 廖哲贤; 钟暐杰; 田来成; 周良宾
Original assignee: Nanya Technology Corp
Current assignee: Nanya Technology Corp
Priority date: 2022-01-20
Filing date: 2022-03-15
Publication date: 2023-08-01
Also published as: TW202331812A; TWI809671B

Abstract

A method of fabricating a semiconductor structure is provided, comprising etching a substrate according to a hard mask to form a plurality of active regions and a plurality of trenches in the substrate; the first oxide is arranged on the active areas and in the grooves in an atomic layer deposition mode to form a first oxide layer; forming a second oxide layer by disposing the second oxide on the first oxide layer in an in-situ vapor generation manner; the third oxide is arranged on the first oxide layer in a high-quality oxidation mode to form a third oxide layer so as to prevent the active region from being corroded and the area from being reduced.

Description

Method for manufacturing semiconductor structure

Technical Field

The present invention relates to a method for manufacturing a semiconductor structure, and more particularly, to a method for manufacturing a semiconductor structure.

Background

Semiconductor structures are widely used in the electronics industry, and isolation structures in the semiconductor structures are formed between Active Areas (AA) to electrically isolate the active areas. As semiconductor devices become smaller and highly integrated, the pitch of the active regions continues to shrink. Accordingly, the size of the isolation structure also continues to shrink.

However, the reduction of the active area pitch and the reduction of the isolation structure size may cause some problems. For example, during the formation of the isolation structure, the active region tapers and deforms at both ends in a top view, resulting in a reduction in the area of the buried contact (tie capacitor) that can contact the active region. Thus, the prior art is in need of improvement.

Disclosure of Invention

An objective of an embodiment of the present invention is to provide a method for manufacturing a semiconductor structure, so as to achieve the effects of preventing the active region from being corroded and reducing the area.

One embodiment of the present invention provides a method for manufacturing a semiconductor structure, comprising etching a substrate according to a hard mask to form a plurality of active regions and a plurality of trenches in the substrate, wherein the trenches are respectively disposed between the active regions; forming a first oxide layer by atomic layer deposition (atomic layer deposition) of the first oxide on the active regions and in the trenches; disposing a second oxide layer on the first oxide layer in an in-situ vapor generation (in-situ steam generation, ISSG) manner to form a second oxide layer; the third oxide is formed on the first oxide layer by high quality oxidation (high quality oxidation, HQ).

In some embodiments, the first oxide comprises silicon oxide, silicon oxynitride, or a combination thereof.

In some embodiments, the first oxide layer has a thickness of about 2 nanometers to about 4 nanometers.

In some embodiments, the second oxide comprises silicon oxide, silicon oxynitride, or a combination thereof.

In some embodiments, the second oxide layer has a thickness of about 1.5 nanometers to about 3 nanometers.

In some embodiments, the conditions for in situ vapor generation are from about 800 ℃ to about 950 ℃ for from about 5 seconds to about 15 seconds.

In some embodiments, the third oxide comprises silicon oxide, silicon oxynitride, or a combination thereof.

In some embodiments, the thickness of the third oxide layer is about 8 nanometers to about 10 nanometers.

In some embodiments, the conditions of the high quality oxidation regime are from about 500 ℃ to about 750 ℃ for from about 5 minutes to about 15 minutes.

In some embodiments, the third oxide layer is formed on the first oxide layer in a high-quality oxidation manner, and after the step of forming the third oxide layer, each trench includes a bottom and a top, wherein a vertical distance from the top to the bottom is a depth, and the bottom has a width; the ratio of depth to width is 1:5 to 1:20.

in some embodiments, the depth is from about 200 nm to about 300 nm and the width is from about 10 nm to about 60 nm.

Drawings

The various aspects of the invention will be best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various features may not be drawn to scale according to industry standard operating procedures. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. The foregoing and other objects, features, advantages and embodiments of the invention will be apparent from the following description taken in conjunction with the accompanying drawings in which:

fig. 1 is a flow chart of a method of fabricating a semiconductor structure according to some embodiments of the present invention.

Fig. 2-8 are schematic cross-sectional views of various stages in a method of fabricating a semiconductor structure according to various embodiments of the present invention.

Fig. 9 is a top view of a semiconductor structure in accordance with some embodiments of the present invention.

Detailed Description

In order that the detailed description of the invention may be more fully understood, a description of specific embodiments and examples of embodiments of the invention are set forth below, but are not intended to be the only forms of carrying out or using the embodiments of the invention. The embodiments disclosed below may be combined with or substituted for each other as desired, and other embodiments may be added to one embodiment without further description or illustration. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments below. However, embodiments of the invention may be practiced without these specific details.

In addition, spatially relative terms, such as "lower," "upper," and the like, may be used for convenience in describing the relative relationship of one element or feature to another element or feature in the drawings. These spatially relative terms are intended to encompass different orientations of the structure in use or operation in addition to the orientation depicted in the figures. The structure may be otherwise oriented (e.g., rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In this document, the terms "a" and "an" may refer generally to one or more unless the context clearly dictates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "having," when used herein, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

The following examples and experimental examples are set forth to illustrate the method of preparing a semiconductor structure according to the present invention in more detail, but are not intended to limit the invention thereto, as the scope of the invention is defined by the appended claims.

As mentioned in the related art, the top area of the active region may be reduced and deformed during the formation of the isolation structure. Specifically, when the oxide layer is formed by in-situ vapor generation, silicon atoms that erode the active region are converted into silicon dioxide, resulting in a reduced area of the active region, such as an active region that is elliptical in plan view, and has both ends of its major axis that taper and exhibit irregular waves. This results in a reduced area of buried contacts of the link capacitor that can contact the active region. Therefore, the present invention provides a method for manufacturing a semiconductor structure, which can significantly prevent the active region from being eroded and the area from being reduced. Some embodiments of methods of fabricating semiconductor structures are described in detail below.

Although the methods disclosed herein are illustrated below with a series of acts or steps, the order in which the acts or steps are performed should not be construed as a limitation of the present invention. For example, certain operations or steps may be performed in a different order and/or concurrently with other steps. Moreover, not all illustrated operations, steps, and/or features may be required to implement an embodiment of the invention. Furthermore, each operation or step described herein may comprise several sub-steps or actions.

Referring to fig. 1, fig. 1 is a flow chart illustrating a method of fabricating a semiconductor structure according to some embodiments of the present invention. The method 10 begins with step S11, etching the substrate according to the hard mask to form a plurality of active regions and a plurality of trenches in the substrate, wherein the trenches are respectively disposed between the active regions. Next, the method 10 proceeds to step S12, where a first oxide layer is formed by atomic layer deposition of a first oxide on the active regions and in the trenches. Next, the method 10 proceeds to step S13, where a second oxide layer is formed by disposing a second oxide on the first oxide layer in an in-situ vapor generation manner. Next, the method 10 proceeds to step S14, where a third oxide layer is formed by oxidizing the third oxide layer with high quality on the first oxide layer.

Referring now to fig. 2-8, fig. 2-8 are schematic cross-sectional views of various stages in a method of fabricating a semiconductor structure according to various embodiments of the present invention. Referring to fig. 1 to 5, fig. 2 to 5 are drawn according to step S11 of fig. 1. In step S11, the substrate 110 is etched according to the hard mask 120a to form a plurality of active regions 110a and a plurality of trenches 110t in the substrate 110. In fig. 2, a substrate 110 is provided. In some embodiments, the substrate 110 includes a base semiconductor, a compound semiconductor, an alloy semiconductor, any other suitable material, and/or combinations thereof. The base semiconductor comprises silicon or germanium in crystalline, polycrystalline and/or amorphous structures. The compound semiconductor includes silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide. The alloy semiconductor includes silicon germanium (SiGe), gallium arsenide phosphorus (GaAsP), indium aluminum arsenide (AlInAs), gallium aluminum arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP), and/or gallium indium arsenide phosphide (GaInAsP).

With continued reference to fig. 2, a hard mask layer 120 is formed over the substrate 110 prior to etching the substrate 110. The formation of the hard mask layer 120 may include any suitable deposition method, such as plasma enhanced atomic layer deposition (plasma-enhanced atomic layer deposition, PEALD), chemical vapor deposition (chemical vapor deposition, CVD), plasma enhanced chemical vapor deposition (plasma-enhanced chemical vapor deposition, PECVD), or physical vapor deposition (physical vapor deposition, PVD), among others. In some embodiments, the hard mask layer 120 may comprise silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, or the like.

Referring to fig. 3, portions of the hard mask layer 120 are removed to form a hard mask 120a, and portions of the substrate 110 are exposed.

Referring to fig. 4, the substrate 110 is etched according to the hard mask 120a to form a plurality of trenches 110t (or called shallow trenches) in the substrate 110. The trenches 110t are disposed between the active regions 110a, i.e., the trenches 110t share sidewalls with two adjacent active regions 110 a. In other words, the substrate 110 is etched to define a plurality of island-shaped active regions 110a, and trenches 110t are formed between the active regions 110 a. In some embodiments, the substrate 110 is etched by performing a dry etching technique, such as a reactive ion etching technique (reactive ion etching, RIE), but is not limited thereto.

Referring to fig. 5, the hard mask 120a (see fig. 4) is removed. In some embodiments, the hard mask 120a is removed by dry etching or wet etching to expose the top 111 of the active region 110 a.

Referring to fig. 6, fig. 6 is drawn according to step S12 of fig. 1. In step S12, a first oxide layer 130 is formed by depositing a first oxide on the active regions 110a and in the trenches 110t. In some embodiments, the first oxide comprises silicon oxide, silicon oxynitride, or a combination thereof. In some embodiments, the thickness D1 of the first oxide layer 130 is about 2 nanometers to about 4 nanometers, such as about 2.2 nanometers, about 2.4 nanometers, about 2.6 nanometers, about 2.8 nanometers, about 3.0 nanometers, about 3.2 nanometers, about 3.4 nanometers, about 3.6 nanometers, about 3.8 nanometers, or any value in between any two of these equivalents. The first oxide layer 130 formed by the atomic layer deposition does not attack the sidewall and the top 111 of the active region 110a and the bottom 112 of the trench 110t, so as to maintain the pattern of the active region 110 a.

Referring to fig. 7, fig. 7 is drawn according to step S13 of fig. 1. In step S13, a second oxide layer 140 is formed by disposing a second oxide on the first oxide layer 130 in an in-situ vapor generation manner. In some embodiments, the second oxide comprises silicon oxide, silicon oxynitride, or a combination thereof. In some embodiments, the thickness D2 of the second oxide layer 140 is about 1.5 nanometers to about 3 nanometers, such as about 1.6 nanometers, about 1.8 nanometers, about 2.0 nanometers, about 2.2 nanometers, about 2.4 nanometers, about 2.6 nanometers, about 2.8 nanometers, or any value in between any two of these equivalents. In some embodiments, the in-situ vapor generation conditions are about 800 ℃ to about 950 ℃ for about 5 seconds to about 15 seconds, such that the active region 110a assumes a more circular arc and continuously maintains the active region 110 a.

Referring to fig. 8, fig. 8 is drawn according to step S14 of fig. 1. In step S14, a third oxide layer 150 is formed by forming a third oxide layer on the second oxide layer 140 in a high-quality oxidation manner. In some embodiments, the third oxide comprises silicon oxide, silicon oxynitride, or a combination thereof. In some embodiments, the thickness D3 of the third oxide layer 150 is about 8 nanometers to about 10 nanometers, such as about 8.2 nanometers, about 8.4 nanometers, about 8.6 nanometers, about 8.8 nanometers, about 9.0 nanometers, about 9.2 nanometers, about 9.4 nanometers, about 9.6 nanometers, about 9.8 nanometers, or any value in between any two of these equivalents. In some embodiments, the conditions for in situ vapor generation are from about 500 ℃ to about 750 ℃ for from about 5 minutes to about 15 minutes. The third oxide layer 150 generated by the in-situ vapor generation method makes the two ends of the major axis of the ellipse of the active region 110a in a circular arc shape in a top view, rather than a thin-pointed shape, as an effect of repairing the short side.

Referring to fig. 9, fig. 9 is a top view of a package structure according to some embodiments of the invention. After steps S11, S12, S13 and S14 of the above method 10, it can be seen from a top view that the top 111 of the active region 110a has an oval shape, and its two ends of the major axis L of the oval shape have a circular arc shape with a non-thin peak shape, and the distance between the minor axis M is about 10 nm to about 20 nm, for example, about 12 nm, about 14 nm, about 15 nm, about 16 nm, about 18 nm, or any value between any two of these values. Specifically, in a top view, the top 111 of the elliptical active region 110a is divided into three parts in the direction of the major axis L: first aliquot A1, second aliquot A2, and third aliquot A3. Compared with the method of forming the oxide layer directly by in-situ vapor generation and high quality oxidation without atomic layer deposition, the areas of the first and third portions A1 and A3 of the top 111 of the active region 110a in the preparation method of the present invention are increased by 25%.

Referring to fig. 8, in some embodiments, a third oxide is formed on the first oxide layer by high-quality oxidation, and after the step of forming the third oxide layer 150, a vertical distance from the top 111 of the active region 110a to the bottom 112 of the trench 110t is a depth D, and the bottom 112 has a width W. The ratio of depth D to width W is 1:5 to 1:20, as the wafer scale is smaller, the area of the active region 110a can be made smaller by increasing the aspect ratio. In some embodiments, the depth D is from about 200 nm to about 300 nm, such as about 210 nm, about 220 nm, about 230 nm, about 240 nm, about 250 nm, about 260 nm, about 270 nm, about 280 nm, about 290 nm, or any value in between any two of these equivalents. The width W is about 10 nm to about 60 nm, such as about 15 nm, about 20 nm, about 25 nm, about 30 nm, about 35 nm, about 40 nm, about 45 nm, about 50 nm, about 55 nm, or any value in between any two of these equivalents.

In some embodiments, after step S14, the trench 110t of the substrate 110 may be further filled with a flowable insulation material (not shown), and then the flowable insulation material is cured to form the insulation material. In some embodiments, the flowable isolation material fills the trenches 110t of the substrate 110 in spin-on dielectrics (SOD). In some embodiments, curing the flowable insulation material includes using UV curing means, annealing means, or a combination thereof. In some embodiments, the flowable isolation material includes, but is not limited to, a polysilazane-based spin-on dielectric, and the like. In some embodiments, the flowable insulation material may have a-HN-SiH ₂ -NH-repeat units.

In some embodiments of the present invention, a method for fabricating a semiconductor structure is provided, in which an oxide layer is formed by atomic layer deposition, so as to maintain the original volume and area of an active region from being reduced. For example, an active region having an elliptical shape in plan view, both ends of the major axis of the ellipse maintain circular arcs. This will allow the buried contact of the link capacitor to have sufficient area to contact the active region.

While the present invention has been described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention, and it is intended that the invention be limited only by the terms of the appended claims.

[ symbolic description ]

10: method of

S11-S14: step (a)

110: substrate board

110a: active region

110t: groove(s)

111: top part

112: bottom part

120: hard mask layer

120a: hard mask

130: first oxide layer

140: second oxide layer

150: third oxide layer

A1: first equivalent

A2: second part of

A3: third equivalent

D: depth of

D1: thickness of (L)

D2: thickness of (L)

D3: thickness of (L)

L: long axis

M: short shaft

W: width of the material.

Claims

1. A method of fabricating a semiconductor structure, comprising:

etching the substrate according to the hard mask to form a plurality of active regions and a plurality of grooves in the substrate, wherein the grooves are respectively arranged among the active regions;

the first oxide is arranged on the active areas and in the grooves in an atomic layer deposition mode to form a first oxide layer;

forming a second oxide layer by disposing a second oxide on the first oxide layer in an in-situ vapor generation manner;

and forming a third oxide layer by oxidizing the third oxide layer with high quality.

2. The method of claim 1, wherein the first oxide comprises silicon oxide, silicon oxynitride, or a combination thereof.

3. The method of claim 1, wherein the first oxide layer has a thickness of about 2 nm to about 4 nm.

4. The method of claim 1, wherein the second oxide comprises silicon oxide, silicon oxynitride, or a combination thereof.

5. The method of claim 1, wherein the second oxide layer has a thickness of about 1.5 nm to about 3 nm.

6. The method of claim 1, wherein the in-situ vapor generation conditions are from about 800 ℃ to about 950 ℃ for from about 5 seconds to about 15 seconds.

7. The method of claim 1, wherein the third oxide comprises silicon oxide, silicon oxynitride, or a combination thereof.

8. The method of claim 1, wherein the third oxide layer has a thickness of about 8 nm to about 10 nm.

9. The method of claim 1, wherein the high quality oxidation regime is at a temperature of about 500 ℃ to about 750 ℃ for about 5 minutes to about 15 minutes.

10. The method of claim 1, wherein after the step of forming the third oxide layer by oxidizing the third oxide layer with high quality, each trench comprises a bottom and a top, the vertical distance from the top to the bottom being depth, the bottom having a width; the ratio of the depth to the width is 1:5 to 1:20.

11. the method of claim 10, wherein the depth is about 200 nm to about 300 nm and the width is about 10 nm to about 60 nm.