CN113423170A - Circuit mother board and preparation method of circuit board - Google Patents
Circuit mother board and preparation method of circuit board Download PDFInfo
- Publication number
- CN113423170A CN113423170A CN202110672817.3A CN202110672817A CN113423170A CN 113423170 A CN113423170 A CN 113423170A CN 202110672817 A CN202110672817 A CN 202110672817A CN 113423170 A CN113423170 A CN 113423170A
- Authority
- CN
- China
- Prior art keywords
- circuit
- conductive pattern
- detection
- board
- cutting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 238000001514 detection method Methods 0.000 claims abstract description 119
- 238000005520 cutting process Methods 0.000 claims abstract description 113
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 description 25
- 238000009966 trimming Methods 0.000 description 20
- 230000008569 process Effects 0.000 description 17
- 238000010586 diagram Methods 0.000 description 9
- 230000002950 deficient Effects 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 238000007641 inkjet printing Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
- G01B5/00—Measuring arrangements characterised by the use of mechanical techniques
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Structure Of Printed Boards (AREA)
Abstract
The invention provides a circuit motherboard and a preparation method of a circuit board, belongs to the technical field of circuit board preparation, and can at least partially solve the problem that the cutting precision of the existing circuit board cannot be accurately identified. The invention relates to a circuit mother board, which comprises a plurality of circuit daughter boards, wherein each circuit daughter board comprises: a substrate; a bonding pad disposed on the substrate and extending in a first direction; a detection pattern disposed on the substrate and located on at least one side of the bonding pad in a second direction; the detection pattern includes: the circuit daughter board comprises a cutting area, and the first detection portion and the second detection portion are respectively located at two edge ends of the cutting area in the first direction.
Description
Technical Field
The invention belongs to the technical field of circuit board preparation, and particularly relates to a circuit motherboard and a circuit board preparation method.
Background
With the development of consumer electronics products such as smart phones and smart televisions toward light weight, thinness, full-screen and high resolution, flexible circuit boards face the market demand of high-flexibility and ultra-fine circuits. With the development of display technology and the demand for narrow frames of display products, the Bonding Pad (Bonding Pad) size of a Flexible Printed Circuit (FPC) is getting smaller and smaller. With the reduction of the size of the Bonding pad, the overlapping area of the flexible circuit board and the Bonding pad of the display substrate (Panel) during Bonding is also reduced. In the prior art, due to the restriction of various processes, the minimum overlapping area of the bonding pad of the flexible circuit board and the bonding pad of the display substrate during bonding is not easy to meet the electric connection requirement, and the narrow frame of the display product is restricted.
Disclosure of Invention
The invention at least partially solves the problem that the cutting precision of the existing circuit board cannot be accurately identified, and provides a circuit mother board and a circuit daughter board preparation method which can facilitate the detection of cutting errors.
The technical scheme adopted for solving the technical problem of the invention is a circuit mother board, which comprises a plurality of circuit daughter boards, wherein each circuit daughter board comprises:
a substrate;
a bonding pad disposed on the substrate and extending in a first direction;
a detection pattern disposed on the substrate and located on at least one side of the bonding pad in a second direction; the detection pattern includes: the circuit daughter board comprises a cutting area, and the first detection portion and the second detection portion are respectively located at two edge ends of the cutting area in the first direction.
Optionally, the number of the bonding pads includes a plurality of bonding pads, and the plurality of bonding pads are arranged along the second direction.
Optionally, the first detecting portion and the second detecting portion are spaced apart by a second distance in a second direction.
Further optionally, the circuit motherboard further includes: carrying out alignment identification; in the second direction, the alignment mark is located between the first detection part and the second detection part.
Optionally, the first detection part comprises a first conductive pattern and a second conductive pattern; the second detection part includes a third conductive pattern and a fourth conductive pattern;
the detection pattern further includes: a connecting bridge; in a first direction, the connecting bridge is located between the first detection part and the second detection part;
the orthographic projection of the connecting bridge on the substrate covers the cutting area; the first conductive pattern and the second conductive pattern are electrically connected to the connection bridge, respectively; the third conductive pattern and the fourth conductive pattern are electrically connected to the connection bridge, respectively.
Further optionally, the shape of the connecting bridge comprises a rectangle, and an orthographic projection of the connecting bridge on the substrate completely falls into the cutting area.
Optionally, the circuit motherboard further includes: carrying out alignment identification;
in a second direction, the detection pattern is located between the bonding pad and the alignment mark.
Further optionally, in the second direction, a minimum distance between the detection pattern and the alignment mark is not less than 0.2 mm.
Another technical scheme adopted for solving the technical problem of the invention is a preparation method of a circuit sub-board, which comprises the following steps:
cutting the circuit mother board at least along a second direction to cut the plurality of circuit sub-boards into circuit sub-boards; the circuit motherboard comprises any one of the circuit motherboards;
and detecting whether the detection pattern on the cut line sub-board and the detection pattern on the substrate around the cut line sub-board are complete or not, and determining whether the cut line sub-board exceeds the maximum cutting error or not according to the detection result.
Another technical scheme adopted for solving the technical problem of the invention is a preparation method of a circuit sub-board, which comprises the following steps:
cutting the circuit mother board at least along a second direction to cut the plurality of circuit sub-boards into circuit sub-boards; the circuit motherboard comprises the above partial circuit motherboard;
writing detection signals to the first conductive pattern and the third conductive pattern of the same line sub-board, respectively, and detecting output signals of the second conductive pattern and the fourth conductive pattern;
and determining whether the cut line sub-board exceeds the maximum cutting error according to the detection result.
Optionally, the determining, according to the detection result, whether the cut line sub-board exceeds the maximum cutting error includes:
detecting whether an output signal exists in the second conductive pattern and the fourth conductive pattern; when the second conductive pattern and the fourth conductive pattern have output signals, the cut circuit sub-board does not exceed the maximum cutting error; when at least one of the second conductive pattern and the fourth conductive pattern can not detect an output signal, the cut line sub-board exceeds the maximum cutting error.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic structural diagram of a conventional display motherboard;
fig. 2 is a schematic structural diagram of a circuit daughter board in a conventional display mother board;
fig. 3 is a schematic structural diagram of a circuit daughter board according to an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating the trimming line of the circuit sub-board of FIG. 3 exceeding the allowable range of error;
FIG. 5 is a schematic diagram of another trimming line of the circuit sub-board of FIG. 3 exceeding an error tolerance;
fig. 6 is a schematic structural diagram of another line daughter board according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a portion of the structure in the line daughter board of FIG. 6;
FIG. 8 is a schematic structural diagram of a detection pattern after the circuit sub-board of FIG. 7 is cut along the cutting line;
FIG. 9 is a partial schematic view of the line daughter board of FIG. 6 with the cutting line exceeding the tolerance;
FIG. 10 is a schematic diagram illustrating a structure of a detection pattern after the circuit sub-board of FIG. 9 is cut along the cutting line;
FIG. 11 is a partial schematic view of another trimming line of the circuit sub-board of FIG. 6 exceeding an error tolerance;
fig. 12 is a schematic structural view of a detection pattern after the circuit sub-board of fig. 11 is cut along the cutting line.
Detailed Description
In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
In the present invention, the two structures "in the same layer" means that they are formed of the same material layer and thus are in the same layer in a stacked relationship, but do not represent that they are equidistant from the substrate nor that they are completely identical in structure with other layers between the substrate.
In the present invention, the "patterning process" refers to a step of forming a structure having a specific pattern, which may be a photolithography process including one or more steps of forming a material layer, coating a photoresist, exposing, developing, etching, stripping a photoresist, and the like; of course, the "patterning process" may also be an imprinting process, an inkjet printing process, or other processes.
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of components, are set forth in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
With the development of display technology and the demand for narrow frames of display products, the Bonding Pad (Bonding Pad) size of a Flexible Printed Circuit (FPC) is getting smaller and smaller. With the reduction of the size of the Bonding pad, the overlapping area of the flexible circuit board and the Bonding pad of the display substrate (Panel) during Bonding is also reduced. In the prior art, due to the restriction of various processes, the minimum overlapping area of a bonding Pad (FPC Pad) of a flexible circuit board and a bonding Pad (Panel Pad) of a display substrate during bonding cannot meet the electrical connection requirement, and the narrow frame of a display product is restricted.
Referring to fig. 1 and 2, in a common FPC manufacturing process in the prior art, a plurality of flexible circuit daughter boards 01 are formed on a flexible circuit mother board 02 through processes of etching, routing, punching, exposing and the like, and are finally cut into single flexible circuit boards through a mold. The flexible circuit motherboard 02 is further provided with a positioning hole 03 for positioning the flexible circuit motherboard 02. In the prior art, the limit precision of the positioning hole 03 is about +/-0.04 mm, the precision of the precision cutting die is +/-0.05 mm, and the expansion and contraction rate of the flexible circuit board substrate in the first direction (in the vertical direction in fig. 1) is +/-0.01 mm. After cutting, the limit precision of the cross alignment mark 3 of the flexible printed circuit board from the edge of the cut bonding pad 1 in the first direction is +/-0.1 mm-0.04 +0.05+0.01, and the cumulative tolerance is +/-0.065- (0.04-0.04 + 0.05-0.05 + 0.01). Because the existing influence factors can not control the CPK (Process capability index), part of products still fall between the precision of 0.065-0.1mm after actual cutting.
With the narrower design requirements of the frame of the display product, the frame is especially based on the next generation LTPS&The a-Si design platform requires the height (dimension in the vertical direction in fig. 2) of bond pad 1 to be designed from 0.35mm to 0.3mm to meet trend requirements. However, according to the prior art, after the height of the bonding Pad 1 is reduced, the overlapping area between the FPC Pad and the Panel Pad is reduced, and the minimum value of the overlapping area specification is not met (for example, the overlapping area Spec is not less than 12000um required by the prior ACF3418 model)2) Leading to an ACF (Anisotropic Conductive Film; anisotropic conductive film).
Referring to fig. 3 to 12, in one aspect, the present embodiment provides a circuit motherboard 02 including a plurality of circuit daughter boards 01. The line sub-board 01 includes: a substrate; a bonding pad 1 disposed on a substrate and extending in a first direction; the detection pattern 2 is arranged on the substrate, and in the second direction, the detection pattern 2 is positioned on at least one side of the bonding pad 1; the detection pattern 2 includes: the circuit sub-board 01 comprises a cutting area A, and the cutting area A at least extends along a second direction; the first detecting portion 21 and the second detecting portion 22 are respectively located at two end edges of the cutting area a in the first direction.
The circuit mother board 02 provided by this embodiment can be cut by a cutting device, and a plurality of circuit daughter boards 01 are cut into a plurality of circuit boards along the cutting area a. This circuit board accessible bonding pad 1 and display panel bond. The circuit board can be a common flexible circuit board (FPC) or other circuit boards.
In the circuit motherboard 02 provided by this embodiment, the detection pattern 2 is provided on the substrate, and the detection of the cutting error of the circuit motherboard 02 is realized by detecting the detection pattern 2 after the circuit motherboard 02 is cut. Referring to fig. 3 through 6, bond pad 1 is disposed on a substrate and extends in a first direction (vertical direction in the figures). The number of bonding pads 1 may be multiple, and a plurality of bonding pads 1 may be arranged in an array. Specifically, referring to FIGS. 3-6, a plurality of bond pads 1 may form a row. The sensing pattern 2 may be disposed at one side or both sides of the array of bonding pads 1 in the row direction. Each detection pattern 2 includes two detection portions (a first detection portion 21 and a second detection portion 22). The two detection parts are respectively positioned at two edge ends of the cutting area A in the first direction. The trimming area a is an ideal trimming area a when the wiring mother board 02 is trimmed in the second direction, or a trimming error allowable area. That is, the cutting line (refer to the dotted line in the figure) extends along the second direction, and when the cutting line falls in the cutting area a, the circuit board formed by cutting is a circuit board meeting the standard. Referring to fig. 3, the first detecting portion 21 and the second detecting portion 22 define an error-allowable area for cutting the wiring motherboard 02 in the second direction. When the mother board 02 is cut in the second direction, the cutting line should ideally pass through the interval region between the first detecting portion 21 and the second detecting portion 22. After the cutting is completed, the first detecting portion 21 and the second detecting portion 22 should be complete, at this time, it is stated that the cutting of the circuit motherboard 02 is within the error range, and the circuit board formed by cutting meets the production requirement. If the first detection part 21 or the second detection part 22 is not complete, it indicates that the cutting of the circuit mother board 02 is wrong, and the circuit board formed by cutting is a defective product. Therefore, based on the circuit motherboard 02 provided by this embodiment, the cutting yield of the formed circuit board can be detected by detecting the detection pattern 2, and the circuit board meeting the cutting requirement is selected, so as to improve the cutting precision control capability of the circuit board.
The distance between the first detection unit 21 and the second detection unit 22 in the first direction determines the detection range of the cutting accuracy. The maximum cutting error allowed when the circuit sub-board 01 is cut into the circuit sub-board 01 along the second direction can be determined according to actual conditions. Specifically, the distance between the first detecting portion 21 and the second detecting portion 22 in the first direction in the present embodiment may be 0.5mm, and in this case, the maximum cutting error range of the circuit sub-board 01 that can be detected is-0.25 to + 0.25.
Optionally, in some embodiments, the first detection portion 21 and the second detection portion 22 are spaced apart by a second distance in the second direction. Referring to fig. 3 to 5, it can be understood that when the display mother substrate is cut, the cutting line should ideally be exactly parallel to the second direction. In practice, however, the cutting line may deviate from the second direction to some extent. In the present embodiment, the first detection portion 21 and the second detection portion 22 are spaced apart by a certain distance in the second direction, so that the trimming error of the circuit motherboard 02 can be observed conveniently. It can be understood that, in the case of the same cropping error, the farther the first detection portion 21 and the second detection portion 22 are spaced in the second direction, the more obvious the detection result of the error is, that is, the easier the detection is. Therefore, in the present embodiment, the first detecting portion 21 and the second detecting portion 22 are spaced apart by a second distance in the second direction, so that the detecting result is more accurate. It should be noted that, in an ideal state, the farther the distance between the first detecting portion 21 and the second detecting portion 22 in the second direction is, the better, but in an actual product, the distance between the first detecting portion 21 and the second detecting portion 22 may be set according to the specification and the size of the actual product of the circuit board, and the embodiment is not particularly limited.
Referring to fig. 3, in some embodiments, the method further includes: a registration mark 3; in the second direction, the alignment mark 3 is located between the first detection part 21 and the second detection part 22. The alignment mark 3 can be used for alignment when the circuit board and the display panel are bonded so as to ensure the alignment precision of the circuit board and the display panel. In this embodiment, the alignment mark 3 is provided between the first detection unit 21 and the second detection unit 22, so that the increase in the area of the circuit board due to the provision of the alignment mark 3 can be avoided as much as possible while ensuring the detection accuracy.
Referring to fig. 6, in other embodiments, the sensing pattern 2 may be positioned between the bonding pad 1 and the alignment mark 3. Referring to fig. 2, a redundant pad is disposed between the bonding pad 1 and the alignment mark 3 in the prior art, and in this embodiment, the redundant pad in the prior art may be removed, and the inspection pattern 2 is disposed therein, so as to reduce the size of the circuit board.
Alternatively, in some embodiments, the first detection part 21 includes a first conductive pattern 21a and a second conductive pattern 21 b; the second detection part 22 includes a third conductive pattern 22a and a fourth conductive pattern 22 b; the detection pattern 2 further includes: a connecting bridge 23; in the first direction, the connecting bridge 23 is located between the first detection part 21 and the second detection part 22; the orthographic projection of the connecting bridge 23 on the substrate covers the cutting area A; the shape of the cutting area A comprises a rectangle, and the orthographic projection of the connecting bridge 23 on the substrate completely falls into the cutting area A; the first conductive pattern 21a and the second conductive pattern 21b are connected to both end points of the connection bridge 23 in the second direction, respectively; the third conductive pattern 22a and the fourth conductive pattern 22b are electrically connected to both ends of the connection bridge 23 in the second direction, respectively.
In the present embodiment, both the two conductive patterns (the first conductive pattern 21a and the second conductive pattern 21b) of the first detection part 21 and both the two conductive patterns (the third conductive pattern 22a and the fourth conductive pattern 22b) of the second detection part 22 are electrically connected by the connection bridge 23. Wherein the orthographic projection of the connecting bridge 23 on the substrate covers the cutting area a. Referring to fig. 7 to 12, when the circuit mother board 02 is cut in the second direction, the cutting line should pass through the cutting area a. The two conductive patterns of the first detecting portion 21 and the two conductive patterns of the second detecting portion 22 should be located at two sides of the cutting line, respectively, and meanwhile, the two conductive patterns of the first detecting portion 21 are connected only by the connecting bridge 23, and the two conductive patterns of the second detecting portion 22 are also connected only by the connecting bridge 23. When the mother board 02 is cut in the second direction, the cutting line should ideally pass through the spacing region between the first detecting portion 21 and the second detecting portion 22, that is, the connecting bridge 23. After the cutting is completed, the first detecting portion 21 and the second detecting portion 22, and the third detecting portion and the fourth detecting portion should be electrically connected through the two connecting bridges 23. Specifically, when the cutting of the wiring mother board 02 meets the error range, the connecting bridge 23 is cut into two parts in the second direction, that is, the connecting bridge 23 is divided into two parts in the first direction. Wherein the first portion may electrically connect the first conductive pattern 21a with the second conductive pattern 21 b; the second portion may electrically connect the third conductive pattern 22a with the fourth conductive pattern 22 b. When the trimming of the wiring motherboard 02 is biased upward (the first direction is upward in fig. 9) beyond the allowable error range, the trimming line is located above the connecting bridge 23, and the connecting bridge 23 is not trimmed but the first conductive pattern 21a and the second conductive pattern 21b are disconnected from the connecting bridge 23, and at the same time, the third conductive pattern 22a and the fourth conductive pattern 22b are electrically connected through the connecting bridge 23. When the trimming deviation of the wiring motherboard 02 exceeds the allowable error range, the trimming line is located below the connecting bridge 23, the connecting bridge 23 is not trimmed, the third conductive pattern 22a and the fourth conductive pattern 22b are disconnected from the connecting bridge 23, and the first conductive pattern 21a and the second conductive pattern 21b are electrically connected through the connecting bridge 23.
Therefore, in the present embodiment, it is possible to determine whether the cut line sub-board 01 exceeds the maximum cutting error by writing the detection signal to the first conductive pattern 21a and the third conductive pattern 22a and detecting whether the output signal exists in the second conductive pattern 21b and the fourth conductive pattern 22 b. Specifically, when the second conductive pattern 21b and the fourth conductive pattern 22b both have output signals, the cut circuit sub-board 01 does not exceed the maximum cutting error, the cutting of the circuit mother board 02 is within the error range, and the cut circuit board meets the production requirement; when at least one of the second conductive pattern 21b and the fourth conductive pattern 22b cannot detect the output signal, the cut circuit sub-board 01 exceeds the maximum cutting error, and the formed circuit board is cut into a defective product. Therefore, based on the circuit motherboard 02 provided by the embodiment, the yield of the formed circuit board can be detected by detecting the detection pattern 2, so that the cutting precision control capability of the circuit board is improved.
In this embodiment, the projection of the connecting bridge 23 on the substrate should cover the ideal trimming area, which is the area where the trimming line is allowed to be trimmed if the trimming error is allowed. It will be appreciated that the shape of the cropped area a should be a rectangle extending in the second direction, and the size in the first direction should be related to the error allowed by cropping, with smaller sizes providing higher detection accuracy.
It is understood that the projection of the connecting bridge 23 on the substrate in this embodiment covers the cutout a, while the four conductive patterns are connected only by the connecting bridge 23. The shape of the connecting bridge 23 may include various shapes, as shown in fig. 6 to 12, the connecting bridge 23 may be regular rectangular, polygonal, or the like, or may be irregular, and details thereof are not described in this embodiment. Alternatively, in some embodiments, the shape of the connecting bridge 23 comprises a rectangle, in which case one edge of the rectangle is arranged along a first direction, and the dimension in the first direction is equal to the first distance.
Referring to fig. 6 to 12, the distance between the first conductive pattern 21a and the second conductive pattern 21b in the second direction may be determined by the connecting bridge 23, and similarly, the distance between the third conductive pattern 22a and the fourth conductive pattern 22b in the second direction may also be determined by the connecting bridge 23. It will be appreciated that when cutting the display mother panel, the cutting lines should ideally be strictly parallel to the second direction. In practice, however, the cutting line may deviate from the second direction to some extent. In the present embodiment, the first detection portion 21 and the second detection portion 22 are spaced apart by a certain distance in the second direction, so that the trimming error of the circuit motherboard 02 can be observed conveniently. It can be understood that, in the case of an equivalent cutting error, the larger the dimension of the connecting bridge 23 in the second direction (i.e., the longer the connecting bridge 23), the more obvious the detection result of the error is, i.e., the easier the detection is. It should be noted that, in an ideal state, the larger the dimension of the connecting bridge 23 in the second direction, the better, but in an actual product, the dimension may be set according to the specification and the size of the actual product of the circuit board, and the embodiment is not particularly limited.
In some embodiments, the wiring motherboard 02 further comprises: a registration mark 3; in the second direction, the sensing pattern 2 is positioned between the bonding pad 1 and the alignment mark 3. The alignment mark 3 can be used for aligning the circuit board and the display substrate at the bonding time so as to ensure the alignment precision of the circuit board and the display substrate. Referring to fig. 2, a redundant pad is disposed between the bonding pad 1 and the alignment mark 3 in the prior art, and in this embodiment, the redundant pad in the prior art may be eliminated, and the inspection pattern 2 is disposed to reduce the size of the circuit board.
In some embodiments, at least two of the sensing pattern 2, the bonding pad 1, and the alignment mark 3 may be formed through a one-time patterning process. Specifically, in this embodiment, a metal film layer may be formed on a substrate through a one-step patterning process, and then at least some structures of the detection pattern 2, the bonding pad 1, and the alignment mark 3 may be formed through an etching process.
In some embodiments, at least in the second direction, the minimum distance between the detection pattern 2 and the alignment mark 3 is not less than 0.2mm, so as to avoid that the detection pattern 2 is too close to the alignment mark 3 to affect the alignment of the circuit board during the bonding process. Further, in the first direction, the minimum distance between the mapping pattern 2 and the alignment mark 3 should be not less than 0.2mm,
in a second aspect, the present embodiment further provides a method for manufacturing a circuit sub-board 01, which may include the following steps:
s1, cutting the circuit mother board 02 at least along a second direction to cut the plurality of circuit sub-boards 01 into the circuit sub-boards 01; the circuit motherboard 02 may include any one of the circuit motherboards 02 described above.
In this step, the circuit motherboard 02 may be cut using a cutting die. In this embodiment, the second direction refers to a cutting direction when the circuit mother board 02 is cut into circuit boards. The detection pattern 2 in the present embodiment corresponds to detection of a trimming error in the second direction of the wiring motherboard 02. In practical cases, an independent circuit board may be obtained by cutting the circuit motherboard 02 in multiple directions, and in this case, the second direction in this embodiment may be one of the directions, or multiple directions. When error detection is required in multiple directions, corresponding detection pads may be disposed corresponding to multiple different second directions, which may specifically refer to the above-mentioned contents and will not be described herein again.
S2, detecting whether the detection pattern 2 on the cut line sub-board 01 and the detection pattern 2 on the substrate around the cut line sub-board are complete or not, and determining whether the cut line sub-board 01 exceeds the maximum cutting error or not according to the detection result.
Referring to fig. 7 to 12, in the present embodiment, the first detection portion 21 and the second detection portion 22 define an error allowable area for cutting the circuit motherboard 02 in the second direction. When the mother board 02 is cut in the second direction, the cutting line should ideally pass through the interval region between the first detecting portion 21 and the second detecting portion 22. After the cutting is completed, the first detecting portion 21 and the second detecting portion 22 should be complete, at this time, it is stated that the cutting of the circuit motherboard 02 is within the error range, and the circuit board formed by cutting meets the production requirement. If the first detection part 21 or the second detection part 22 is not complete, it indicates that the cutting of the circuit mother board 02 is wrong, and the circuit board formed by cutting is a defective product. Therefore, based on the circuit motherboard 02 provided by the embodiment, the yield of the formed circuit board can be detected by detecting the detection pattern 2, so that the cutting precision control capability of the circuit board is improved.
In a third aspect, this embodiment further provides a method for manufacturing a circuit daughter board 01, where the circuit mother board 02 includes the above-mentioned part of the circuit mother board 02, and the first detection portion 21 includes a first conductive pattern 21a and a second conductive pattern 21 b; the second detection portion 22 includes a third conductive pattern 22a and a fourth conductive pattern 22b, and the specific structure can refer to the related contents in the above embodiments. The preparation method provided by the embodiment can comprise the following steps:
and S11, cutting the circuit mother board 02 at least along the second direction to cut the plurality of circuit sub-boards 01 into the circuit sub-boards 01.
Both the two conductive patterns (the first conductive pattern 21a and the second conductive pattern 21b) of the first detection part 21 and both the two conductive patterns (the third conductive pattern 22a and the fourth conductive pattern 22b) of the second detection part 22 are electrically connected by the connection bridge 23. Wherein the orthographic projection of the connecting bridge 23 on the substrate covers the cutting area a. When the circuit mother board 02 is cut in the second direction, the cutting line should pass through the cutting area a. The two conductive patterns of the first detecting portion 21 and the two conductive patterns of the second detecting portion 22 should be located at two sides of the cutting line, respectively, and meanwhile, the two conductive patterns of the first detecting portion 21 are connected only by the connecting bridge 23, and the two conductive patterns of the second detecting portion 22 are also connected only by the connecting bridge 23. When the mother board 02 is cut in the second direction, the cutting line should ideally pass through the spacing region between the first detecting portion 21 and the second detecting portion 22, that is, the connecting bridge 23. After the cutting is completed, the first detecting portion 21 and the second detecting portion 22, and the third detecting portion and the fourth detecting portion should be electrically connected through the two connecting bridges 23. Specifically, when the cutting of the wiring mother board 02 meets the error range, the connecting bridge 23 is cut into two parts in the second direction, that is, the connecting bridge 23 is divided into two parts in the first direction. Wherein the first portion may electrically connect the first conductive pattern 21a with the second conductive pattern 21 b; the second portion may electrically connect the third conductive pattern 22a with the fourth conductive pattern 22 b. When the trimming of the wiring motherboard 02 is deviated beyond the allowable error range, the trimming line is located above the connecting bridge 23, the connecting bridge 23 is not trimmed, but the first conductive pattern 21a and the second conductive pattern 21b are disconnected from the connecting bridge 23, and at the same time, the third conductive pattern 22a and the fourth conductive pattern 22b are electrically connected through the connecting bridge 23. When the trimming deviation of the wiring motherboard 02 exceeds the allowable error range, the trimming line is located below the connecting bridge 23, the connecting bridge 23 is not trimmed, the third conductive pattern 22a and the fourth conductive pattern 22b are disconnected from the connecting bridge 23, and the first conductive pattern 21a and the second conductive pattern 21b are electrically connected through the connecting bridge 23.
S12, writing detection signals to the first conductive pattern 21a and the third conductive pattern 22a of the same line sub-board 01, respectively, and detecting output signals of the second conductive pattern 21b and the fourth conductive pattern 22 b.
Based on the different connection relationships between the conductive patterns and the connection bridge 23 in the different cutting cases, in the present embodiment, it is possible to determine whether the cut line sub-board 01 exceeds the maximum cutting error by writing the detection signal to the first conductive pattern 21a and the third conductive pattern 22a and detecting whether the output signal exists from the second conductive pattern 21b and the fourth conductive pattern 22 b.
And S13, determining whether the cut circuit sub-board 01 exceeds the maximum cutting error according to the detection result.
Optionally, in some embodiments, step S13 includes: detecting whether the second conductive pattern 21b and the fourth conductive pattern 22b have the output signal; when the output signal exists in both the second conductive pattern 21b and the fourth conductive pattern 22b, the cut line sub-board 01 does not exceed the maximum cutting error; when at least one of the second conductive pattern 21b and the fourth conductive pattern 22b cannot detect the output signal, the cut circuit sub-board 01 exceeds the maximum cutting error.
Specifically, when the second conductive pattern 21b and the fourth conductive pattern 22b both have output signals, the cut circuit sub-board 01 does not exceed the maximum cutting error, the cutting of the circuit mother board 02 is within the error range, and the cut circuit board meets the production requirement; when at least one of the second conductive pattern 21b and the fourth conductive pattern 22b cannot detect the output signal, the cut circuit sub-board 01 exceeds the maximum cutting error, and the formed circuit board is cut into a defective product. Therefore, based on the circuit motherboard 02 provided by the embodiment, the yield of the formed circuit board can be detected by detecting the detection pattern 2, so that the cutting precision control capability of the circuit board is improved.
Optionally, in some embodiments, step S13 may include: the cutting error is determined based on the output signal data of the second conductive pattern 21b and the fourth conductive pattern 22 b. Specifically, even if the actual cutting line is cut between the first detecting portion 21 and the second detecting portion 22 during the cutting process, in accordance with the amount of deviation according to the cutting line, in most cases, the connecting bridge 23 is cut into two portions having different widths (sizes in the first direction), and the two portions of the connecting bridge 23 electrically connect the first conductive pattern 21a and the second conductive pattern 21b, and the third conductive pattern 22a and the fourth conductive pattern 22b, respectively. Here, since the widths of the two-part connecting bridge 23 are different, the resistance values thereof are also different. On the basis, in the present embodiment, the amount of shift of the cutting line is determined by correlation estimation based on the relative change amounts of the detection signal data received by the second conductive pattern 21b and the fourth conductive pattern 22b and the detection signal data input to the corresponding first conductive pattern 21a and the third conductive pattern 22 a.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
In accordance with the present invention, as set forth above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (11)
1. A circuit motherboard comprising a plurality of circuit daughterboards, the circuit daughterboard comprising:
a substrate;
a bonding pad disposed on the substrate and extending in a first direction;
a detection pattern disposed on the substrate and located on at least one side of the bonding pad in a second direction; the detection pattern includes: a first detection unit and a second detection unit;
the circuit daughter board comprises a cutting area, and the first detection portion and the second detection portion are respectively located at two edge ends of the cutting area in the first direction.
2. The circuit motherboard of claim 1, wherein in each of said circuit daughterboards,
the number of the bonding pads comprises a plurality of bonding pads, and the bonding pads are arranged along the second direction.
3. The wiring motherboard of claim 1, wherein the first detection portion is spaced from the second detection portion by a second distance in a second direction.
4. The wiring motherboard of claim 3, further comprising: carrying out alignment identification; in the second direction, the alignment mark is located between the first detection part and the second detection part.
5. The wiring motherboard according to claim 1, wherein the first detection section includes a first conductive pattern and a second conductive pattern which are disposed apart in the second direction; the second detection part comprises a third conductive pattern and a fourth conductive pattern which are arranged in a second direction at intervals;
the detection pattern further includes: a connecting bridge; in a first direction, the connecting bridge is located between the first detection part and the second detection part;
the orthographic projection of the connecting bridge on the substrate covers the cutting area; the first conductive pattern and the second conductive pattern are electrically connected to the connection bridge, respectively; the third conductive pattern and the fourth conductive pattern are electrically connected to the connection bridge, respectively.
6. The wiring motherboard of claim 5, wherein the shape of the connecting bridge comprises a rectangle and an orthographic projection of the connecting bridge on the substrate falls entirely within the cutout.
7. The wiring motherboard of claim 5, further comprising: carrying out alignment identification;
in a second direction, the detection pattern is located between the bonding pad and the alignment mark.
8. The wiring motherboard according to claim 7, wherein in the second direction, the minimum distance between the detection pattern and the alignment mark is not less than 0.2 mm.
9. A preparation method of a circuit sub-board is characterized by comprising the following steps:
cutting the circuit mother board at least along a second direction to cut the plurality of circuit sub-boards into circuit sub-boards; the wiring motherboard comprises the wiring motherboard of any one of claims 1 to 8;
and detecting whether the detection pattern on the cut line sub-board and the detection pattern on the substrate around the cut line sub-board are complete or not, and determining whether the cut line sub-board exceeds the maximum cutting error or not according to the detection result.
10. A preparation method of a circuit sub-board is characterized by comprising the following steps:
cutting the circuit mother board at least along a second direction to cut the plurality of circuit sub-boards into circuit sub-boards; the wiring motherboard comprises the wiring motherboard of any one of claims 5 to 7;
writing detection signals to the first conductive pattern and the third conductive pattern of the same line sub-board, respectively, and detecting output signals of the second conductive pattern and the fourth conductive pattern;
and determining whether the cut line sub-board exceeds the maximum cutting error according to the detection result.
11. The manufacturing method according to claim 10, wherein the determining whether the cut line sub-board exceeds a maximum cutting error according to the detection result comprises:
detecting whether an output signal exists in the second conductive pattern and the fourth conductive pattern; when the second conductive pattern and the fourth conductive pattern have output signals, the cut circuit sub-board does not exceed the maximum cutting error; when at least one of the second conductive pattern and the fourth conductive pattern can not detect an output signal, the cut line sub-board exceeds the maximum cutting error.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110672817.3A CN113423170B (en) | 2021-06-17 | 2021-06-17 | Circuit motherboard and preparation method of circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110672817.3A CN113423170B (en) | 2021-06-17 | 2021-06-17 | Circuit motherboard and preparation method of circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113423170A true CN113423170A (en) | 2021-09-21 |
| CN113423170B CN113423170B (en) | 2024-09-17 |
Family
ID=77788851
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110672817.3A Active CN113423170B (en) | 2021-06-17 | 2021-06-17 | Circuit motherboard and preparation method of circuit board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113423170B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115115190A (en) * | 2022-01-30 | 2022-09-27 | 希望知舟技术(深圳)有限公司 | Quality monitoring method based on working condition, related device and program medium product |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1304543A1 (en) * | 2001-10-22 | 2003-04-23 | Agilent Technologies, Inc. (a Delaware corporation) | Positioning with conductive indicia ( silicon optical bench ) |
| US20060146263A1 (en) * | 2005-01-04 | 2006-07-06 | Samsung Electronics Co., Ltd. | Mother plate for a flexible printed circuit film formed with a cutting pattern and display device provided with a flexible printed circuit film cut from the same |
| JP2006235503A (en) * | 2005-02-28 | 2006-09-07 | Optrex Corp | Display device |
| EP2860150A1 (en) * | 2013-10-11 | 2015-04-15 | OCE-Technologies B.V. | Substrate plate for MEMS devices |
| CN205643942U (en) * | 2016-05-24 | 2016-10-12 | 合肥京东方光电科技有限公司 | Circuit plate structure and display device |
| CN112911794A (en) * | 2021-01-21 | 2021-06-04 | 昆山国显光电有限公司 | Flexible circuit board, display screen and electronic equipment |
-
2021
- 2021-06-17 CN CN202110672817.3A patent/CN113423170B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1304543A1 (en) * | 2001-10-22 | 2003-04-23 | Agilent Technologies, Inc. (a Delaware corporation) | Positioning with conductive indicia ( silicon optical bench ) |
| US20060146263A1 (en) * | 2005-01-04 | 2006-07-06 | Samsung Electronics Co., Ltd. | Mother plate for a flexible printed circuit film formed with a cutting pattern and display device provided with a flexible printed circuit film cut from the same |
| JP2006235503A (en) * | 2005-02-28 | 2006-09-07 | Optrex Corp | Display device |
| EP2860150A1 (en) * | 2013-10-11 | 2015-04-15 | OCE-Technologies B.V. | Substrate plate for MEMS devices |
| CN205643942U (en) * | 2016-05-24 | 2016-10-12 | 合肥京东方光电科技有限公司 | Circuit plate structure and display device |
| CN112911794A (en) * | 2021-01-21 | 2021-06-04 | 昆山国显光电有限公司 | Flexible circuit board, display screen and electronic equipment |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115115190A (en) * | 2022-01-30 | 2022-09-27 | 希望知舟技术(深圳)有限公司 | Quality monitoring method based on working condition, related device and program medium product |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113423170B (en) | 2024-09-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3256391B2 (en) | Circuit board structure | |
| US7358619B2 (en) | Tape carrier for TAB | |
| US4927491A (en) | Method of bonding IC unit | |
| JP2011100326A (en) | Motherboard for touch panel and method for manufacturing the same | |
| EP1819209B1 (en) | Wired circuit board and production method thereof | |
| US20060180910A1 (en) | Three-dimensional circuit module and method of manufacturing the same | |
| CN113423170B (en) | Circuit motherboard and preparation method of circuit board | |
| CN101754575B (en) | Wired circuit board assembly sheet | |
| CN111863915A (en) | Flexible display substrate and display panel | |
| JPH1041634A (en) | Multilayer pattern forming method and electronic component | |
| JP6384647B1 (en) | Electronic component, electronic device, and mounting method of electronic component | |
| KR20040069288A (en) | Film Carrier Tape For Mounting Electronic Devices Thereon And Final Defect Marking Method Using The Same | |
| JP2018098448A (en) | Manufacturing method of flexible print circuit board | |
| CN112423464B (en) | Auxiliary measuring circuit of flexible circuit board | |
| JP3740711B2 (en) | Multilayer printed wiring board | |
| CN110856376B (en) | Binding method | |
| TWI837693B (en) | Printed circuit, display device therewith, and method for manufacturing display device | |
| CN220858501U (en) | SMT makeup structure of flexible circuit board | |
| CN107580408B (en) | PCB tolerance plate structure and processing method thereof | |
| JPH079139Y2 (en) | LCD drive circuit connection structure | |
| KR101060660B1 (en) | Scale index device, substrate having same, forming method thereof, method and apparatus for measuring deformation of substrate using same | |
| JP2010192610A (en) | Method of manufacturing and method of inspecting base material for printed wiring board having multiple development patterns formed, method of manufacturing and method of inspecting multiple-patterned printed wiring board, method of manufacturing semiconductor device, and exposure mask | |
| TWI596426B (en) | A method for detecting the error of negative film and a system thereof | |
| JPH0579540U (en) | Display device | |
| JPH0219976B2 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |