CN113422916A - Digital accumulator for eliminating jitter and jitter eliminating method - Google Patents
Digital accumulator for eliminating jitter and jitter eliminating method Download PDFInfo
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Abstract
The invention relates to the field of low-light-level image sensors, and provides a circuit structure for detecting and eliminating jitter for solving a series of image jitter problems generated by mechanical vibration, wherein the circuit structure comprises a detection circuit and a compensation circuit, the circuit structure of the detection circuit is a cyclic shift circuit with a feedback function, the compensation circuit is formed by connecting a plurality of D triggers in series, the data output end of the D trigger at the previous stage is connected with the data input end of the D trigger at the next stage, the D triggers are connected in series to form a shift register ring, and all D trigger clock signals CP are connected together and are connected with Shifter _ input of the detection circuit; analog quantity sensed by two lines of pixels is quantized by an analog-to-digital converter and is transmitted into a detection circuit, and the detection circuit outputs the analog quantity to a compensation circuit for reverse shift.
Description
Technical Field
The invention relates to the field of low-light-level image sensors, in particular to a digital accumulator structure for jitter elimination based on Time Delay Integration (TDI).
Background
The low-light-level night vision imaging technology is a technology which overcomes the disadvantage that human eyes are difficult to observe under the condition of low illumination by a photoelectric conversion mode in the environment of weak light such as moonlight, starlight and the like, and performs image enhancement processing on image information invisible to naked eyes to convert the image information into an image suitable for human eyes to observe.
The low-light-level imaging technology has very important application in the fields of military affairs, medical treatment, scientific detection and the like, the low-light-level imaging needs to sense the invisible brightness of human eyes by an image sensor, and the TDI technology image sensor can well solve the problem. Working principle of complementary metal oxide semiconductor-time delay integration (CMOS-TDI) image sensor: the TDI technology carries out multiple times of exposure and accumulated output on the same target through multiple rows of pixels, so that the light signal integration time is prolonged equivalently on the premise of not reducing the scanning speed, and the imaging quality of the linear array image sensor under the conditions of high speed and low illumination is improved. The TDI pixel array is similar to an area array image sensor, but the imaging mode is linear array scanning. The number of columns (in the track-crossing direction) is equivalent to the length X pixels of the linear array, and the number of rows (in the track direction) is the number Y of delay integration (i.e. the accumulated number). This therefore gives a good perception of the image in the low light range. Although in industrial applications the relative motion of the object and the sensor can be accurately controlled, high quality imaging can be guaranteed. However, in remote imaging systems such as satellites, flight stability is sometimes affected by vibrations caused by flexible internal components or the external environment. Satellites in orbit are sometimes affected by random interference. Especially for vibrations in the cross-track direction, the true accumulation path will change, which will drastically reduce the image quality. According to open data from existing satellites, such as LANDSAT-4 by NASA/GSFC and OLYMPUS by ESA, the stochastic perturbation contains a large number of harmonic vibrations (sine waves) with frequencies centered at 500 Hz. The major harmonic vibrations caused by solar panel tuning are about 1-2.2 Hz. When the rotation speed is changed, the reaction wheel (momentum wheel) also generates resonance at 100-. The motor and the electric pump generate another harmonic vibration at several hundred hertz. Jet explosions, pointing control, spacecraft orbiting, attitude changes and earth rotation errors also contribute to disturbances. In a remote time delay integration imaging system, the above-mentioned vibrations will cause the camera movement to be unstable, and the image generated by the conventional accumulation method of time delay integration will have blurring and distortion.
Disclosure of Invention
In order to overcome the defects of the prior art and solve a series of image jitter problems caused by mechanical vibration, the invention aims to provide a circuit structure for detecting and eliminating jitter. Therefore, the technical scheme adopted by the invention is that the digital accumulator and the jitter elimination method comprise the following steps:
detecting the horizontal shaking amount through two rows of detection pixels, wherein the shaking amount is reflected on a second row of pixels by taking a first row of pixels as a reference;
step (2), quantizing the analog quantity sensed by the two lines of pixels through an analog-to-digital converter, and transmitting the quantized analog quantity to a detection circuit;
generating a result of a jitter shift amount through a detection circuit;
step (4), transmitting the result of the jitter shift amount to a jitter compensation circuit after the analog-to-digital converter for shifting and simultaneously finishing jitter elimination;
and (5) finally, accumulating the analog-to-digital conversion quantization result after the jitter elimination by a digital accumulator to complete the perception of glimmer and eliminate the jitter brought by mechanical vibration.
The digital accumulator for eliminating the jitter comprises a detection circuit and a compensation circuit, wherein the circuit structure of the detection circuit is a cyclic shift circuit with a feedback function, the compensation circuit is formed by connecting a plurality of D triggers in series, the data output end of the D trigger at the previous stage is connected with the data input end of the D trigger at the next stage, so that a shift register ring is formed by the connection, and all D trigger clock signals CP are connected together and are connected with Shifter _ input of the detection circuit; analog quantity sensed by two rows of pixels is quantized through an analog-to-digital converter and is transmitted into a detection circuit, and the detection circuit outputs the analog quantity to a compensation circuit for reverse shift.
The detection circuit has the following specific structure: the outputs AD1, AD2 of the two analog-to-digital converters are connected to the corresponding memories M1, M2, M1, M2 are connected to the data inputs of D flip-flops D1, D2, respectively, the upper end of switch B is connected to the output of AD2, the lower end of switch B is connected to the data input of D flip-flop D2, the output of D2 is connected to the lower end of switch a and the left end of switch S2, the output of D1 is connected to the left end of S1, the right ends of S1 and S2 are connected to xor gate X, the output of xor gate X is connected to the high input of multiplexer MUX, the low input of MUX is connected to low level VSS, where the output of multiplexer MUX is connected to the inputs of N1, N2, N3, the original D flip-flop reset signal is connected to the input of N3, the output of N3 is connected to the RST 3, the original D flip-flop reset signal is connected to the inverted output of N3, the output of N2 is connected to the clock input CP2 of the D2 flip-flop, the inverted output of the original switch B clock signal Shifter _ input _ orig and MUX is connected to the input of N3, and the output of N3 is connected to switch B.
The digital accumulator circuit timing is as follows for the first column detection circuit: the signals of the pixels in the first row and the pixels in the second row are quantized by the analog-to-digital converter and are respectively transmitted to the latches M1 and M2 for latching, wherein S1, S2 and B are in an off state, which is a preparation state of the detection circuit, and the pixel quantization signals are stored in M1 and M2; then M1 and M2 are opened simultaneously, S1 and S2 are opened, clock signals CP1 and CP2 of the D flip-flops start to transmit simultaneously, the signals are divided into signals which start to shift through the respective D1 and D2, the signals arrive at an XOR gate to start to be compared, if the signals do not jitter, the results of the two signals are the same, the comparison result after the XOR gate is 1, the output result of the multiplexer is 1, the reset signal RST of the D flip-flop is set high through a feedback circuit, the CP2 signals are eliminated, the switch B is closed and does not transmit any more, and no jitter is detected; when the signal is jittered, the output of the exclusive-nor gate is 0, the output of the multiplexer is 0, the D flip-flop D1 in the feedback circuit is not reset, so the pixel quantization signal of the previous state is still stored in the switch a, which is opened by the feedback circuit, and is connected to the switch B of the next detection circuit, so that a shift register chain is formed, wherein the Shifter _ input signal is set to be a square wave signal and is faster than the CP2, in order to ensure that the signal is transmitted first and then shifted, and then the signal is shifted from left to right along with the triggering of the clock signal CP2, and the switches S1 and S2 are always in an open state, the timing of S1 and S2 is set to be faster than the timing of the CP2, and the shift must be performed after the comparison is completed, and by the cyclic comparison shift in this way, when the comparison results of two signals correspond to each other, the output of the multiplexer is 1, the subsequent output results are already described above and are not described again, then the detection circuit stops working, and the Shifter _ input only retains the square wave signal before shifting through the feedback circuit, so that the number of square waves of the signal is the number of cyclic shifts of the detection circuit, that is, the amount of jitter; the jitter amount is eliminated by outputting the jitter amount to a shift register behind a non-detection ADC for reverse shift, and finally, the corrected quantization result is accumulated for multiple times to complete counting.
The invention has the characteristics and beneficial effects that:
if the image sensor shakes, the comparison result of signals transmitted by the first CP clock rising edge of the detection circuit is inconsistent, the detection circuit can carry out cyclic shift, for example, shaking of two pixel units occurs on the image sensor, the results to be detected are consistent after twice shifting, the number of the detected shift results can be represented by the number of square waves of the Shifter _ input, and then the signals are transmitted to the compensation circuit to carry out reverse shift, so that the influence caused by shaking can be eliminated. Fig. 6 is a timing chart of the result of detecting two pixel shakes. Thus, the present invention achieves jitter cancellation for digital accumulators.
Description of the drawings:
the working principle of the CMOS-TDI image sensor is shown in figure 1.
Fig. 2 is a general architecture diagram of a jitter cancellation circuit.
FIG. 3 is a schematic diagram of a detection circuit.
FIG. 4 is a timing diagram of the detection circuit.
Fig. 5 a jitter compensation circuit diagram.
FIG. 6 is a timing chart of the detection results.
Detailed Description
The implementation mode of the invention is as follows:
fig. 2 is a circuit overall architecture diagram, the outputs of two rows of detection pixels are quantized by an analog-to-digital converter, the quantized results are received by a detection circuit to generate dither results, and the dither results are transmitted to a compensation circuit behind a normal photosensitive sensor analog-to-digital converter.
The working steps of the circuit structure are as follows:
detecting the horizontal shaking amount through two rows of detection pixels, wherein the shaking amount is reflected on a second row of pixels by taking a first row of pixels as a reference;
step (2), quantizing the analog quantity sensed by the two lines of pixels through an analog-to-digital converter, and transmitting the quantized analog quantity to a detection circuit;
generating a result of a jitter shift amount through a detection circuit;
step (4), transmitting the result of the jitter shift amount to a jitter compensation circuit after the analog-to-digital converter for shifting and simultaneously finishing jitter elimination;
and (5) finally, accumulating the analog-to-digital conversion quantization result after the jitter elimination by a digital accumulator to complete the perception of glimmer and eliminate the jitter brought by mechanical vibration.
The jitter detection circuit mainly comprises a detection circuit and a compensation circuit. Fig. 2 is a diagram of a detection circuit, and the circuit structure of the detection circuit is a cyclic shift circuit with a feedback function. The outputs AD1, AD2 of the two analog-to-digital converters are connected to the corresponding memories M1, M2, M1, M2 are connected to the data inputs of D flip-flops D1, D2, respectively, the upper end of switch B is connected to the output of AD2, the lower end of switch B is connected to the data input of D flip-flop D2, the output of D2 is connected to the lower end of switch a and the left end of switch S2, the output of D1 is connected to the left end of S1, the right ends of S1 and S2 are connected to xor gate X, the output of xor gate X is connected to the high input of multiplexer MUX, the low input of MUX is connected to low level VSS, where the output of multiplexer MUX is connected to the inputs of N1, N2, N3, the original D flip-flop reset signal is connected to the input of N3, the output of N3 is connected to the RST 3, the original D flip-flop reset signal is connected to the inverted output of N3, the output of N2 is connected to the clock input CP2 of the D2 flip-flop, the inverted output of the original switch B clock signal Shifter _ input _ orig and MUX is connected to the input of N3, and the output of N3 is connected to switch B.
Fig. 3 is a diagram of a compensation circuit, in which a plurality of D flip-flops are connected in series, a data output terminal of a D flip-flop of a previous stage is connected to a data input terminal of a D flip-flop of a next stage, and thus connected to form a shift register loop, and all D flip-flop clock signals CP are connected together and to a Shifter _ input of a detection circuit.
Fig. 4 is a timing diagram of the detection circuit, and since the circuit structure of each column is the same, only the principle of the first column detection circuit is explained here: the signals of the pixels in the first row and the pixels in the second row are quantized by the analog-to-digital converter and are respectively transmitted to the latches M1 and M2 for latching, wherein S1, S2 and B are in an off state, which is a state of preparation for the detection circuit, and the pixel quantization signals are stored in M1 and M2. Then M1 and M2 are opened simultaneously, S1 and S2 are opened, clock signals CP1 and CP2 of the D flip-flops start to transmit simultaneously, the signals are divided into signals which start to shift through the respective D1 and D2, the signals arrive at an XOR gate to start to be compared, if the signals do not jitter, the results of the two signals are the same, the comparison result after the XOR gate is 1, the result output by the multiplexer is 1, the reset signal RST of the D flip-flop is set high through a feedback circuit, the CP2 signals are eliminated, the switch B is closed and does not transmit any more, and no jitter is detected. When the signal is jittered, the output of the exclusive-nor gate is 0, the output of the multiplexer is 0, the D flip-flop D1 in the feedback circuit is not reset, so the pixel quantization signal of the previous state is still stored in the switch a, which is opened by the feedback circuit, and is connected to the switch B of the next detection circuit, so that a shift register chain is formed, wherein the Shifter _ input signal is set to be a square wave signal and is faster than the CP2, in order to ensure that the signal is transmitted first and then shifted, and then the signal is shifted from left to right along with the triggering of the clock signal CP2, and the switches S1 and S2 are always in an open state, the timing of S1 and S2 is set to be faster than the timing of the CP2, and the shift must be performed after the comparison is completed, and by the cyclic comparison shift in this way, when the comparison results of two signals correspond to each other, the output of the multiplexer is 1, the subsequent output results are described above and are not described again, and then the detection circuit stops working, and Shifter _ input only retains the square wave signal before shifting through the feedback circuit, so the number of square waves of the signal is the number of cyclic shifts of the detection circuit, that is, the amount of jitter. The jitter amount can be eliminated by outputting the jitter amount to a shift register after the non-detection ADC for reverse shift, and finally, the corrected quantization result is accumulated for multiple times to complete counting.
According to the technical scheme, the D trigger, the logic gate circuit, the multiplexer and the transmission gate switch are of typical structures, the storage unit is of a latch structure, the analog-to-digital converter recommends using a converter with short quantization period, such as a cyclic analog-to-digital converter (cycloADC), and the accumulator is a digital domain accumulator, so that the quantization result can be conveniently processed.
Fig. 4 is a timing diagram of the preferred embodiment. All detection timings should start accessing after the quantization of the adc is finished, wherein the reset signal of the D flip-flop should be accessed first, and the first clock rising edge of Shifter _ input is followed by the first clock rising edges of CP1 and CP2, so that the comparison of the first original signal is completed before the cyclic detection is considered. The first clock rising edge of S1& S2 should be between CP1, CP2 and the first clock rising edge of Shifter _ input.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (4)
1. A digital accumulator and a jitter elimination method are characterized by comprising the following steps:
detecting the horizontal shaking amount through two rows of detection pixels, wherein the shaking amount is reflected on a second row of pixels by taking a first row of pixels as a reference;
step (2), quantizing the analog quantity sensed by the two lines of pixels through an analog-to-digital converter, and transmitting the quantized analog quantity to a detection circuit;
generating a result of a jitter shift amount through a detection circuit;
step (4), transmitting the result of the jitter shift amount to a jitter compensation circuit after the analog-to-digital converter for shifting and simultaneously finishing jitter elimination;
and (5) finally, accumulating the analog-to-digital conversion quantization result after the jitter elimination by a digital accumulator to complete the perception of glimmer and eliminate the jitter brought by mechanical vibration.
2. A digital accumulator for eliminating jitter is characterized by comprising a detection circuit and a compensation circuit, wherein the circuit structure of the detection circuit is a cyclic shift circuit with a feedback function, the compensation circuit is formed by connecting a plurality of D triggers in series, the data output end of the D trigger at the previous stage is connected with the data input end of the D trigger at the next stage, the D triggers are connected in this way to form a shift register ring, and all clock signals CP of the D triggers are connected together and are connected with Shifter _ input of the detection circuit; analog quantity sensed by two rows of pixels is quantized through an analog-to-digital converter and is transmitted into a detection circuit, and the detection circuit outputs the analog quantity to a compensation circuit for reverse shift.
3. The digital accumulator for removing jitter of claim 2 wherein the detection circuit is configured as follows: the outputs AD1, AD2 of the two analog-to-digital converters are connected to the corresponding memories M1, M2, M1, M2 are connected to the data inputs of D flip-flops D1, D2, respectively, the upper end of switch B is connected to the output of AD2, the lower end of switch B is connected to the data input of D flip-flop D2, the output of D2 is connected to the lower end of switch a and the left end of switch S2, the output of D1 is connected to the left end of S1, the right ends of S1 and S2 are connected to xor gate X, the output of xor gate X is connected to the high input of multiplexer MUX, the low input of MUX is connected to low level VSS, where the output of multiplexer MUX is connected to the inputs of N1, N2, N3, the original D flip-flop reset signal is connected to the input of N3, the output of N3 is connected to the RST 3, the original D flip-flop reset signal is connected to the inverted output of N3, the output of N2 is connected to the clock input CP2 of the D2 flip-flop, the inverted output of the original switch B clock signal Shifter _ input _ orig and MUX is connected to the input of N3, and the output of N3 is connected to switch B.
4. The digital accumulator for debounce of claim 2, wherein the digital accumulator circuit is clocked as follows for the first column detection circuit: the signals of the pixels in the first row and the pixels in the second row are quantized by the analog-to-digital converter and are respectively transmitted to the latches M1 and M2 for latching, wherein S1, S2 and B are in an off state, which is a preparation state of the detection circuit, and the pixel quantization signals are stored in M1 and M2; then M1 and M2 are opened simultaneously, S1 and S2 are opened, clock signals CP1 and CP2 of the D flip-flops start to transmit simultaneously, the signals are divided into signals which start to shift through the respective D1 and D2, the signals arrive at an XOR gate to start to be compared, if the signals do not jitter, the results of the two signals are the same, the comparison result after the XOR gate is 1, the output result of the multiplexer is 1, the reset signal RST of the D flip-flop is set high through a feedback circuit, the CP2 signals are eliminated, the switch B is closed and does not transmit any more, and no jitter is detected; when the signal is jittered, the output of the exclusive-nor gate is 0, the output of the multiplexer is 0, the D flip-flop D1 in the feedback circuit is not reset, so the pixel quantization signal of the previous state is still stored in the switch a, which is opened by the feedback circuit, and is connected to the switch B of the next detection circuit, so that a shift register chain is formed, wherein the Shifter _ input signal is set to be a square wave signal and is faster than the CP2, in order to ensure that the signal is transmitted first and then shifted, and then the signal is shifted from left to right along with the triggering of the clock signal CP2, and the switches S1 and S2 are always in an open state, the timing of S1 and S2 is set to be faster than the timing of the CP2, and the shift must be performed after the comparison is completed, and by the cyclic comparison shift in this way, when the comparison results of two signals correspond to each other, the output of the multiplexer is 1, the subsequent output results are already described above and are not described again, then the detection circuit stops working, and the Shifter _ input only retains the square wave signal before shifting through the feedback circuit, so that the number of square waves of the signal is the number of cyclic shifts of the detection circuit, that is, the amount of jitter; the jitter amount is eliminated by outputting the jitter amount to a shift register behind a non-detection ADC for reverse shift, and finally, the corrected quantization result is accumulated for multiple times to complete counting.
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