CN113421903B - Display substrate, preparation method thereof, display panel and display device - Google Patents
Display substrate, preparation method thereof, display panel and display device Download PDFInfo
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- CN113421903B CN113421903B CN202110678498.7A CN202110678498A CN113421903B CN 113421903 B CN113421903 B CN 113421903B CN 202110678498 A CN202110678498 A CN 202110678498A CN 113421903 B CN113421903 B CN 113421903B
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/122—Pixel-defining structures or layers, e.g. banks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
- H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
Abstract
The embodiment of the disclosure provides a display substrate, a preparation method thereof, a display panel and a display device. The display substrate includes: a substrate; the active layer, the first insulating layer, the gate electrode, the second insulating layer, the source electrode and the drain electrode are positioned on one side of the substrate, and the first insulating layer and the second insulating layer are positioned in the display area and the metal wiring area; the metal wire is positioned in the metal wire area; the first flat layer is positioned in the display area and is positioned at one side of the source electrode and the drain electrode, which is away from the substrate; the second flat layer is positioned in the metal wiring area and is positioned on one side of the metal wiring, which is away from the substrate, and the thickness of at least part of the second flat layer is smaller than that of the first flat layer; an organic light emitting diode located on a side of the first planarization layer facing away from the substrate. According to the technical scheme, the shrinkage/expansion degree of the second flat layer when being subjected to heat/cold impact can be reduced, peeling or cracking of the film layers positioned on the upper side and the lower side of the second flat layer is avoided, and abnormal driving and packaging failure are avoided.
Description
Technical Field
The disclosure relates to the technical field of display, in particular to a display substrate, a preparation method thereof, a display panel and a display device.
Background
Organic Light-Emitting Diode (OLED) is a display lighting technology that has been developed in recent years, and in particular, in the display industry, OLED display has been considered to have a wide application prospect due to advantages of high response, high contrast, flexibility, and the like.
The OLED display substrate comprises a display area and a non-display area, wherein the non-display area comprises a metal wiring area. In the OLED display substrate in the prior art, film peeling or cracking easily occurs in a metal wiring area, so that abnormal OLED driving or packaging failure is caused.
Disclosure of Invention
The embodiment of the disclosure provides a display substrate, a preparation method thereof, a display panel and a display device, which are used for solving or relieving one or more technical problems in the prior art.
As a first aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display substrate including a display area and a metal routing area located outside the display area, the display substrate including:
a substrate;
the active layer, the gate electrode, the source electrode and the drain electrode are positioned in the display area, and the first insulating layer and the second insulating layer are positioned in the display area and the metal wiring area;
the metal wire is positioned in the metal wire area;
the first flat layer is positioned in the display area and is positioned at one side of the source electrode and the drain electrode, which is away from the substrate;
the second flat layer is positioned in the metal wiring area and is positioned on one side of the metal wiring, which is away from the substrate, and the thickness of at least part of the second flat layer is smaller than that of the first flat layer;
the organic light emitting diodes are positioned in the display area and at one side of the first flat layer, which is away from the substrate, and the organic light emitting diodes are connected with the source electrode or the drain electrode.
In some possible implementations, the thickness of the second planar layer ranges from 0.5 μm to 4 μm.
In some possible implementations, the second planar layer includes a first portion and a second portion, the front projection of the first portion on the substrate overlapping the front projection of the metal trace on the substrate, the front projection of the second portion on the substrate not overlapping the front projection of the metal trace on the substrate, and a distance between a surface of the first portion on a side remote from the substrate and the substrate is greater than a distance between a surface of the second portion on a side remote from the substrate and the substrate.
In some possible implementations, the display substrate further includes:
the metal connecting layer is positioned in the display area and is positioned at one side of the first flat layer, which is away from the substrate;
the third flat layer is positioned in the display area and is positioned on one side of the metal connecting layer, which is away from the substrate.
In some possible implementations, the display substrate further includes a fourth flat layer, where the fourth flat layer is located in the metal routing area and is located on a side of the second flat layer facing away from the substrate, and at least a portion of the thickness of the fourth flat layer is smaller than the thickness of the third flat layer.
In some possible implementations, the second planarization layer and the first planarization layer are formed by a single patterning process.
In some possible implementations, the second flat layer and the first flat layer are made of the same material, and the second flat layer and the first flat layer are made of negative photoresist or negative photoresist.
In some possible implementations, the metal trace is located at the same layer as the source or drain electrode.
In some possible implementations, the display area is provided with a plurality of signal lines, and the display substrate further includes a bonding area, and the metal wires are used for connecting the signal lines with pads of the bonding area.
As a second aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a method for manufacturing a display substrate, where the display substrate includes a display area and a metal routing area located outside the display area, the method including:
forming an active layer, a first insulating layer, a gate electrode, a second insulating layer, a source electrode, a drain electrode and a metal wire on one side of a substrate, wherein the active layer, the gate electrode, the source electrode and the drain electrode are positioned in a display area, the first insulating layer and the second insulating layer are positioned in the display area and the metal wire area, and the metal wire is positioned in the metal wire area;
forming a first flat layer positioned in the display area on one side of the source electrode and the drain electrode, which is away from the substrate, and forming a second flat layer positioned in the metal wiring area on one side of the metal wiring, which is away from the substrate, wherein the thickness of the second flat layer is smaller than that of the first flat layer;
a plurality of organic light emitting diodes are formed on one side of the first flat layer, which is away from the substrate, and the organic light emitting diodes are connected with the source electrode or the drain electrode.
In some possible implementations, forming a first planar layer in the display region on a side of the source and drain electrodes facing away from the substrate, and forming a second planar layer in the metal trace region on a side of the metal trace facing away from the substrate, includes:
forming a flat film on one side of the source electrode, the drain electrode and the metal wire, which is away from the substrate, by adopting a coating process;
and exposing and developing the flat film by adopting a half-tone mask, forming a first via hole in the display area to form a first flat layer in the display area, and removing part of the flat film in the metal wiring area along the direction vertical to the substrate to form a second flat layer in the metal wiring area, wherein the thickness of the second flat layer is smaller than that of the first flat layer.
As a third aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display panel, including the display substrate in any one of the embodiments of the present disclosure, and further including a cover glass, where the cover glass is attached to the display substrate opposite to the display substrate.
As a fourth aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display device including the display substrate in any of the embodiments of the present disclosure, or including the display panel in any of the embodiments of the present disclosure.
According to the display substrate provided by the embodiment of the disclosure, the first flat layer is arranged in the display area, the organic light emitting diode is positioned on one side of the first flat layer, which is away from the base, so that the planarization requirement of OLED pixels formed by adopting ink-jet printing in the display area can be met, and the lighting uniformity of the OLED pixels can be ensured; the second flat layer is arranged on one side of the metal wire, which is away from the substrate, and can protect the metal wire, prevent the metal wire from being scratched, and prevent the drive signal crosstalk between the metal wires. In addition, the thickness of at least part of the second flat layer is smaller than that of the first flat layer, so that the thickness of at least part of the second flat layer is reduced, the shrinkage/expansion degree of the second flat layer when being subjected to heat/cold impact is reduced, stripping or cracking of film layers of the metal routing area on the upper side and the lower side of the second flat layer is avoided, and driving abnormality and packaging failure are avoided.
The foregoing summary is for the purpose of the specification only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present disclosure will become apparent by reference to the drawings and the following detailed description.
Drawings
In the drawings, the same reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily drawn to scale. It is appreciated that these drawings depict only some embodiments according to the disclosure and are not to be considered limiting of its scope.
FIG. 1 is a schematic plan view of an OLED display substrate;
FIG. 2 is a schematic cross-sectional view of a display substrate according to an embodiment of the disclosure;
FIG. 3 is a schematic view of a cross-section A-A of FIG. 1 of a substrate according to an embodiment of the disclosure;
FIG. 4 is a schematic cross-sectional view of a display substrate according to another embodiment of the disclosure;
FIG. 5 is a schematic diagram of a display substrate according to an embodiment of the present disclosure after source and drain electrodes are formed;
FIG. 6a is a schematic diagram of a display substrate after a flat film is formed in accordance with one embodiment of the present disclosure;
fig. 6b is a schematic diagram of a substrate after forming a first flat layer and a second flat layer according to an embodiment of the disclosure.
Reference numerals illustrate:
10. a display area; 20. a metal wiring region; 21. a metal wiring; 30. binding area; 31. a substrate; 321. an active layer; 322. a gate electrode; 323a, a source electrode; 323b drain electrode; 36. a pixel defining layer; 51. a first insulating layer; 52. a second insulating layer; 53. a buffer layer; 54', a flat film; 541. a first planarization layer; 542. a second flat layer; 542a, first portion; 542b, second portion; 55', a third insulating film; 55. a third insulating layer; 561. a third planarization layer; 562. a fourth flat layer; 57. a metal connection layer; 70. an organic light emitting diode; 71. a first electrode; 72. an organic light emitting layer; 73. a second electrode; 81. and a first via.
Detailed Description
Hereinafter, only certain exemplary embodiments are briefly described. As will be recognized by those of skill in the pertinent art, the described embodiments may be modified in various different ways without departing from the spirit or scope of the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.
Fig. 1 is a schematic plan view of an OLED display substrate. As shown in fig. 1, the OLED display substrate includes a display area 10 provided with a plurality of organic light emitting diodes 70 and a non-display area including a metal routing area 20 and a bonding area 30, the metal routing area 20 is provided with a plurality of metal routing wires 21 for connecting signal wires of the display area 10 with pads (pads) of the bonding area 30. The display area 10 is provided with a plurality of OLED pixels. In the top-emission OLED display substrate, in order to ensure uniformity of OLED pixel lighting, a planarization layer is required to planarize a display area. In the related art, the display area 10 may be planarized using a negative photoresist resin material having a large thickness. In a routing area (i.e., a metal routing area) of a Bonding Pad (Bonding Pad) of an OLED display substrate, a planarization resin material layer is disposed in the metal routing area 20 in order to prevent the metal routing from being scratched and to prevent driving signal crosstalk between the metal routing. Since the thickness of the resin material layer is relatively large (greater than or equal to 1 μm), when the display substrate on which the resin material layer is formed is baked at a high temperature (for example, baked for 139 hours at 80 ℃), shrinkage/expansion along the plane of the film layer easily occurs due to heating/cooling of the resin material layer, and when the shrinkage/expansion is to a certain extent, peeling and cracking of the film layer due to different shrinkage/expansion degrees occur in the film layers on the upper side and the lower side of the resin material layer in the metal routing area, so that driving abnormality or package failure of the OLED pixels occurs.
In order to solve the technical problems, embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device.
Fig. 2 is a schematic cross-sectional structure of a display substrate according to an embodiment of the disclosure. A schematic plan view of a display substrate according to an embodiment of the disclosure may be shown in fig. 1, and in one implementation, as shown in fig. 1 and 2, the display substrate may include a display area 10 and a metal routing area 20, where the metal routing area 20 is located outside the display area 10. The display substrate may include a base 31, and may further include an active layer 321, a first insulating layer 51 (may also be called a gate insulating layer), a gate electrode 322, a second insulating layer 52 (may also be called an interlayer insulating layer), a source electrode 323a, and a drain electrode 323b, which are located on one side of the base 31. Among them, the active layer 321, the gate electrode 322, the source electrode 323a and the drain electrode 323b are located in the display region 10, and the first insulating layer 51 and the second insulating layer 52 may be located in the display region 10 and the metal wiring region 20.
The display substrate may further include a metal trace 21, where the metal trace 21 is located in the metal trace region 20. It will be appreciated that the display area 10 is provided with a plurality of signal lines, such as gate lines, data lines, etc., and the display substrate may further include a bonding area 30, and the metal traces 21 are used to connect the signal lines of the display area 10 with pads (pads) of the bonding area 30.
As shown in fig. 2, the display substrate may further include a first planarization layer 541 and a second planarization layer 542, the first planarization layer 541 being located in the display area 10, the first planarization layer 541 being located at a side of the source electrode 323a and the drain electrode 232b facing away from the substrate 31. The second flat layer 542 is located in the metal wiring region 20, the second flat layer 542 is located on a side of the metal wiring 21 facing away from the substrate 31, and at least a portion of the thickness of the second flat layer 542 is smaller than that of the first flat layer 541. It is understood that the thickness is the dimension of the film layer in a direction perpendicular to the substrate, for example, the thickness of the second flat layer is the dimension of the second flat layer in a direction perpendicular to the substrate, and the thickness of the first flat layer is the dimension of the first flat layer in a direction perpendicular to the substrate. The display substrate may further include a plurality of organic light emitting diodes 70, the plurality of organic light emitting diodes 70 being disposed in the display region 10 and on a side of the first planarization layer 541 facing away from the substrate 31, the organic light emitting diodes 70 being connected to the source electrode 323a or the drain electrode 323b.
In the display substrate of the embodiment of the disclosure, the first flat layer 541 is disposed in the display area 10, and the organic light emitting diode 70 is located on the side of the first flat layer 541 away from the substrate 31, so that the planarization requirement of forming the OLED pixels in the display area 10 by adopting inkjet printing can be met, and the uniformity of lighting the OLED pixels can be ensured; the second flat layer 542 is disposed on a side of the metal wires 21 facing away from the substrate 31, and the second flat layer 542 can protect the metal wires 21, prevent the metal wires 21 from being scratched, and prevent crosstalk of driving signals between the metal wires 21. Compared to the case where the thickness of the second flat layer is the same as that of the first flat layer in the related art, in the display substrate of the embodiment of the disclosure, the thickness of at least part of the second flat layer 542 is smaller than that of the first flat layer 541, so that the thickness of at least part of the second flat layer 542 is thinned, for example, the thickness of at least part of the second flat layer 542 is smaller than 1 μm, which reduces the shrinkage/expansion degree of the second flat layer 542 when being subjected to heat/cold impact, and is beneficial to avoiding peeling or cracking of the film layers of the metal routing region 20 on the upper side and the lower side of the second flat layer 542, and avoiding driving abnormality and package failure.
In one embodiment, the thickness d1 of the first flat layer 541 ranges from 1 μm to 5 μm (inclusive), and the thickness d2 of the second flat layer 542 ranges from 0.5 μm to 4 μm (inclusive). Setting the thickness of the second flat layer 524 to be in the range of 0.5 μm to 4 μm (inclusive), the shrinkage/expansion degree of the second flat layer 542 under the heat/cold impact can be further reduced, and the film layers of the metal routing area 20 on the upper and lower sides of the second flat layer 542 are prevented from peeling or cracking, and driving abnormality and package failure are prevented. Illustratively, the thickness d1 of the first flat layer 541 may be any value from 1 μm to 5 μm, for example, the thickness d1 of the first flat layer 541 may be one of 1 μm, 2 μm, 3 μm, 4 μm, 5 μm. Illustratively, the thickness d2 of the second flat layer 542 may be any value from 0.5 μm to 4 μm, for example, the thickness d2 of the second flat layer 542 may be one of 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm.
Fig. 3 is a schematic view of a cross section A-A of fig. 1 of a substrate according to an embodiment of the disclosure. In one embodiment, as shown in fig. 3, second planar layer 542 may include a first portion 542a and a second portion 542b, where the front projection of first portion 542a onto substrate 31 overlaps the front projection of metal trace 21 onto substrate 31, and the front projection of second portion 542b onto substrate 31 does not overlap the front projection of metal trace 21 onto substrate 31. The distance d3 between the surface of the first portion 542a on the side away from the substrate 31 and the substrate 31 is greater than the distance d4 between the surface of the second portion 542b on the side away from the substrate 31 and the substrate 31, that is, d3 is greater than d4. Such a second planarization layer, the first portion 542a corresponding to the metal wire 21 may better protect the metal wire 21 and may better prevent the metal wire 21 from being scratched.
In one embodiment, the second and first planarization layers 542 and 541 are formed simultaneously, that is, the second and first planarization layers 542 and 541 are formed by one patterning process. Therefore, the number of masks can be reduced, and the manufacturing process of the display substrate can be simplified.
In one embodiment, the materials of both the second and first planarization layers 542 and 541 may be organic materials, such as resin materials.
In one embodiment, the second flat layer 542 and the first flat layer 541 are made of the same material, and the second flat layer 542 and the first flat layer 541 may be made of a positive photoresist or a negative photoresist.
In one embodiment, as shown in fig. 2, the display substrate may further include a third insulating layer 55 (may also be referred to as a passivation layer PVX), the third insulating layer 55 being located in the display region 10 and/or the metal routing region 20, the third insulating layer 55 being located between the first planarization layer 541 and the source and drain electrodes 323a and 323b.
In one embodiment, the metal trace 21 may be located at the same layer as the source electrode 323a or the drain electrode 323b, that is, the metal trace 21 may be formed with the source electrode 323a or the drain electrode 323b through one patterning process.
Illustratively, in fig. 2, the active layer 321 is located on a side of the substrate 31, the first insulating layer 51 is located on a side of the active layer 321 facing away from the substrate 31, the gate electrode 322 is located on a side of the first insulating layer 51 facing away from the substrate 31, the second insulating layer 52 is located on a side of the gate electrode 322 facing away from the substrate 31, and the source electrode 323a and the drain electrode 323b are located on a side of the second insulating layer 52 facing away from the substrate 31. The thin film transistor is shown in fig. 2, and may include an active layer 321, a gate electrode 322, a source electrode 323a, and a drain electrode 323b, and the thin film transistor shown in fig. 2 is a top gate thin film transistor, and in other embodiments, the thin film transistor may be a bottom gate thin film transistor. It is understood that the display substrate of the present embodiment has no selection requirement for the type of the thin film transistor, as long as the performance of the thin film transistor can be achieved.
As shown in fig. 2, the organic light emitting diode 70 includes a first electrode 71, an organic light emitting layer 72, and a second electrode 73. The first electrode 71 may be an anode and the second electrode 73 may be a cathode. The first electrode 71 is located in the display region, and the first electrode 71 is located at a side of the first planarization layer 541 facing away from the substrate 31. The first electrode 71 is connected to the source electrode 323a or the drain electrode 323b of the corresponding thin film transistor. The display substrate further includes a pixel defining layer 36, the pixel defining layer 36 is located in the display area 10, and the pixel defining layer 36 is provided with a plurality of openings, each opening exposing a corresponding first electrode 71. The organic light emitting layer 72 is located in the opening and on a side of the first electrode 71 facing away from the substrate 31, and the second electrode 73 is located on a side of the organic light emitting layer 72 facing away from the substrate 31.
In one embodiment, as shown in fig. 2, the display substrate may further include a buffer layer 53, and the buffer layer 53 may be located between the base 31 and the active layer 321.
It will be appreciated that the display substrate may further include an encapsulation passivation layer (not shown) which may be located on a side of the organic light emitting diode 70 facing away from the substrate 31, and the encapsulation passivation layer may be located on the display region 10 and the metal routing region 20.
Fig. 4 is a schematic cross-sectional view of a display substrate according to another embodiment of the disclosure. As shown in fig. 4, the display substrate may further include a metal connection layer 57 and a third planarization layer 561. The metal connection layer 57 is located in the display area, and the metal connection layer 57 may be located at a side of the first planarization layer 541 facing away from the substrate 31. The third planarization layer 561 may be located in the display area and on a side of the metal connection layer 57 facing away from the substrate 31. The first electrode 71 may be connected to the source electrode 323a or the drain electrode 323b of the corresponding thin film transistor through the metal connection layer 57.
In one embodiment, as shown in fig. 4, the display substrate may further include a fourth flat layer 562, where the fourth flat layer 562 is located in the metal routing area and is located on a side of the second flat layer 542 facing away from the substrate 31, and at least a portion of the thickness of the fourth flat layer 562 is smaller than the thickness of the third flat layer 561, where it is understood that the thickness is a dimension of the film layer in a direction perpendicular to the substrate.
The specific thicknesses of the third and fourth planarization layers 561 and 562 are not limited herein and may be set as needed.
Illustratively, the fourth flat layer 562 may include a third portion and a fourth portion, an orthographic projection of the third portion on the substrate 31 overlapping an orthographic projection of the metal trace 21 on the substrate 31, an orthographic projection of the fourth portion on the substrate 31 not overlapping an orthographic projection of the metal trace 21 on the substrate 31, and a distance between a surface of the third portion on a side away from the substrate 31 and the substrate 31 may be greater than a distance between a surface of the fourth portion on a side away from the substrate 31 and the substrate 31.
It will be appreciated that other film layers may be provided between the second flat layer 542 and the fourth flat layer 562 as may be desired.
Illustratively, the third and fourth planarization layers 561 and 562 may be formed through a one-time patterning process. The third planarization layer 561 and the fourth planarization layer 562 may be made of the same material. The third planarization layer 561 and the fourth planarization layer 562 may be made of a negative photoresist or a positive photoresist.
In an exemplary embodiment, the first, second, third, and buffer layers may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer, or a composite layer. A Buffer (Buffer) layer for improving the water-oxygen resistance of the substrate, the first insulating layer may be referred to as a Gate Insulating (GI) layer, and the second insulating layer may be referred to as an interlayer Insulating (ILD) layer. The gate electrode, the source electrode, the drain electrode, and the metal wiring may be made of a metal material such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single-layer structure, or a multi-layer composite structure such as Ti/Al/Ti, or the like. The pixel defining layer may be polyimide, acryl, polyethylene terephthalate, or the like. The active layer may be made of various materials such as amorphous indium gallium zinc Oxide (a-IGZO), zinc oxynitride (ZnON), indium Zinc Tin Oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, polythiophene, etc., i.e., the present disclosure is applicable to transistors manufactured based on Oxide technology, silicon technology, and organic technology.
The thickness of the remaining film layers in the display substrate may be set as needed without particular limitation.
The display substrate of the embodiment of the disclosure may be an OLED display substrate, and the substrate may be a hard material such as glass, or may be a flexible material such as Polyimide (PI), or the like.
The embodiment of the disclosure also provides a method for preparing a display substrate, wherein the display substrate may include a display region and a metal wiring region located outside the display region, and the method for preparing the display substrate may include:
forming an active layer, a first insulating layer, a gate electrode, a second insulating layer, a source electrode, a drain electrode and a metal wire on one side of a substrate, wherein the active layer, the gate electrode, the source electrode and the drain electrode are positioned in a display area, the first insulating layer and the second insulating layer are positioned in the display area and the metal wire area, and the metal wire is positioned in the metal wire area;
forming a first flat layer positioned in the display area on one side of the source electrode and the drain electrode, which is away from the substrate, and forming a second flat layer positioned in the metal wiring area on one side of the metal wiring, which is away from the substrate, wherein the thickness of the second flat layer is smaller than that of the first flat layer;
a plurality of organic light emitting diodes are formed on one side of the first flat layer, which is away from the substrate, and the organic light emitting diodes are connected with the source electrode or the drain electrode.
In one embodiment, forming a first flat layer in the display region on a side of the source electrode and the drain electrode facing away from the substrate, and forming a second flat layer in the metal wiring region on a side of the metal wiring facing away from the substrate, includes:
forming a flat film on one side of the source electrode, the drain electrode and the metal wire, which is away from the substrate, by adopting a coating process;
and exposing and developing the flat film by adopting a half-tone mask, forming a first via hole in the display area to form a first flat layer in the display area, and removing part of the flat film in the metal wiring area along the direction vertical to the substrate to form a second flat layer in the metal wiring area, wherein the thickness of the second flat layer is smaller than that of the first flat layer.
The technical solution of the embodiment of the present disclosure is further described below by the preparation process of the display substrate in the embodiment shown in fig. 2. It should be understood that, as used herein, the term "patterning" includes processes such as photoresist coating, mask exposure, development, etching, photoresist stripping, etc. when the patterned material is inorganic or metal, and processes such as mask exposure, development, etc. when the patterned material is organic, evaporation, deposition, coating, etc. are all well-known processes in the related art.
Forming an active layer, a first insulating layer, a gate electrode, a second insulating layer, a source electrode, a drain electrode, and a metal trace on one side of a substrate, the steps may include: as shown in fig. 5, fig. 5 is a schematic view of a substrate according to an embodiment of the present disclosure after forming a source electrode and a drain electrode, and depositing a buffer film on one side of a base 31 to form a buffer layer 53; depositing an active film on one side of the buffer layer 53 away from the substrate 31, and patterning the active film to form an active layer 321 located in the display area 10; depositing a first insulating film on a side of the active layer 321 facing away from the substrate 31; depositing a gate metal film on a side of the first insulating film facing away from the substrate 31, and patterning the gate metal film to form a gate electrode 322 and a gate line (not shown) in the display area 10; depositing a second insulating film on one side of the gate electrode 322 facing away from the substrate 31, performing patterning treatment on the second insulating film and the first insulating film to form a second via hole and a third via hole penetrating through the second insulating film and the first insulating film, wherein the second via hole and the third via hole expose the active layer 321, thereby forming a first insulating layer 51 and a second insulating layer 52, and the first insulating layer 51 and the second insulating layer 52 are positioned in the display area 10 and the metal wiring area 20; a source-drain metal film is deposited on a side of the second insulating layer 52 facing away from the substrate 31, and patterned to form the metal traces 21 in the metal trace region 20 and the source electrode 323a and the drain electrode 323b in the display region 10. The source electrode 323a and the drain electrode 323b are connected to the active layer 321 through a second via hole and a third via hole, respectively. Illustratively, the source and drain electrodes are formed simultaneously with the formation of the data lines (not shown) in the display region.
And forming a first flat layer positioned in the display area on one side of the source electrode and the drain electrode, which is away from the substrate, and forming a second flat layer positioned in the metal wiring area on one side of the metal wiring, which is away from the substrate, wherein the thickness of the second flat layer is smaller than that of the first flat layer. This step may include: forming a third insulating film 55' on the source electrode 323a, the drain electrode 323b, and the side of the metal wire 21 facing away from the substrate 31, and forming a flat film 54' on the side of the third insulating film 55' facing away from the substrate 31 by a coating process, as shown in fig. 6a, fig. 6a is a schematic view of the substrate after forming the flat film in an embodiment of the disclosure; the flat film 54' is exposed and developed using a Halfstone Mask (Halfstone Mask), a first via 81 is formed in the display area 10 to form a first flat layer 541, a portion of the flat film located in the metal routing area 20 is removed in a direction perpendicular to the substrate 31, and the remaining flat film in the metal routing area 20 forms a second flat layer 542, as shown in fig. 6b, fig. 6b is a schematic view of the display substrate after forming the first flat layer and the second flat layer in an embodiment of the present disclosure. Illustratively, the thickness of the second flat layer 542 is less than the thickness of the first flat layer 541, the thickness of the first flat layer 541 ranges from 1 μm to 5 μm (inclusive), and the thickness of the second flat layer 542 ranges from 0.5 μm to 3 μm (inclusive). Wherein, the orthographic projection of the first via 81 on the substrate 31 is within the range of the orthographic projection of the drain electrode 323b on the substrate 31. The first via hole 81 is dry etched to etch away the remaining flat film and the third insulating film of the first via hole 81, so that the first via hole 81 exposes the drain electrode 323b, as shown in fig. 6 b.
A first electrode 71 formed on a side of the first flat layer 541 facing away from the substrate 31, the first electrode 71 being located in the display region, the first electrode 71 being connected to the drain electrode 323b of the thin film transistor through the first via 81; forming a pixel defining layer 36 on a side of the first electrode 71 facing away from the substrate 31, the pixel defining layer 36 being located in the display area, the pixel defining layer 36 being provided with a plurality of openings, each opening exposing a corresponding first electrode 71, as shown in fig. 2; forming an organic light emitting layer 72 by vapor deposition, sputtering, or electron beam deposition; the second electrode 73 is formed on a side of the organic light emitting layer 72 facing away from the substrate 31, and the material of the second electrode 73 may be a transparent conductive material such as indium tin oxide or indium zinc oxide. The organic light emitting layer 72 may be formed by inkjet printing, for example.
An encapsulation passivation layer (not shown) is formed on a side of the second electrode 73 facing away from the substrate 31.
The embodiment of the disclosure also provides a display panel, which comprises the display substrate and the cover glass in any embodiment of the disclosure, wherein one side of the cover glass facing the display substrate is coated with packaging adhesive material, and the cover glass and the display substrate are bonded through a packaging bonding process.
Based on the inventive concept of the foregoing embodiments, the present disclosure also provides a display device including a display substrate employing the foregoing embodiments. The display device may be: any product or component with display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
In the description of the present specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present disclosure.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present disclosure, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; the device can be mechanically connected, electrically connected and communicated; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art as the case may be.
In this disclosure, unless expressly stated or limited otherwise, a first feature being "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other by way of additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is less level than the second feature.
The above disclosure provides many different embodiments or examples for implementing different structures of the disclosure. The components and arrangements of specific examples are described above in order to simplify the present disclosure. Of course, they are merely examples and are not intended to limit the present disclosure. Furthermore, the present disclosure may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed.
The above is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think of various changes or substitutions within the technical scope of the disclosure, which should be covered in the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (11)
1. A display substrate, wherein the display substrate includes a display area and a metal routing area located outside the display area, the display substrate comprising:
a substrate;
the active layer, the gate electrode, the source electrode and the drain electrode are positioned in a display area, and the first insulating layer and the second insulating layer are positioned in the display area and the metal wiring area;
the metal wire is positioned in the metal wire area;
the first flat layer is positioned in the display area and is positioned on one side of the source electrode and the drain electrode, which is away from the substrate;
a second planarization layer located on a side of the metal trace area facing away from the substrate, at least a portion of the second planarization layer having a thickness smaller than a thickness of the first planarization layer, the thickness being a dimension perpendicular to the substrate, the second planarization layer including a first portion and a second portion, an orthographic projection of the first portion on the substrate overlapping an orthographic projection of the metal trace on the substrate, the orthographic projection of the second portion on the substrate not overlapping an orthographic projection of the metal trace on the substrate, a distance between a surface of the first portion on a side facing away from the substrate and the substrate being greater than a distance between a surface of the second portion on a side facing away from the substrate and the substrate, the second planarization layer and the first planarization layer being formed by a patterning process;
the organic light emitting diodes are positioned in the display area and on one side of the first flat layer, which is away from the substrate, and are connected with the source electrode or the drain electrode.
2. The display substrate according to claim 1, wherein a thickness of the second flat layer ranges from 0.5 μm to 4 μm.
3. The display substrate of claim 1, wherein the display substrate further comprises:
the metal connecting layer is positioned in the display area and is positioned on one side of the first flat layer, which is away from the substrate;
the third flat layer is positioned in the display area and is positioned on one side of the metal connecting layer, which is away from the substrate.
4. A display substrate according to claim 3, further comprising a fourth planar layer, the fourth planar layer being located in the metal routing region and on a side of the second planar layer facing away from the base, at least a portion of the fourth planar layer having a thickness less than a thickness of the third planar layer.
5. The display substrate according to claim 1, wherein the second planarization layer and the first planarization layer are made of the same material, and the second planarization layer and the first planarization layer are made of a negative photoresist or a positive photoresist.
6. The display substrate according to any one of claims 1 to 5, wherein the metal wiring is located at the same layer as the source electrode or the drain electrode.
7. The display substrate according to any one of claims 1 to 5, wherein the display region is provided with a plurality of signal lines, the display substrate further comprising a bonding region, the metal trace being for connecting the signal line with a pad of the bonding region.
8. A method for manufacturing a display substrate, wherein the display substrate includes a display area and a metal routing area located outside the display area, the method comprising:
forming an active layer, a first insulating layer, a gate electrode, a second insulating layer, a source electrode, a drain electrode and a metal wire on one side of a substrate, wherein the active layer, the gate electrode, the source electrode and the drain electrode are positioned in a display area, the first insulating layer and the second insulating layer are positioned in the display area and the metal wire area, and the metal wire is positioned in the metal wire area;
forming a first flat layer in a display area on one side of the source electrode and the drain electrode, which is away from the substrate, and forming a second flat layer in a metal wiring area on one side of the metal wiring, which is smaller than the first flat layer, wherein the second flat layer comprises a first part and a second part, the front projection of the first part on the substrate is overlapped with the front projection of the metal wiring on the substrate, the front projection of the second part on the substrate is not overlapped with the front projection of the metal wiring on the substrate, and the distance between the surface of the first part, which is far away from the substrate, and the substrate is larger than the distance between the surface of the second part, which is far away from the substrate, and the substrate;
and forming a plurality of organic light emitting diodes positioned in the display area on one side of the first flat layer, which is away from the substrate, wherein the organic light emitting diodes are connected with the source electrode or the drain electrode.
9. The method of manufacturing according to claim 8, wherein forming a first flat layer in a display region on a side of the source electrode and the drain electrode facing away from the substrate, and forming a second flat layer in a metal wiring region on a side of the metal wiring facing away from the substrate, comprises:
forming a flat film on one side of the source electrode, the drain electrode and the metal wire, which is away from the substrate, by adopting a coating process;
and exposing and developing the flat film by adopting a half-tone mask, forming a first via hole in the display area to form a first flat layer positioned in the display area, and removing part of the flat film positioned in the metal wiring area along the direction vertical to the substrate to form a second flat layer positioned in the metal wiring area, wherein the thickness of the second flat layer is smaller than that of the first flat layer.
10. A display panel comprising the display substrate according to any one of claims 1 to 7, and further comprising cover glass bonded to the display substrate.
11. A display device comprising the display substrate according to any one of claims 1 to 7, or comprising the display panel according to claim 10.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109560088A (en) * | 2018-12-19 | 2019-04-02 | 武汉华星光电半导体显示技术有限公司 | Flexible display substrates and preparation method thereof |
| CN110265576A (en) * | 2019-06-27 | 2019-09-20 | 昆山工研院新型平板显示技术中心有限公司 | A kind of packaging method of display panel, display panel and display device |
| KR20200063122A (en) * | 2020-05-26 | 2020-06-04 | 삼성디스플레이 주식회사 | Organic light emitting display apparatus and the manufacturing method thereof |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101283366B1 (en) * | 2008-12-23 | 2013-07-08 | 엘지디스플레이 주식회사 | An Electrophoretic display device and method of fabricating the same |
| KR102117612B1 (en) * | 2013-08-28 | 2020-06-02 | 삼성디스플레이 주식회사 | Organic light emitting display apparatus and the manufacturing method thereof |
| CN104716164A (en) * | 2015-03-27 | 2015-06-17 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof and organic light-emitting display device |
| CN105552077B (en) * | 2016-02-16 | 2019-05-03 | 武汉华星光电技术有限公司 | Thin-film transistor array base-plate and preparation method thereof, touch display panel |
| JP2019049608A (en) * | 2017-09-08 | 2019-03-28 | 株式会社ジャパンディスプレイ | Display |
| KR102491276B1 (en) * | 2018-05-14 | 2023-01-26 | 삼성디스플레이 주식회사 | Organic light emitting diode display device |
| KR20200053991A (en) * | 2018-11-09 | 2020-05-19 | 엘지디스플레이 주식회사 | Display device |
-
2021
- 2021-06-18 CN CN202110678498.7A patent/CN113421903B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109560088A (en) * | 2018-12-19 | 2019-04-02 | 武汉华星光电半导体显示技术有限公司 | Flexible display substrates and preparation method thereof |
| CN110265576A (en) * | 2019-06-27 | 2019-09-20 | 昆山工研院新型平板显示技术中心有限公司 | A kind of packaging method of display panel, display panel and display device |
| KR20200063122A (en) * | 2020-05-26 | 2020-06-04 | 삼성디스플레이 주식회사 | Organic light emitting display apparatus and the manufacturing method thereof |
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