CN113421903A - Display substrate, preparation method thereof, display panel and display device - Google Patents
Display substrate, preparation method thereof, display panel and display device Download PDFInfo
- Publication number
- CN113421903A CN113421903A CN202110678498.7A CN202110678498A CN113421903A CN 113421903 A CN113421903 A CN 113421903A CN 202110678498 A CN202110678498 A CN 202110678498A CN 113421903 A CN113421903 A CN 113421903A
- Authority
- CN
- China
- Prior art keywords
- substrate
- layer
- display
- area
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 199
- 238000002360 preparation method Methods 0.000 title claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 134
- 239000002184 metal Substances 0.000 claims abstract description 134
- 239000000463 material Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 238000000059 patterning Methods 0.000 claims description 10
- 230000008569 process Effects 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 6
- 239000006059 cover glass Substances 0.000 claims description 6
- 230000002159 abnormal effect Effects 0.000 abstract description 6
- 238000004806 packaging method and process Methods 0.000 abstract description 4
- 230000008602 contraction Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 247
- 239000010408 film Substances 0.000 description 39
- 239000010409 thin film Substances 0.000 description 11
- 239000011347 resin Substances 0.000 description 8
- 229920005989 resin Polymers 0.000 description 8
- 238000000151 deposition Methods 0.000 description 6
- 238000005538 encapsulation Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000002161 passivation Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 238000007641 inkjet printing Methods 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 241000251468 Actinopterygii Species 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- -1 acryl Chemical group 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- UBSJOWMHLJZVDJ-UHFFFAOYSA-N aluminum neodymium Chemical compound [Al].[Nd] UBSJOWMHLJZVDJ-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- DTSBBUTWIOVIBV-UHFFFAOYSA-N molybdenum niobium Chemical compound [Nb].[Mo] DTSBBUTWIOVIBV-UHFFFAOYSA-N 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000000313 electron-beam-induced deposition Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- HRHKULZDDYWVBE-UHFFFAOYSA-N indium;oxozinc;tin Chemical compound [In].[Sn].[Zn]=O HRHKULZDDYWVBE-UHFFFAOYSA-N 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920000139 polyethylene terephthalate Polymers 0.000 description 1
- 239000005020 polyethylene terephthalate Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229920000123 polythiophene Polymers 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/122—Pixel-defining structures or layers, e.g. banks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
- H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
Abstract
The embodiment of the disclosure provides a display substrate, a preparation method of the display substrate, a display panel and a display device. The display substrate includes: a substrate; the active layer, the first insulating layer, the gate electrode, the second insulating layer, the source electrode and the drain electrode are positioned on one side of the substrate, and the first insulating layer and the second insulating layer are positioned in the display area and the metal wiring area; the metal routing is positioned in the metal routing area; the first flat layer is positioned in the display area and positioned on one side of the source electrode and the drain electrode, which is far away from the substrate; the second flat layer is positioned in the metal wiring area and on one side of the metal wiring, which is far away from the substrate, and the thickness of at least part of the second flat layer is smaller than that of the first flat layer; and the organic light-emitting diode is positioned on one side of the first flat layer, which is far away from the substrate. According to the technical scheme, the contraction/expansion degree of the second flat layer when being heated/impacted can be reduced, the film layers positioned on the upper side and the lower side of the second flat layer are prevented from being peeled or cracked, and abnormal driving and packaging failure are avoided.
Description
Technical Field
The disclosure relates to the technical field of display, and in particular to a display substrate, a manufacturing method thereof, a display panel and a display device.
Background
Organic Light-Emitting diodes (OLEDs) are a display illumination technology that has been gradually developed in recent years, and particularly in the display industry, OLED display is considered to have a wide application prospect because of its advantages of high response, high contrast, flexibility, and the like.
The OLED display substrate comprises a display area and a non-display area, wherein the non-display area comprises a metal wiring area. In the OLED display substrate in the prior art, a metal wiring area is easy to have film layer stripping or cracks, so that OLED driving is abnormal or packaging fails.
Disclosure of Invention
The embodiment of the disclosure provides a display substrate, a preparation method thereof, a display panel and a display device, so as to solve or alleviate one or more technical problems in the prior art.
As a first aspect of the embodiments of the present disclosure, embodiments of the present disclosure provide a display substrate including a display area and a metal routing area located outside the display area, the display substrate including:
a substrate;
the active layer, the gate electrode, the source electrode and the drain electrode are positioned in the display area, and the first insulating layer and the second insulating layer are positioned in the display area and the metal wiring area;
the metal routing is positioned in the metal routing area;
the first flat layer is positioned in the display area and positioned on one side of the source electrode and the drain electrode, which is far away from the substrate;
the second flat layer is positioned in the metal wiring area and on one side of the metal wiring, which is far away from the substrate, and the thickness of at least part of the second flat layer is smaller than that of the first flat layer;
and the plurality of organic light emitting diodes are positioned in the display area and on one side of the first flat layer, which is far away from the substrate, and the organic light emitting diodes are connected with the source electrode or the drain electrode.
In some possible implementations, the second planar layer has a thickness in a range of 0.5 μm to 4 μm.
In some possible implementations, the second flat layer includes a first portion and a second portion, an orthogonal projection of the first portion on the substrate overlaps an orthogonal projection of the metal trace on the substrate, an orthogonal projection of the second portion on the substrate does not overlap an orthogonal projection of the metal trace on the substrate, and a distance between a surface of the first portion on a side away from the substrate and the substrate is greater than a distance between a surface of the second portion on a side away from the substrate and the substrate.
In some possible implementations, the display substrate further includes:
the metal connecting layer is positioned in the display area and positioned on one side, away from the substrate, of the first flat layer;
and the third flat layer is positioned in the display area and positioned on one side of the metal connecting layer, which is far away from the substrate.
In some possible implementations, the display substrate further includes a fourth flat layer, the fourth flat layer is located in the metal routing area and on a side of the second flat layer facing away from the substrate, and a thickness of at least a portion of the fourth flat layer is smaller than a thickness of the third flat layer.
In some possible implementations, the second and first planar layers are formed by a single patterning process.
In some possible implementations, the second flat layer and the first flat layer are made of the same material, and the second flat layer and the first flat layer are made of negative photoresist or negative photoresist.
In some possible implementations, the metal trace is located at the same layer as the source electrode or the drain electrode.
In some possible implementation manners, the display area is provided with a plurality of signal lines, the display substrate further includes a bonding area, and the metal routing lines are used for connecting the signal lines with the bonding pads of the bonding area.
As a second aspect of the embodiments of the present disclosure, an embodiment of the present disclosure provides a method for manufacturing a display substrate, the display substrate including a display area and a metal routing area located outside the display area, the method including:
forming an active layer, a first insulating layer, a gate electrode, a second insulating layer, a source electrode, a drain electrode and metal wiring on one side of a substrate, wherein the active layer, the gate electrode, the source electrode and the drain electrode are positioned in a display area, the first insulating layer and the second insulating layer are positioned in the display area and a metal wiring area, and the metal wiring is positioned in the metal wiring area;
forming a first flat layer positioned in the display area on one side of the source electrode and the drain electrode, which is far away from the substrate, and forming a second flat layer positioned in the metal wiring area on one side of the metal wiring, which is far away from the substrate, wherein the thickness of the second flat layer is smaller than that of the first flat layer;
and forming a plurality of organic light emitting diodes positioned in the display area on one side of the first flat layer, which is far away from the substrate, wherein the organic light emitting diodes are connected with the source electrode or the drain electrode.
In some possible implementations, forming a first flat layer in the display area on a side of the source electrode and the drain electrode away from the substrate, and forming a second flat layer in the metal routing area on a side of the metal routing away from the substrate includes:
forming a flat film on the side of the source electrode, the drain electrode and the metal wire, which is far away from the substrate, by adopting a coating process;
and exposing and developing the flat film by adopting a half-tone mask, forming a first through hole in the display area to form a first flat layer positioned in the display area, removing part of the flat film positioned in the metal wiring area along the direction vertical to the substrate to form a second flat layer positioned in the metal wiring area, wherein the thickness of the second flat layer is smaller than that of the first flat layer.
As a third aspect of the embodiments of the present disclosure, an embodiment of the present disclosure provides a display panel, including the display substrate in any embodiment of the present disclosure, and further including a cover glass, where the cover glass is attached to the display substrate relatively.
As a fourth aspect of the embodiments of the present disclosure, an embodiment of the present disclosure provides a display device including the display substrate in any embodiment of the present disclosure, or including the display panel in any embodiment of the present disclosure.
According to the display substrate provided by the embodiment of the disclosure, the first flat layer is arranged in the display area, and the organic light emitting diode is positioned on one side of the first flat layer, which is far away from the substrate, so that the planarization requirement of forming OLED pixels in the display area by adopting ink-jet printing can be met, and the lighting uniformity of the OLED pixels can be ensured; set up the flat layer of second on the one side that metal wiring deviates from the basement, the flat layer of second can play the guard action to metal wiring, can prevent that metal wiring from being by the fish tail to, the flat layer of second can also prevent that metal wiring from the drive signal between crosstalking. In addition, the thickness of at least part of the second flat layer is smaller than that of the first flat layer, so that the thickness of at least part of the second flat layer is reduced, the contraction/expansion degree of the second flat layer during heating/cold impact is reduced, the film layers of the metal wiring area, which are positioned at the upper side and the lower side of the second flat layer, are prevented from being peeled or cracked, and abnormal driving and packaging failure are avoided.
The foregoing summary is provided for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present disclosure will be readily apparent by reference to the drawings and following detailed description.
Drawings
In the drawings, like reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily to scale. It is appreciated that these drawings depict only some embodiments in accordance with the disclosure and are not to be considered limiting of its scope.
FIG. 1 is a schematic plane structure diagram of an OLED display substrate;
FIG. 2 is a schematic cross-sectional view illustrating a display substrate according to an embodiment of the present disclosure;
FIG. 3 is a schematic cross-sectional view taken along line A-A of FIG. 1 illustrating a substrate according to one embodiment of the present disclosure;
FIG. 4 is a schematic cross-sectional view of a display substrate according to another embodiment of the present disclosure;
fig. 5 is a schematic view showing a substrate after forming a source electrode and a drain electrode according to an embodiment of the present disclosure;
FIG. 6a is a schematic view of a display substrate after a planar film is formed thereon according to one embodiment of the present disclosure;
fig. 6b is a schematic diagram illustrating a first planar layer and a second planar layer formed on a substrate according to an embodiment of the disclosure.
Description of reference numerals:
10. a display area; 20. a metal routing area; 21. metal routing; 30. a binding region; 31. a substrate; 321. an active layer; 322. a gate electrode; 323a, a source electrode; 323b drain electrode; 36. a pixel defining layer; 51. a first insulating layer; 52. a second insulating layer; 53. a buffer layer; 54', a flat membrane; 541. a first planar layer; 542. a second planar layer; 542a, a first portion; 542b, a second portion; 55', a third insulating film; 55. a third insulating layer; 561. a third flat layer; 562. a fourth planar layer; 57. a metal connection layer; 70. an organic light emitting diode; 71. a first electrode; 72. an organic light emitting layer; 73. a second electrode; 81. a first via.
Detailed Description
In the following, only certain exemplary embodiments are briefly described. As those skilled in the art can appreciate, the described embodiments can be modified in various different ways, without departing from the spirit or scope of the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
Fig. 1 is a schematic plan view of an OLED display substrate. As shown in fig. 1, the OLED display substrate includes a display area 10 and a non-display area, the display area is provided with a plurality of organic light emitting diodes 70, the non-display area includes a metal routing area 20 and a bonding area 30, the metal routing area 20 is provided with a plurality of metal wires 21, and the metal wires are used for connecting signal lines of the display area 10 with bonding pads (Pad) of the bonding area 30. The display area 10 is provided with a plurality of OLED pixels. In the top-emitting OLED display substrate, in order to ensure uniformity of lighting of OLED pixels, a planarization layer is required to planarize a display area. In the related art, the display region 10 may be planarized using a negative photoresist resin material having a large thickness. In a routing area (i.e., a metal routing area) of a Bonding Pad (Bonding Pad) of the OLED display substrate, in order to prevent the metal routing from being scratched, and in order to prevent crosstalk of driving signals between the metal routing, a planarization resin material layer is disposed in the metal routing area 20. Because the thickness of the resin material layer is relatively large (greater than or equal to 1 μm), when the display substrate formed with the resin material layer is baked at a high temperature (for example, baked at 80 ℃ for 139 hours), the resin material layer is easily shrunk/expanded along the plane of the film layer when heated/cooled, and after the resin material layer is shrunk/expanded to a certain degree, the film layers on the upper side and the lower side of the resin material layer in the metal wiring area are peeled and cracked due to different shrinkage/expansion degrees, so that the OLED pixel driving is abnormal or the packaging failure is generated.
In order to solve the above technical problem, embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device.
Fig. 2 is a schematic cross-sectional structure diagram of a display substrate according to an embodiment of the disclosure. A schematic plan view of a display substrate according to an embodiment of the present disclosure may be shown in fig. 1, and in an implementation manner, as shown in fig. 1 and fig. 2, the display substrate may include a display area 10 and a metal routing area 20, where the metal routing area 20 is located outside the display area 10. The display substrate may include a base 31, and may further include an active layer 321, a first insulating layer 51 (which may also be referred to as a gate insulating layer), a gate electrode 322, a second insulating layer 52 (which may also be referred to as an interlayer insulating layer), a source electrode 323a, and a drain electrode 323b on one side of the base 31. Wherein the active layer 321, the gate electrode 322, the source electrode 323a and the drain electrode 323b are located in the display region 10, and the first insulating layer 51 and the second insulating layer 52 may be located in the display region 10 and the metal wiring region 20.
The display substrate may further include metal traces 21, and the metal traces 21 are located in the metal trace region 20. It is understood that the display area 10 is provided with a plurality of signal lines, such as gate lines, data lines, etc., and the display substrate may further include a bonding area 30, and the metal traces 21 are used to connect the signal lines of the display area 10 with pads (Pad) of the bonding area 30.
As shown in fig. 2, the display substrate may further include a first planarization layer 541 and a second planarization layer 542, the first planarization layer 541 is located in the display area 10, and the first planarization layer 541 is located on a side of the source electrode 323a and the drain electrode 232b facing away from the substrate 31. The second flat layer 542 is located in the metal routing area 20, the second flat layer 542 is located on a side of the metal routing 21 away from the substrate 31, and a thickness of at least a portion of the second flat layer 542 is smaller than a thickness of the first flat layer 541. It is understood that the thickness is a dimension of the film layer in a direction perpendicular to the substrate, for example, the thickness of the second planarization layer is a dimension of the second planarization layer in a direction perpendicular to the substrate, and the thickness of the first planarization layer is a dimension of the first planarization layer in a direction perpendicular to the substrate. The display substrate may further include a plurality of organic light emitting diodes 70, the plurality of organic light emitting diodes 70 are located in the display region 10 and on a side of the first flat layer 541 facing away from the base 31, and the organic light emitting diodes 70 are connected to the source electrode 323a or the drain electrode 323 b.
According to the display substrate of the embodiment of the disclosure, the first flat layer 541 is disposed in the display area 10, and the organic light emitting diode 70 is located on a side of the first flat layer 541 away from the substrate 31, so that a planarization requirement that the display area 10 forms OLED pixels by inkjet printing can be met, and lighting uniformity of the OLED pixels can be ensured; set up second flat layer 542 at the one side that metal is walked line 21 and is kept away from base 31, second flat layer 542 can play the guard action to metal is walked line 21, can prevent that metal is walked line 21 by the fish tail to, second flat layer 542 can also prevent the drive signal crosstalk between the metal is walked line 21. Compared with the related art in which the thickness of the second flat layer is the same as that of the first flat layer, in the display substrate of the embodiment of the present disclosure, the thickness of at least a portion of the second flat layer 542 is smaller than that of the first flat layer 541, so that the thickness of at least a portion of the second flat layer 542 is reduced, for example, the thickness of at least a portion of the second flat layer 542 is smaller than 1 μm, which reduces the shrinkage/expansion degree of the second flat layer 542 when subjected to thermal/cold impact, is beneficial to avoiding peeling or cracking of the film layers of the metal routing area 20 located on the upper and lower sides of the second flat layer 542, and avoids abnormal driving and package failure.
In one embodiment, the thickness d1 of the first planar layer 541 ranges from 1 μm to 5 μm (inclusive), and the thickness d2 of the second planar layer 542 ranges from 0.5 μm to 4 μm (inclusive). By setting the thickness of the second flat layer 524 to be 0.5 μm to 4 μm (inclusive), the shrinkage/expansion degree of the second flat layer 542 during thermal/cold impact can be further reduced, and peeling or cracking of the film layers of the metal routing area 20 on the upper and lower sides of the second flat layer 542 can be avoided, and abnormal driving and failure of the package can be avoided. Illustratively, the thickness d1 of the first planarization layer 541 may be any value from 1 μm to 5 μm, for example, the thickness d1 of the first planarization layer 541 may be one of 1 μm, 2 μm, 3 μm, 4 μm, and 5 μm. Illustratively, the thickness d2 of the second planarization layer 542 may be any value from 0.5 μm to 4 μm, for example, the thickness d2 of the second planarization layer 542 may be one of 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm.
FIG. 3 is a schematic cross-sectional view taken along line A-A of FIG. 1 illustrating a substrate according to an embodiment of the present disclosure. In one embodiment, as shown in fig. 3, the second flat layer 542 may include a first portion 542a and a second portion 542b, an orthographic projection of the first portion 542a on the substrate 31 overlaps an orthographic projection of the metal trace 21 on the substrate 31, and an orthographic projection of the second portion 542b on the substrate 31 does not overlap an orthographic projection of the metal trace 21 on the substrate 31. The distance d3 between the surface of the first portion 542a on the side away from the substrate 31 and the substrate 31 is greater than the distance d4 between the surface of the second portion 542b on the side away from the substrate 31 and the substrate 31, i.e., d3 is greater than d 4. In such a second flat layer, the first portion 542a corresponding to the metal trace 21 can better protect the metal trace 21, and can better prevent the metal trace 21 from being scratched.
In one embodiment, the second flat layer 542 and the first flat layer 541 are formed simultaneously, that is, the second flat layer 542 and the first flat layer 541 are formed by one patterning process. Therefore, the number of masks can be reduced, and the manufacturing process of the display substrate is simplified.
In one embodiment, the material of each of the second and first flat layers 542 and 541 may be an organic material, such as a resin material.
In one embodiment, the second flat layer 542 and the first flat layer 541 are made of the same material, and the second flat layer 542 and the first flat layer 541 can be made of a positive photoresist or a negative photoresist.
In one embodiment, as shown in fig. 2, the display substrate may further include a third insulating layer 55 (which may also be referred to as a passivation layer PVX), the third insulating layer 55 is located in the display region 10 and/or the metal routing region 20, and the third insulating layer 55 is located between the first flat layer 541 and the source and drain electrodes 323a and 323 b.
In one embodiment, the metal trace 21 may be located at the same layer as the source electrode 323a or the drain electrode 323b, that is, the metal trace 21 may be formed by a patterning process with the source electrode 323a or the drain electrode 323 b.
Exemplarily, in fig. 2, the active layer 321 is located on a side of the substrate 31, the first insulating layer 51 is located on a side of the active layer 321 facing away from the substrate 31, the gate electrode 322 is located on a side of the first insulating layer 51 facing away from the substrate 31, the second insulating layer 52 is located on a side of the gate electrode 322 facing away from the substrate 31, and the source electrode 323a and the drain electrode 323b are located on a side of the second insulating layer 52 facing away from the substrate 31. A thin film transistor is illustrated in fig. 2, and the thin film transistor may include an active layer 321, a gate electrode 322, a source electrode 323a, and a drain electrode 323b, and the thin film transistor illustrated in fig. 2 is a top gate type thin film transistor, and in other embodiments, the thin film transistor may be a bottom gate type thin film transistor. It is to be understood that the display substrate of the present embodiment has no selection requirement for the type of the thin film transistor, as long as the performance of the thin film transistor can be achieved.
As shown in fig. 2, the organic light emitting diode 70 includes a first electrode 71, an organic light emitting layer 72, and a second electrode 73. The first electrode 71 may be an anode, and the second electrode 73 may be a cathode. The first electrode 71 is located in the display area, and the first electrode 71 is located on a side of the first flat layer 541 facing away from the substrate 31. The first electrode 71 is connected to the source electrode 323a or the drain electrode 323b of the corresponding thin film transistor. The display substrate further includes a pixel defining layer 36, the pixel defining layer 36 is disposed in the display region 10, and the pixel defining layer 36 is provided with a plurality of openings, each opening exposing a corresponding first electrode 71. The organic light emitting layer 72 is located in the opening and on a side of the first electrode 71 facing away from the substrate 31, and the second electrode 73 is located on a side of the organic light emitting layer 72 facing away from the substrate 31.
In one embodiment, as shown in fig. 2, the display substrate may further include a buffer layer 53, and the buffer layer 53 may be positioned between the substrate 31 and the active layer 321.
It is understood that the display substrate may further include an encapsulation passivation layer (not shown), the encapsulation passivation layer may be located on a side of the organic light emitting diode 70 facing away from the substrate 31, and the encapsulation passivation layer may be located in the display region 10 and the metal routing region 20.
Fig. 4 is a schematic cross-sectional view of a display substrate according to another embodiment of the present disclosure. As shown in fig. 4, the display substrate may further include a metal connection layer 57 and a third flat layer 561. The metal connection layer 57 is located in the display region, and the metal connection layer 57 may be located on a side of the first flat layer 541 facing away from the substrate 31. A third flat layer 561 may be located at the display area and at a side of the metal connection layer 57 facing away from the substrate 31. The first electrode 71 may be connected to the source electrode 323a or the drain electrode 323b of the corresponding thin film transistor through the metal connection layer 57.
In one embodiment, as shown in fig. 4, the display substrate may further include a fourth planarization layer 562, the fourth planarization layer 562 is located in the metal routing area and on a side of the second planarization layer 542 facing away from the base 31, and a thickness of at least a portion of the fourth planarization layer 562 is smaller than a thickness of the third planarization layer 561.
The specific thicknesses of the third and fourth planarization layers 561, 562 are not limited herein and may be set as desired.
For example, the fourth flat layer 562 may include a third portion and a fourth portion, an orthogonal projection of the third portion on the substrate 31 overlaps an orthogonal projection of the metal trace 21 on the substrate 31, an orthogonal projection of the fourth portion on the substrate 31 does not overlap an orthogonal projection of the metal trace 21 on the substrate 31, and a distance between a surface of the third portion on a side far from the substrate 31 and the substrate 31 may be greater than a distance between a surface of the fourth portion on a side far from the substrate 31 and the substrate 31.
It is understood that other film layers may be disposed between the second planarization layer 542 and the fourth planarization layer 562 as desired.
Illustratively, the third and fourth planarization layers 561 and 562 may be formed by one patterning process. The third and fourth flat layers 561 and 562 may be made of the same material. The third and fourth flat layers 561 and 562 can be made of negative photoresist or positive photoresist.
In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, and the buffer layer may employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer, or a composite layer. A Buffer (Buffer) layer for improving the water and oxygen resistance of the substrate, and the first insulating layer may be referred to as a Gate Insulating (GI) layer and the second insulating layer may be referred to as an interlayer Insulating (ILD) layer. The gate electrode, the source electrode, the drain electrode, and the metal wire may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium (AlNd) or molybdenum niobium (MoNb), and may have a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti, and the like. The pixel defining layer may be made of polyimide, acryl, polyethylene terephthalate, or the like. The active layer may be made of various materials such as amorphous indium gallium zinc Oxide (a-IGZO), zinc oxynitride (ZnON), Indium Zinc Tin Oxide (IZTO), amorphous silicon (a-Si), polysilicon (p-Si), hexathiophene, polythiophene, etc., that is, the present disclosure is applicable to transistors manufactured based on Oxide technology, silicon technology, and organic technology.
The thickness of each of the remaining layers in the display substrate may be set as needed, and is not particularly limited.
The display substrate of the embodiment of the present disclosure may be an OLED display substrate, and the substrate may be a hard material such as glass, or a flexible material such as Polyimide (PI).
The embodiment of the present disclosure further provides a method for manufacturing a display substrate, where the display substrate may include a display area and a metal routing area located outside the display area, and the method for manufacturing the display substrate may include:
forming an active layer, a first insulating layer, a gate electrode, a second insulating layer, a source electrode, a drain electrode and metal wiring on one side of a substrate, wherein the active layer, the gate electrode, the source electrode and the drain electrode are positioned in a display area, the first insulating layer and the second insulating layer are positioned in the display area and a metal wiring area, and the metal wiring is positioned in the metal wiring area;
forming a first flat layer positioned in the display area on one side of the source electrode and the drain electrode, which is far away from the substrate, and forming a second flat layer positioned in the metal wiring area on one side of the metal wiring, which is far away from the substrate, wherein the thickness of the second flat layer is smaller than that of the first flat layer;
and forming a plurality of organic light emitting diodes positioned in the display area on one side of the first flat layer, which is far away from the substrate, wherein the organic light emitting diodes are connected with the source electrode or the drain electrode.
In one embodiment, forming a first flat layer on the display area at the side of the source electrode and the drain electrode away from the substrate, and forming a second flat layer on the metal routing area at the side of the metal routing away from the substrate includes:
forming a flat film on the side of the source electrode, the drain electrode and the metal wire, which is far away from the substrate, by adopting a coating process;
and exposing and developing the flat film by adopting a half-tone mask, forming a first through hole in the display area to form a first flat layer positioned in the display area, removing part of the flat film positioned in the metal wiring area along the direction vertical to the substrate to form a second flat layer positioned in the metal wiring area, wherein the thickness of the second flat layer is smaller than that of the first flat layer.
The technical solution of the embodiment of the present disclosure is further illustrated by the preparation process of the display substrate in the embodiment shown in fig. 2. It is to be understood that "patterning" as used herein includes processes of coating photoresist, mask exposure, development, etching, stripping photoresist, etc. when the material to be patterned is an inorganic material or a metal, and processes of mask exposure, development, etc. when the material to be patterned is an organic material, and evaporation, deposition, coating, etc. as used herein are well-known preparation processes in the related art.
Forming an active layer, a first insulating layer, a gate electrode, a second insulating layer, a source electrode, a drain electrode, and metal traces on one side of a substrate, which may include: as shown in fig. 5, fig. 5 is a schematic view showing a substrate after forming a source electrode and a drain electrode according to an embodiment of the present disclosure, and a buffer film is deposited on one side of a substrate 31 to form a buffer layer 53; depositing an active film on the side of the buffer layer 53 away from the substrate 31, and patterning the active film to form an active layer 321 in the display region 10; depositing a first insulating film on the side of the active layer 321 facing away from the substrate 31; depositing a gate metal film on a side of the first insulating film away from the substrate 31, and performing patterning on the gate metal film to form a gate electrode 322 and a gate line (not shown) in the display region 10; depositing a second insulating film on the side of the gate electrode 322, which is away from the substrate 31, patterning the second insulating film and the first insulating film to form a second via hole and a third via hole, which penetrate through the second insulating film and the first insulating film, wherein the active layer 321 is exposed by the second via hole and the third via hole, so as to form a first insulating layer 51 and a second insulating layer 52, and the first insulating layer 51 and the second insulating layer 52 are both located in the display area 10 and the metal wiring area 20; and depositing a source-drain metal film on the side of the second insulating layer 52 away from the substrate 31, and performing patterning on the source-drain metal film to form a metal trace 21 located in the metal trace area 20 and a source electrode 323a and a drain electrode 323b located in the display area 10. The source electrode 323a and the drain electrode 323b are connected to the active layer 321 through second and third vias, respectively. Illustratively, a data line (not shown in the drawings) located at the display region is also formed at the same time as the source and drain electrodes.
And forming a first flat layer positioned in the display area on one side of the source electrode and the drain electrode, which is deviated from the substrate, and forming a second flat layer positioned in the metal wiring area on one side of the metal wiring, which is deviated from the substrate, wherein the thickness of the second flat layer is smaller than that of the first flat layer. This step may include: forming a third insulating film 55 ' on the source electrode 323a, the drain electrode 323b, and the side of the metal trace 21 away from the substrate 31, and forming a flat film 54 ' on the side of the third insulating film 55 ' away from the substrate 31 by a coating process, as shown in fig. 6a, where fig. 6a is a schematic diagram of a display substrate according to an embodiment of the disclosure after forming the flat film; the flat film 54' is exposed and developed by using a half-tone Mask (halftone Mask), a first via hole 81 is formed in the display area 10 to form a first flat layer 541, a portion of the flat film in the metal routing area 20 is removed in a direction perpendicular to the substrate 31, and the remaining flat film in the metal routing area 20 forms a second flat layer 542, as shown in fig. 6b, where fig. 6b is a schematic diagram of the display substrate according to an embodiment of the present disclosure after forming the first flat layer and the second flat layer. Illustratively, the thickness of the second planarization layer 542 is less than the thickness of the first planarization layer 541, the thickness of the first planarization layer 541 ranges from 1 μm to 5 μm (inclusive), and the thickness of the second planarization layer 542 ranges from 0.5 μm to 3 μm (inclusive). Wherein, the orthographic projection of the first via 81 on the substrate 31 is located within the range of the orthographic projection of the drain electrode 323b on the substrate 31. The first via hole 81 is dry etched to remove the remaining flat film of the first via hole 81 and the third insulating film, so that the first via hole 81 exposes the drain electrode 323b, as shown in fig. 6 b.
A first electrode 71 is formed on one side of the first flat layer 541, which is away from the substrate 31, the first electrode 71 is located in the display area, and the first electrode 71 is connected with the drain electrode 323b of the thin film transistor through the first via hole 81; forming a pixel defining layer 36 on a side of the first electrode 71 away from the substrate 31, where the pixel defining layer 36 is located in the display area, and the pixel defining layer 36 is provided with a plurality of openings, and each opening exposes a corresponding first electrode 71, as shown in fig. 2; forming the organic light emitting layer 72 by evaporation, sputtering, electron beam deposition or the like; a second electrode 73 is formed on a side of the organic light emitting layer 72 away from the substrate 31, and the material of the second electrode 73 may be a transparent conductive material such as indium tin oxide or indium zinc oxide. Illustratively, the organic light emitting layer 72 may be formed by inkjet printing.
An encapsulation passivation layer (not shown) is formed on the side of the second electrode 73 facing away from the substrate 31.
The embodiment of the present disclosure further provides a display panel, which includes the display substrate and the cover glass in any embodiment of the present disclosure, wherein one side of the cover glass facing the display substrate is coated with an encapsulation adhesive material, and the cover glass is attached to the display substrate through an encapsulation and attachment process.
Based on the inventive concept of the foregoing embodiments, embodiments of the present disclosure also provide a display device including a display substrate employing the foregoing embodiments. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
In the description of the present specification, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present disclosure and to simplify the description, but are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the present disclosure.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present disclosure, "a plurality" means two or more unless specifically limited otherwise.
In the present disclosure, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integral; the connection can be mechanical connection, electrical connection or communication; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present disclosure can be understood by those of ordinary skill in the art as appropriate.
In the present disclosure, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise the first and second features being in direct contact, or may comprise the first and second features being in contact, not directly, but via another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly above and obliquely above the second feature, or simply meaning that the first feature is at a lesser level than the second feature.
The above disclosure provides many different embodiments or examples for implementing different features of the disclosure. The components and arrangements of specific examples are described above to simplify the present disclosure. Of course, they are merely examples and are not intended to limit the present disclosure. Moreover, the present disclosure may repeat reference numerals and/or reference letters in the various examples, which have been repeated for purposes of simplicity and clarity and do not in themselves dictate a relationship between the various embodiments and/or arrangements discussed.
While the present disclosure has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (13)
1. A display substrate, comprising a display area and a metal routing area outside the display area, the display substrate comprising:
a substrate;
the active layer, the gate electrode, the source electrode and the drain electrode are positioned in a display area, and the first insulating layer and the second insulating layer are positioned in the display area and the metal wiring area;
the metal routing is positioned in the metal routing area;
the first flat layer is positioned in the display area and positioned on one side, away from the substrate, of the source electrode and the drain electrode;
the second flat layer is positioned in the metal routing area and on one side, away from the substrate, of the metal routing, the thickness of at least part of the second flat layer is smaller than that of the first flat layer, and the thickness is the size in the direction perpendicular to the substrate;
and the plurality of organic light emitting diodes are positioned in the display area and on one side of the first flat layer, which is far away from the substrate, and the organic light emitting diodes are connected with the source electrode or the drain electrode.
2. The display substrate of claim 1, wherein the second planarization layer has a thickness in a range from 0.5 μ ι η to 4 μ ι η.
3. The display substrate according to claim 1, wherein the second flat layer comprises a first portion and a second portion, an orthogonal projection of the first portion on the substrate overlaps an orthogonal projection of the metal trace on the substrate, an orthogonal projection of the second portion on the substrate does not overlap an orthogonal projection of the metal trace on the substrate, and a distance between a surface of the first portion on a side away from the substrate and the substrate is greater than a distance between a surface of the second portion on a side away from the substrate and the substrate.
4. The display substrate of claim 1, further comprising:
the metal connecting layer is positioned in the display area and positioned on one side, away from the substrate, of the first flat layer;
and the third flat layer is positioned in the display area and positioned on one side of the metal connecting layer, which is far away from the substrate.
5. The display substrate according to claim 4, further comprising a fourth planarization layer on the metal routing area and on a side of the second planarization layer facing away from the substrate, wherein a thickness of at least a portion of the fourth planarization layer is smaller than a thickness of the third planarization layer.
6. The display substrate according to claim 1, wherein the second flat layer and the first flat layer are formed by a single patterning process.
7. The display substrate of claim 1, wherein the second planarization layer and the first planarization layer are made of the same material, and the second planarization layer and the first planarization layer are made of a negative photoresist or a positive photoresist.
8. The display substrate according to any one of claims 1 to 7, wherein the metal trace is located at the same layer as the source electrode or the drain electrode.
9. The display substrate according to any one of claims 1 to 7, wherein the display area is provided with a plurality of signal lines, the display substrate further comprises a bonding area, and the metal trace is used for connecting the signal lines with pads of the bonding area.
10. A preparation method of a display substrate is characterized in that the display substrate comprises a display area and a metal wiring area outside the display area, and the method comprises the following steps:
forming an active layer, a first insulating layer, a gate electrode, a second insulating layer, a source electrode, a drain electrode and a metal wire on one side of a substrate, wherein the active layer, the gate electrode, the source electrode and the drain electrode are positioned in a display area, the first insulating layer and the second insulating layer are positioned in the display area and the metal wire area, and the metal wire is positioned in the metal wire area;
forming a first flat layer positioned in a display area on one side of the source electrode and the drain electrode, which is far away from the substrate, and forming a second flat layer positioned in a metal wiring area on one side of the metal wiring, which is far away from the substrate, wherein the thickness of the second flat layer is smaller than that of the first flat layer;
and forming a plurality of organic light emitting diodes positioned in the display area on one side of the first flat layer, which is far away from the substrate, wherein the organic light emitting diodes are connected with the source electrode or the drain electrode.
11. The method of claim 10, wherein forming a first planar layer in a display area on a side of the source electrode and the drain electrode facing away from the substrate, and forming a second planar layer in a metal routing area on a side of the metal routing facing away from the substrate comprises:
forming a flat film on the source electrode, the drain electrode and one side of the metal wire, which is far away from the substrate, by adopting a coating process;
and exposing and developing the flat film by adopting a half-tone mask, forming a first through hole in the display area to form a first flat layer positioned in the display area, and removing part of the flat film positioned in the metal wiring area along the direction vertical to the substrate to form a second flat layer positioned in the metal wiring area, wherein the thickness of the second flat layer is smaller than that of the first flat layer.
12. A display panel comprising the display substrate according to any one of claims 1 to 9, and further comprising a cover glass attached to the display substrate in an opposed manner.
13. A display device comprising the display substrate according to any one of claims 1 to 9 or comprising the display panel according to claim 12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110678498.7A CN113421903B (en) | 2021-06-18 | 2021-06-18 | Display substrate, preparation method thereof, display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110678498.7A CN113421903B (en) | 2021-06-18 | 2021-06-18 | Display substrate, preparation method thereof, display panel and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113421903A true CN113421903A (en) | 2021-09-21 |
| CN113421903B CN113421903B (en) | 2023-11-10 |
Family
ID=77789093
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110678498.7A Active CN113421903B (en) | 2021-06-18 | 2021-06-18 | Display substrate, preparation method thereof, display panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113421903B (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100155735A1 (en) * | 2008-12-23 | 2010-06-24 | Sung-Jin Park | Electrophoretic display device and method of fabricating the same |
| US20150060786A1 (en) * | 2013-08-28 | 2015-03-05 | Samsung Display Co., Ltd. | Organic light-emitting display apparatus and method of manufacturing the same |
| US20170235396A1 (en) * | 2016-02-16 | 2017-08-17 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Thin film transistor array substrate, manufacturing method thereof and touch display panel |
| US20170278913A1 (en) * | 2015-03-27 | 2017-09-28 | Boe Technology Group Co., Ltd. | Array substrate and manufacturing method thereof and organic light-emitting display apparatus |
| US20190081126A1 (en) * | 2017-09-08 | 2019-03-14 | Japan Display Inc. | Display device |
| CN109560088A (en) * | 2018-12-19 | 2019-04-02 | 武汉华星光电半导体显示技术有限公司 | Flexible display substrates and preparation method thereof |
| CN110265576A (en) * | 2019-06-27 | 2019-09-20 | 昆山工研院新型平板显示技术中心有限公司 | A kind of packaging method of display panel, display panel and display device |
| US20190348489A1 (en) * | 2018-05-14 | 2019-11-14 | Samsung Display Co., Ltd. | Organic light emitting diode display device |
| US20200152707A1 (en) * | 2018-11-09 | 2020-05-14 | Lg Display Co., Ltd. | Display Device |
| KR20200063122A (en) * | 2020-05-26 | 2020-06-04 | 삼성디스플레이 주식회사 | Organic light emitting display apparatus and the manufacturing method thereof |
-
2021
- 2021-06-18 CN CN202110678498.7A patent/CN113421903B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100155735A1 (en) * | 2008-12-23 | 2010-06-24 | Sung-Jin Park | Electrophoretic display device and method of fabricating the same |
| US20150060786A1 (en) * | 2013-08-28 | 2015-03-05 | Samsung Display Co., Ltd. | Organic light-emitting display apparatus and method of manufacturing the same |
| US20170278913A1 (en) * | 2015-03-27 | 2017-09-28 | Boe Technology Group Co., Ltd. | Array substrate and manufacturing method thereof and organic light-emitting display apparatus |
| US20170235396A1 (en) * | 2016-02-16 | 2017-08-17 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Thin film transistor array substrate, manufacturing method thereof and touch display panel |
| US20190081126A1 (en) * | 2017-09-08 | 2019-03-14 | Japan Display Inc. | Display device |
| US20190348489A1 (en) * | 2018-05-14 | 2019-11-14 | Samsung Display Co., Ltd. | Organic light emitting diode display device |
| US20200152707A1 (en) * | 2018-11-09 | 2020-05-14 | Lg Display Co., Ltd. | Display Device |
| CN109560088A (en) * | 2018-12-19 | 2019-04-02 | 武汉华星光电半导体显示技术有限公司 | Flexible display substrates and preparation method thereof |
| CN110265576A (en) * | 2019-06-27 | 2019-09-20 | 昆山工研院新型平板显示技术中心有限公司 | A kind of packaging method of display panel, display panel and display device |
| KR20200063122A (en) * | 2020-05-26 | 2020-06-04 | 삼성디스플레이 주식회사 | Organic light emitting display apparatus and the manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113421903B (en) | 2023-11-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102458907B1 (en) | Organic light emitting display and method of fabricating the same | |
| CN110120463B (en) | Display substrate, preparation method thereof and display device | |
| CN114551766A (en) | Display device | |
| US20170154934A1 (en) | Display substrate, method of manufacturing display substrate, and display device including display substrate | |
| CN112133729B (en) | Display substrate, preparation method thereof and display device | |
| US11723257B2 (en) | Organic light emitting diode display substrate, manufacturing method therefor, and organic light emitting diode display device | |
| US10529790B2 (en) | Organic light-emitting diode display and method of manufacturing the same with no cladding process | |
| CN113658990B (en) | Display panel, preparation method thereof and display device | |
| CN109065590B (en) | Organic light-emitting display substrate, manufacturing method thereof and organic light-emitting display device | |
| US9911802B2 (en) | Display device and method for manufacturing the same | |
| US11177340B2 (en) | Display device and method for manufacturing the same | |
| KR20180019793A (en) | Backplane for display device and method of manufacturing the same | |
| US10371986B2 (en) | Display devices including mirror substrates and methods of manufacturing mirror substrates | |
| KR20190118221A (en) | Organic light emitting display device | |
| KR20200133890A (en) | Display device and method for manufacturing the same | |
| CN113870693A (en) | Display device and method of providing the same | |
| KR101056429B1 (en) | Display device and method of manufacturing the same | |
| US20220344448A1 (en) | Display Substrate and Preparation Method Thereof, and Display Apparatus | |
| US20230329056A1 (en) | Organic light emitting display device | |
| JP2023518622A (en) | DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY MOTHERBOARD AND DISPLAY DEVICE | |
| US20210134851A1 (en) | Display device and method for manufacturing the same | |
| US20220059630A1 (en) | Display device and method for manufacturing the same | |
| CN113421903B (en) | Display substrate, preparation method thereof, display panel and display device | |
| CN113410274A (en) | Display substrate, preparation method thereof and display device | |
| WO2021169568A1 (en) | Display mother board and preparation method therefor, display substrate and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |