CN113421892B - Display panel, manufacturing method thereof and display device - Google Patents
Display panel, manufacturing method thereof and display device Download PDFInfo
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- CN113421892B CN113421892B CN202110671282.8A CN202110671282A CN113421892B CN 113421892 B CN113421892 B CN 113421892B CN 202110671282 A CN202110671282 A CN 202110671282A CN 113421892 B CN113421892 B CN 113421892B
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 8
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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Abstract
The embodiment of the application discloses a display panel, a manufacturing method thereof and a display device, wherein the display panel comprises: the LED display device comprises an array substrate, a plurality of LEDs, a plurality of first bridging structures and a plurality of second bridging structures, wherein the first bridging structures comprise a first bridging region and a second bridging region, the second bridging region is not overlapped with the LEDs in the direction perpendicular to the plane of the array substrate, the second bridging structures are electrically connected with the array substrate, and the second bridging structures and electrodes of the LEDs are positioned on the same side of the first bridging structures in the direction perpendicular to the plane of the array substrate; and the electrode of the LED is electrically connected with the first bridging region of the first bridging structure, and the second bridging structure is electrically connected with the second bridging region of the first bridging structure, so that the electrode of the LED is electrically connected with the array substrate through the first bridging structure and the second bridging structure in sequence, and the stability of the display panel is improved.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to a display panel, a manufacturing method thereof, and a display device including the display panel.
Background
Along with the development of display technology, the display panel is increasingly widely applied, and has been gradually applied to various fields of people's work and life, thereby bringing great convenience to people's work and life. The Micro LED display panel uses self-luminous micron-level LEDs as luminous pixel units, and the self-luminous micron-level LEDs are assembled on a driving panel to form a display panel of a high-density LED array, so that the Micro LED display panel has greater advantages in the aspects of brightness, resolution, contrast, energy consumption, service life, response speed, thermal stability and the like compared with LCDs and OLEDs in the aspect of display. However, in the existing Micro LED display panel, a huge amount of transfer bonding process is used for transferring Micro LEDs, and the huge amount of transfer bonding process has a pressurizing and heating process, so that both the Micro LEDs and the backboard are damaged, and the reliability problem of the Micro LED display panel is caused.
Disclosure of Invention
In order to solve the technical problems, the embodiment of the application provides a display panel to improve the reliability of the display panel.
In order to solve the problems, the embodiment of the application provides the following technical scheme:
a display panel, comprising:
an array substrate;
the LED comprises a light-emitting layer and an electrode, wherein the electrode is positioned on one side of the light-emitting layer close to the array substrate;
The first bridging structures comprise first bridging areas and second bridging areas, and the second bridging areas are not overlapped with the LEDs in the direction perpendicular to the plane of the array substrate;
the second bridging structures are electrically connected with the array substrate, and the second bridging structures and the electrodes of the LEDs are positioned on the same side of the first bridging structures in the direction perpendicular to the plane of the array substrate;
the electrode of the LED is electrically connected with the first bridging region of the first bridging structure, and the second bridging structure is electrically connected with the second bridging region of the first bridging structure.
A manufacturing method of a display panel comprises the following steps:
providing a first substrate, and forming a plurality of LEDs on a first side of the first substrate, wherein the LEDs comprise a light-emitting layer and an electrode positioned on one side of the light-emitting layer away from the first substrate;
forming a plurality of first bridging structures on one side of the LEDs, which is away from the first substrate, wherein the first bridging structures comprise first bridging areas and second bridging areas, the second bridging areas are not overlapped with the LEDs in the direction perpendicular to the plane of the first substrate, and the LED electrodes are electrically connected with the first bridging areas of the first bridging structures;
Transferring the LEDs and the first bridging structures to an array substrate, removing the first substrate, wherein the electrodes of the LEDs are positioned on one side of the light-emitting layer, which is close to the array substrate, and the first bridging structures are positioned between the electrodes of the LEDs and the array substrate;
and forming a second bridging structure on one side of the first bridging structure, which is away from the array substrate, wherein the second bridging structure is electrically connected with a second bridging region of the first bridging structure, and the second bridging structure is electrically connected with the array substrate through a via hole.
A display device comprises the display panel.
Compared with the prior art, the technical scheme has the following advantages:
in the technical scheme provided by the embodiment of the application, the electrode of the LED is electrically connected with the first bridging region of the first bridging structure, the second bridging structure is electrically connected with the second bridging region of the first bridging structure, and the second bridging structure is electrically connected with the array substrate, so that the electrode of the LED is electrically connected with the array substrate through the first bridging structure and the second bridging structure in sequence without adopting a huge transfer bonding process, the phenomenon of internal stress accumulation of the display panel caused by the introduction of the huge transfer bonding process is avoided, the stability of the display panel is improved, and the yield of the display panel is further improved.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the application;
FIG. 2 is a schematic diagram of an LED structure of the display panel shown in FIG. 1;
FIG. 3 is a schematic diagram of a display panel according to another embodiment of the present application;
FIG. 4 is a schematic structural diagram of a display panel according to another embodiment of the present application;
fig. 5 is a schematic layout diagram of a first bridge region and a second bridge region of a first bridge structure in a display panel according to an embodiment of the application;
fig. 6 is a schematic diagram of another arrangement of the first bridge region and the second bridge region of the first bridge structure in the display panel according to the embodiment of the application;
FIG. 7 is a schematic diagram of another structure of the LEDs in the display panel provided in FIG. 1;
FIG. 8 is a schematic view of another structure of the LEDs in the display panel provided in FIG. 1;
FIG. 9 is a schematic diagram of a display panel according to another embodiment of the present application;
FIG. 10 is a schematic diagram of a display device according to an embodiment of the present application;
FIG. 11 is a flowchart of a method for fabricating a display panel according to an embodiment of the present application;
fig. 12 to 24 are cross-sectional views of a portion of a display panel according to an embodiment of the present application after each process step is completed.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present application is not limited to the specific embodiments disclosed below.
As described in the background section, in the existing Micro LED display panel, a huge amount of transfer bonding process is used to transfer Micro LEDs, and the huge amount of transfer bonding process has a pressurizing and heating process, so that both the Micro LEDs and the back plate are damaged, thereby causing the reliability problem of the Micro LED display panel.
The inventor researches and discovers that the conventional Micro LED display panel is characterized in that the LEDs are directly fixed on the driving panel through a huge transfer bonding process in the process of assembling the self-luminous micron-sized LEDs on the driving panel, and in the huge transfer bonding process, the contact area between the LEDs and the driving panel is required to be heated and pressurized, so that more stress accumulation exists in the manufactured Micro LED display panel, damage is caused to the Micro LEDs and the backboard of the display panel, and the reliability of the Micro LED display panel is affected.
In view of this, an embodiment of the present application provides a display panel, as shown in fig. 1, which includes:
an array substrate 10;
a plurality of LEDs 20, the plurality of LEDs 20 being located on a first side of the array substrate 10, as shown in fig. 2, the LEDs including a light emitting layer 21 and an electrode 22 located on a side of the light emitting layer 21 facing the array substrate 10;
A plurality of first bridge structures 30, wherein the first bridge structures 30 include a first bridge region 301 and a second bridge region 302, and the second bridge region 302 does not overlap the LEDs 20 in a direction perpendicular to a plane of the array substrate 10;
a plurality of second bridge structures 40, wherein the second bridge structures 40 are electrically connected with the array substrate 10, and the second bridge structures 40 and the electrodes 22 of the LEDs 20 are located on the same side of the first bridge structures 30 in the direction perpendicular to the plane of the array substrate 10;
wherein the electrode 22 of the LED20 is electrically connected to the first bridge region 301 of the first bridge structure 30, and the second bridge structure 40 is electrically connected to the second bridge region 302 of the first bridge structure 30.
Optionally, on the basis of the foregoing embodiment, in one embodiment of the present application, the second bridge structure is electrically connected to the array substrate through a via hole.
In particular, in one embodiment of the application, the LED is a Micro LED or a Mini LED, but the present application is not limited thereto, and the LED is specifically defined as the case may be.
Optionally, as further shown in fig. 2, the LED20 further includes an intrinsic semiconductor layer 24 located on a side of the light emitting layer 21 facing away from the electrode 22, where the intrinsic semiconductor layer includes a buffer layer, a low-temperature semiconductor layer, and a high-temperature semiconductor layer, where a surface of the buffer layer facing away from the light emitting layer has a bump to improve light emitting efficiency of the LED, the high-temperature semiconductor layer is used to improve flatness of a plane formed by the light emitting layer, and the low-temperature semiconductor layer is a transition layer between the buffer layer and the high-temperature semiconductor layer, and in other embodiments of the present application, the LED may further include other structures, which are not limited in this respect, and specific cases are defined by the present application.
In the display panel provided by the embodiment of the application, the electrode of the LED is electrically connected with the first bridging region of the first bridging structure, the second bridging structure is electrically connected with the second bridging region of the first bridging structure, and the second bridging structure is electrically connected with the array substrate, so that the electrode of the LED is electrically connected with the array substrate through the first bridging structure and the second bridging structure in sequence without adopting a huge transfer bonding process, the phenomenon of internal stress accumulation of the display panel caused by the introduction of the huge transfer bonding process is avoided, the stability of the display panel is improved, and the yield of the display panel is further improved.
Specifically, in one embodiment of the present application, as further shown in fig. 1, the first bridge structure 30 includes a first bridge electrode 31 and a second bridge electrode 32, the first bridge region includes a first bridge region of the first bridge electrode 31 and a first bridge region of the second bridge electrode 32, and the second bridge region includes a second bridge region of the first bridge electrode 31 and a second bridge region of the second bridge electrode 32; in this embodiment, the electrodes of the LED include an N electrode and a P electrode, the first bridge region of the first bridge electrode 31 is electrically connected to the N electrode of the LED, and the first bridge region of the second bridge electrode 32 is electrically connected to the P electrode of the LED; the second bridge structure 40 includes a third bridge electrode 41 and a fourth bridge electrode 42, the third bridge electrode 41 is electrically connected to the second region of the first bridge electrode 31, the fourth bridge electrode 42 is electrically connected to the second bridge region of the second bridge electrode 32, so that the N electrode of the LED is electrically connected to the array substrate 10 through the first bridge region of the first bridge electrode 31, the second bridge region of the first bridge electrode 31, and the third bridge electrode 41 of the second bridge structure 40 in sequence, and the P electrode of the LED is electrically connected to the array substrate 10 through the first bridge region of the second bridge electrode 32, the second bridge region of the second bridge electrode 32, and the fourth bridge electrode 42 of the second bridge structure 40 in sequence.
On the basis of any of the above embodiments, in one embodiment of the present application, as further shown in fig. 1 and 2, in a direction X perpendicular to the plane of the array substrate, the first bridge structure 30 at least partially overlaps the LED electrode 22 to ensure that the first bridge structure 30 may be electrically connected to at least a partial area of a side surface of the LED electrode 22 facing the array substrate 10, and in a direction Y parallel to the plane of the array substrate, the first bridge structure 30 at least partially overlaps the LED electrode 22 to enable the first bridge structure 30 to be electrically connected to at least a partial area of a side surface of the LED electrode 22, so that the first bridge structure 30 may be simultaneously electrically connected to the bottom surface and the side surface of the LED electrode 22, thereby increasing the electrical connection area of the first bridge structure 30 and the LED electrode 22 and improving the electrical connection performance of the first bridge structure 30 and the LED electrode 22.
In the embodiment of the present application, the first bridge structure is electrically connected to at least a portion of the area of the side surface of the LED electrode facing the array substrate, which may be the direct contact between the first bridge structure and at least a portion of the area of the side surface of the LED electrode facing the array substrate, or may be the electrical connection between the first bridge structure and at least a portion of the area of the side surface of the LED electrode facing the array substrate through a conductive layer, which is not limited in this way, according to circumstances.
Specifically, in one embodiment of the present application, as shown in fig. 1 and 2, the first bridge structure 30 includes a first bridge electrode 31 and a second bridge electrode 32, the electrodes of the LED include an N electrode 221 of the LED and a P electrode 222 of the LED, and in this embodiment, an electrical connection area between the first bridge electrode 31 and the N electrode 221 of the LED includes at least a partial area of a side surface of the N electrode 221 facing the array substrate 10 and at least a partial area of a side surface of the N electrode 221, so as to increase an electrical connection area between the first bridge electrode 31 and the N electrode 221 of the LED, and further improve electrical connection performance between the first bridge electrode 31 and the N electrode 221 of the LED; similarly, the electrical connection area between the second bridge electrode 31 and the P electrode 222 of the LED includes at least a partial area of the P electrode 222 facing the surface of the array substrate 10 and at least a partial area of the side surface of the P electrode 222, so as to increase the electrical connection area between the second bridge electrode 32 and the P electrode 222 of the LED, and further improve the electrical connection performance between the second bridge electrode 32 and the P electrode 222 of the LED. However, the present application is not limited thereto, and in other embodiments of the present application, as shown in fig. 3, the electrical connection area between the first bridge electrode 31 and the N electrode 221 of the LED may include only at least a portion of the area where the N electrode 221 faces the side surface of the array substrate 10, and the electrical connection area between the second bridge electrode 32 and the P electrode 222 of the LED may include only at least a portion of the area where the P electrode 222 faces the side surface of the array substrate 10, as the case may be.
Optionally, on the basis of the foregoing embodiment, in one embodiment of the present application, the first bridge electrode is directly contacted with the bottom surface and the side surface of the N electrode of the LED to further enhance the electrical connection performance between the first bridge electrode and the N electrode of the LED, and the second bridge electrode is directly contacted with the bottom surface and the side surface of the P electrode of the LED to further enhance the electrical connection performance between the second bridge electrode and the P electrode of the LED, but the present application is not limited thereto, and in other embodiments of the present application, the first bridge electrode may be electrically connected with the bottom surface and the side surface of the N electrode of the LED through a conductive layer, and the second bridge electrode is also electrically connected with the bottom surface and the side surface of the P electrode of the LED through a conductive layer, as the case may be.
In one embodiment of the present application, the light emitting layer of the LED includes an N-type semiconductor layer, a quantum well layer, and a P-type semiconductor layer stacked, wherein a stacked structure formed by the quantum well layer and the P-type semiconductor layer exposes a part of a surface of the N-type semiconductor layer, a P-electrode of the LED is electrically connected to the P-type semiconductor layer, and an N-electrode of the LED is electrically connected to the N-type semiconductor layer.
Optionally, on the basis of the foregoing embodiment, in one embodiment of the present application, a side surface of the P electrode facing the array substrate is flush with a side surface of the N electrode facing the array substrate, so as to facilitate electrical connection between the electrode of the LED and the first bridge structure. In this embodiment, since the P-type semiconductor layer is located on the side of the N-type semiconductor layer facing the array substrate, when the P-electrode faces the surface of the array substrate and the N-electrode faces the surface of the array substrate, the thickness of the N-electrode is greater than that of the P-electrode, and accordingly, the side area of the N-electrode is greater than that of the P-electrode.
As can be seen from the above, in this embodiment, the electrical connection area between the first bridge electrode and the N electrode includes, in addition to the surface of the N electrode facing the array substrate, a side surface of the N electrode, where the thickness of the N electrode is larger, and correspondingly, the area of the side surface of the N electrode is larger, and the area of the side surface of the N electrode that can be used for electrical connection with the first bridge electrode is larger; similarly, the electrical connection area between the second bridging electrode and the P electrode includes, besides the surface of the P electrode facing the array substrate, a side surface of the P electrode, where the thickness of the P electrode is smaller, and correspondingly, the area of the side surface of the P electrode is smaller, and the area of the side surface of the P electrode that can be used for electrical connection with the second bridging electrode is smaller.
Therefore, on the basis of the above-described embodiments, in one embodiment of the present application, as shown in fig. 4, in the direction X perpendicular to the plane of the array substrate 10, the overlapping area of the first bridging structure 30 and the N electrode 221 of the LED is smaller than the overlapping area of the first bridging structure 30 and the P electrode 222 of the LED, so that in the case where the distance between the N electrode 221 and the P electrode 222 in the LED is unchanged, the probability of a short circuit between the first bridging structure 30 and the N electrode 221 of the LED and the probability of a short circuit between the N electrode 221 of the LED and the second bridging structure 31 and the P electrode 222 of the LED are reduced by decreasing the overlapping area of the first bridging structure 30 and the N electrode 221 of the LED in the direction X perpendicular to the plane of the array substrate 10, that is, by decreasing the overlapping area of the first bridging structure 31 and the N electrode 221 of the LED in the direction X perpendicular to the plane of the array substrate 10.
On the basis of the above embodiment, in one embodiment of the present application, as shown in fig. 4, the overlapping area of the first bridging structure 30 and the N electrode 221 of the LED is larger than the overlapping area of the first bridging structure 30 and the P electrode 222 of the LED in the direction Y parallel to the plane of the array substrate 10, that is, the overlapping area of the first bridging electrode 31 and the N electrode 221 of the LED is larger than the overlapping area of the second bridging electrode 32 and the P electrode 222 of the LED in the direction Y parallel to the plane of the array substrate 10, so that the electrical connection area of the first bridging electrode 31 and the side of the N electrode 221 of the LED is larger than the electrical connection area of the second bridging electrode 32 and the side of the P electrode 222 of the LED, and thus the probability of the first bridging structure 30 and the N electrode 221 of the LED being electrically shorted to each other is reduced by reducing the overlapping area of the N electrode 221 of the LED in the direction X perpendicular to the plane of the array substrate 10, and the electrical connection performance of the first bridging electrode 31 and the LED is not specifically improved.
Specifically, in one embodiment of the present application, in order to ensure the electrical connection performance between the first bridge electrode and the N electrode, the width W1 of the electrical connection area between the bottom surface of the N electrode (i.e., the surface of the N electrode facing the array substrate) and the first bridge electrode satisfies the following relationship:
W1≥∣σ A ∣+∣σ B ∣+∣σ C ∣+Dcontact1；
wherein sigma A Representing the process error of the LED electrode in the direction parallel to the plane of the array substrate during manufacturing; sigma (sigma) B Representing the process error of the first bridging structure in the direction parallel to the plane of the array substrate during the manufacture; sigma (sigma) C Representing an alignment tolerance between the LED and the first bridge structure;
dcontact1 represents the minimum width of the N electrode to which the first bridge structure is electrically connected.
Similarly, in order to ensure the electrical connection performance between the second bridge electrode and the P electrode, the width W2 of the electrical connection area between the bottom surface of the P electrode (i.e., the surface of the P electrode facing the array substrate) and the second bridge electrode satisfies the following relationship:
W2≥∣σ A ∣+∣σ B ∣+∣σ C ∣+Dcontact2；
wherein sigma A Representing the process error of the LED electrode in the direction parallel to the plane of the array substrate during manufacturing; sigma (sigma) B Representing the process error of the first bridging structure in the direction parallel to the plane of the array substrate during the manufacture; sigma (sigma) C Representing an alignment tolerance between the LED and the first bridge structure;
dcontact2 represents the minimum width of the P electrode to which the first bridge structure is electrically connected.
On the basis of any one of the above embodiments, in one embodiment of the present application, in order to ensure electrical insulation between the P electrode and the N electrode in the LED, a width d of a distance between the P electrode and the N electrode in the LED satisfies the following relationship:
d≥∣σ A ∣+∣σ B ∣+∣σ C ∣+Dins；
wherein sigma A Representing the process error of the LED electrode in the direction parallel to the plane of the array substrate during manufacturing; sigma (sigma) B Representing the process error of the first bridging structure in the direction parallel to the plane of the array substrate during the manufacture; sigma (sigma) C Representing an alignment tolerance between the LED and the first bridge structure; dins represents the minimum width of the LED when the first bridge electrode is insulated from the P electrode, or the minimum width of the LED when the second bridge electrode is insulated from the N electrode.
On the basis of any of the above embodiments, in one embodiment of the present application, as further shown in fig. 4, the display panel further includes: a planarization layer 50, the planarization layer 50 is located between the LEDs 20 and the array substrate 10, the planarization layer 50 has a plurality of first grooves and a plurality of second grooves, the first bridge electrode 31 is located in the first grooves, and the second bridge electrode 32 is located in the second grooves, so as to accommodate the first bridge structure 30 in the planarization layer 50, but the application is not limited thereto.
On the basis of any of the above embodiments, in one embodiment of the present application, as shown in fig. 5, the first bridge region 301 and the second bridge region 302 of the first bridge structure 30 are arranged along a first direction C, where the first direction C is parallel to the plane of the array substrate 10, and the first direction C is parallel to the directions of the P electrodes 222 to the N electrodes 221 of the LEDs, so as to reduce the size of the first bridge structure 30 in the second direction D, facilitate the display panel to set more LEDs in the second direction D, and increase the pixels of the display panel in the second direction D. The second direction is parallel to the plane where the array substrate is located and intersects with the first direction. Optionally, the second direction is perpendicular to the first direction, but the present application is not limited thereto, and the present application is specifically limited thereto as the case may be.
In another embodiment of the present application, as shown in fig. 6, the first bridge area 301 and the second bridge area 302 of the first bridge structure 30 are arranged along the second direction D, where the first direction C and the second direction D are parallel to the plane of the array substrate 10, the first direction C is parallel to the directions of the P-electrode 222 to the N-electrode 221 of the LED, and the first direction C intersects with the second direction D, so as to reduce the size of the first bridge structure 30 in the first direction C, so that the display panel is provided with more LEDs in the first direction C, and increase the pixel point of the display panel in the first direction C. The application is not limited thereto and is specifically applicable.
On the basis of any one of the above embodiments, in one embodiment of the present application, the electrode of the LED includes: the P electrode is positioned on the surface of the P-type semiconductor layer in the light-emitting layer and is electrically connected with the P-type semiconductor layer of the light-emitting layer, and the N electrode is positioned on the surface of the N-type semiconductor layer in the light-emitting layer and is electrically connected with the N-type semiconductor layer in the light-emitting layer; in an embodiment of the present application, as shown in fig. 7, the LED further includes: the first protection layer 23 is located at the side of the light emitting layer 21 and covers the side of the light emitting layer 21 to protect the side of the light emitting layer 21, thereby avoiding damage to the side of the light emitting layer 21 during the manufacturing process of the first bridge structure. Optionally, the first protection layer 23 also covers the P-type semiconductor layer and the N-type semiconductor layer, but the present application is not limited thereto, and the present application is specifically limited as the case may be.
It should be noted that, in the embodiment of the present application, in the direction perpendicular to the plane of the array substrate, the first protection layer may overlap with the N electrode and the P electrode, as further shown in fig. 7, that is, the first protection layer 23 extends to a partial area between the N electrode 221 and the light-emitting layer 21 and a partial area between the bottom surface of the P electrode 222 and the light-emitting layer 21, or may not overlap, as shown in fig. 8, that is, the first protection layer 23 covers only the side surface of the light-emitting layer 21 and a partial surface of the N-type semiconductor layer in the light-emitting layer 21.
Alternatively, as further shown in fig. 7 and 8, when the LED further includes an intrinsic semiconductor layer 24 on a side of the light emitting layer 21 facing away from the electrode 22, the first protective layer 23 also covers a side surface of the intrinsic semiconductor layer 24.
It should be further noted that, even if the side surface of the light emitting layer is protected by the first protection layer, when the forming process of the first bridge structure adopts a dry etching process, the dry etching process etches the first protection layer to increase the probability of damaging the side surface of the light emitting layer, so, on the basis of the above embodiment, in one embodiment of the present application, the forming process of the first bridge structure adopts a wet etching process, but the present application is not limited thereto, and is specifically defined as the case may be.
It should be further noted that, because the first bridge structure is located on a side of the electrode of the LED facing away from the light emitting layer when the first bridge structure is fabricated, in order to avoid that the electrode of the LED is disabled during the fabrication process of the first bridge structure, in an embodiment of the present application, the fabrication material of the electrode of the LED includes a metal that cannot be etched by a wet etching process. Optionally, in an embodiment of the present application, a material for manufacturing the electrode of the LED includes gold, for example, a material for the P electrode includes gold, and a material for the N electrode includes gold, so as to avoid that the manufacturing process of the first bridge structure causes the electrode of the LED to fail, and affect the electrical connection performance between the first bridge structure and the electrode of the LED.
Optionally, in an embodiment of the present application, the electrode of the LED is made of a material that includes, in addition to gold, other metal materials, and the layer of gold is an outer surface layer of the electrode, so as to protect the other metal material layers of the electrode of the LED.
On the basis of any of the foregoing embodiments, in one embodiment of the present application, a dry etching process is used in the process of manufacturing the second bridge structure, and the material selection etching ratio of the second bridge structure to the first bridge structure is greater than 2, that is, the etching rate of the second bridge structure is greater than 2 times of the etching rate of the first bridge structure, so as to reduce damage to the first bridge structure during the formation of the second bridge structure. The application is not limited thereto and is specifically applicable.
On the basis of any one of the foregoing embodiments, in one embodiment of the present application, the display panel further includes: the display panel comprises a plurality of cathodes and a common cathode connecting wire electrically connected with the cathodes, so that one end of each of the LEDs electrically connected with the cathodes can transmit signals through one signal wire, and the number of the signal wires in the display panel is reduced.
Based on the above embodiments, in one embodiment of the present application, the second bridge structure and the common cathode connection line in the display panel are located at the same layer, so as to reduce the thickness of the display panel, which is beneficial to the development of the light and thin display panel, but the present application is not limited thereto, and the present application is specifically defined as the case may be.
On the basis of any of the above embodiments, in one embodiment of the present application, as shown in fig. 9, the display panel further includes:
the protection structures 60 are located at one side of the first bridging structure away from the array substrate 10, the protection structures 60 are in one-to-one correspondence with the LEDs 20, a first through hole is formed in the protection structures 60, and the LEDs 20 are located in the first through hole, so that the protection structures 60 are annularly arranged around the LEDs 20;
the refractive index of the second protective layer 70 is smaller than that of the protective structure 60, so that light emitted from the side surface of the LED20 to the protective structure 60 is totally reflected at the interface between the protective structure 60 and the second protective layer 70, reflected back to the upper LED20, and finally emitted from the side of the LED20 away from the array substrate 10, thereby improving the light-emitting efficiency of the display panel.
It should be noted that, in the embodiment of the present application, in the direction perpendicular to the plane of the array substrate 10, the cross-sectional view of the protection structure 60 is an inverted trapezoid, and the cross-sectional view of the protection structure is an inverted trapezoid, which means that in the direction perpendicular to the plane of the array substrate, the cross-sectional view of the protection structure is a trapezoid, and the side length of the cross-sectional view of the protection structure facing away from the side of the array substrate is greater than the side length of the cross-sectional view of the protection structure facing close to the side of the array substrate.
It should be noted that, the display panel provided by the embodiment of the present application may be a borderless display panel, a flexible display panel, a transparent display panel, or other various types of display panels, which is not limited in this aspect of the present application, and is specifically determined according to circumstances.
Correspondingly, as shown in fig. 10, the embodiment of the present application further provides a display device, which includes the display panel provided in any one of the embodiments, and optionally, the display device may be a device with a display function, such as a mobile phone, a computer, a television, etc., which is not limited in this regard, and the present application is specifically defined as the case may be.
In addition, the embodiment of the application also provides a manufacturing method of the display panel, as shown in fig. 11, the manufacturing method comprises the following steps:
S1: providing a first substrate, and forming a plurality of LEDs on a first side of the first substrate, wherein the LEDs comprise a light emitting layer and an electrode positioned on one side of the light emitting layer away from the first substrate.
Optionally, in an embodiment of the present application, the first substrate is a glass substrate, and forming the plurality of LEDs on the first side of the first substrate includes:
s11: as shown in fig. 12, a plurality of LEDs 20 are formed on a sapphire substrate 80, the LEDs 20 including a light emitting layer and electrodes electrically connected to the light emitting layer.
In one embodiment of the present application, forming a plurality of LEDs on a sapphire substrate includes:
forming a plurality of light emitting layers on a sapphire substrate;
and forming an electrode electrically connected with the light-emitting layer on one side of the light-emitting layer, which is away from the sapphire substrate.
Specifically, in one embodiment of the present application, as further shown in fig. 12, the light emitting layer includes a stacked N-type semiconductor layer 211, a quantum well layer 212 and a P-type semiconductor layer 213, wherein a stacked structure formed by the quantum well layer 212 and the P-type semiconductor layer 213 exposes a part of the surface of the N-type semiconductor layer 211; the electrodes of the LED include an N electrode 221 and a P electrode 222, the N electrode 221 is located on the surface of the N-type semiconductor layer 211 and is electrically connected to the N-type semiconductor layer 211, and the P electrode 222 is located on the surface of the P-type semiconductor layer 213 and is electrically connected to the P-type semiconductor layer 213.
Optionally, in an embodiment of the present application, the N-type semiconductor layer is an N-type doped GaN layer, the P-type semiconductor layer is a P-type doped GaN layer, and the quantum well layer is an InGaN multiple quantum well layer.
On the basis of the above embodiments, in one embodiment of the present application, the LED further includes: an intrinsic semiconductor layer 24, such as an intrinsic GaN layer, is located on the side of the light emitting layer facing away from the electrode. The intrinsic semiconductor layer comprises a buffer layer, a low-temperature semiconductor layer and a high-temperature semiconductor layer, wherein a bulge is arranged on one side surface of the buffer layer, which faces away from the light-emitting layer, so as to improve the light-emitting efficiency of the LED, the high-temperature semiconductor layer is used for improving the flatness of a forming plane of the light-emitting layer, the low-temperature semiconductor layer is a transition layer between the buffer layer and the high-temperature semiconductor layer, and is used as a lattice constant transition layer between the sapphire substrate and the light-emitting layer so as to improve the growth quality of the light-emitting layer.
Specifically, in one embodiment of the present application, taking the semiconductor layer as a GaN layer as an example, forming a plurality of LEDs on a sapphire substrate includes:
Patterning the surface of the sapphire substrate to enable the surface of the sapphire substrate to be provided with a plurality of grooves;
forming an intrinsic GaN layer, i.e., an undoped GaN layer, on a surface of the sapphire substrate having a groove side such that the intrinsic GaN layer has a plurality of protrusions toward the sapphire substrate side;
forming an N-type GaN layer on one side of the intrinsic GaN layer, which is away from the sapphire substrate;
forming an InGaN multi-quantum well layer on one side of the N-type GaN layer, which is away from the intrinsic GaN layer;
forming a P-type GaN layer on one side of the InGaN multi-quantum well layer, which is away from the N-type GaN layer;
etching a plurality of areas of the P-type GaN layer and the InGaN multi-quantum well layer to expose part of the surface of the N-type GaN layer;
cutting the N-type GaN layer and the intrinsic GaN layer to form a plurality of independent light-emitting layers;
and forming an N electrode electrically connected with the N-type GaN layer and a P electrode electrically connected with the P-type GaN layer on one side of the light-emitting layer, which is away from the sapphire substrate.
On the basis of any of the above embodiments, in one embodiment of the present application, as further shown in fig. 12, the LED further includes: the first protection layer 23 is located at the side of the light emitting layer and covers the side of the light emitting layer, so as to avoid damage to the side of the light emitting layer in the subsequent process. Specifically, in the present embodiment, forming a plurality of LEDs on a sapphire substrate includes:
Forming a plurality of light emitting layers on a sapphire substrate;
forming a first protective layer on the surface and the side surface of the light-emitting layer;
removing at least part of the area of the first protective layer on the surface of the N-type semiconductor layer in the light-emitting layer and at least part of the area of the surface of the P-type semiconductor layer in the light-emitting layer;
and forming an N electrode in a region of the N-type semiconductor layer which is not covered by the first protective layer, and forming a P electrode in a region of the P-type semiconductor layer which is not covered by the first protective layer.
Optionally, the first protection layer is a silicon dioxide layer, but the present application is not limited thereto, and the present application is specifically limited thereto as the case may be.
Specifically, on the basis of any one of the above embodiments, in one embodiment of the present application, the LED is a Micro LED or a Mini LED.
S12: as shown in fig. 13, a second substrate 81 is provided, and an alignment layer (not shown in the drawing) and an adhesive layer 82 are sequentially formed on the second substrate 81, and optionally, the second substrate is a glass substrate, where the alignment layer is used for positioning the placement position of the LED when the LED is subsequently transferred, and the adhesive layer is used for fixedly connecting the LED and the second substrate after the LED is subsequently transferred.
S13: continuing with fig. 13, the plurality of LEDs 20 on the sapphire substrate are transferred to a side of the adhesive layer 82 facing away from the second substrate 81, and the sapphire substrate 80 is removed.
Optionally, in one embodiment of the present application, the LEDs on the sapphire substrate are transferred to the side of the bonding layer facing away from the second substrate by using a laser lift-off technology, but the present application is not limited thereto.
S14: as shown in fig. 14, a second die attach layer 84 is formed on the first substrate 83, and the second die attach layer 84 is non-solid, and optionally, in an embodiment of the present application, the second die attach layer is a transparent flexible layer, such as a polyimide layer, but the present application is not limited thereto, and the present application is specifically limited thereto as the case may be.
In the embodiment of the present application, before the second die bonding layer is formed on the first substrate, an alignment layer may be formed on the first substrate, so as to improve alignment accuracy between the second substrate and the first substrate when the LEDs on the second substrate are subsequently transferred onto the first substrate. Optionally, the alignment layer on the first substrate is an annular metal layer, which may be disposed around one side of the second die bonding layer near the first substrate, corresponding to an edge area of the second die bonding layer, or may be disposed around the second die bonding layer in the same layer as the second die bonding layer.
S15: continuing to transfer the plurality of LEDs 20 on the second substrate 81 to the side of the second die bonding layer 84 facing away from the first substrate 83 as shown in fig. 14, and curing the second die bonding layer 84, removing the second substrate 81 as shown in fig. 15, so as to realize the transfer of the plurality of LEDs 20.
It should be noted that, in practical applications, the display panel may include LEDs of one color, and may also include LEDs of multiple colors. A process of forming a plurality of LEDs on a first side of the first substrate will be described below taking an example in which the display panel includes LEDs of three colors.
Specifically, in one embodiment of the present application, forming a plurality of LEDs on the first substrate includes:
forming a plurality of first color LEDs on a first sapphire substrate;
forming a plurality of second color LEDs on a second sapphire substrate;
forming a plurality of third color LEDs on a third sapphire substrate;
sequentially forming an alignment layer and an adhesive layer on a second substrate;
transferring a plurality of first color LEDs on the first sapphire substrate to one side of the bonding layer away from the second substrate, and removing the first sapphire substrate;
transferring a plurality of second color LEDs on the second sapphire substrate to one side of the bonding layer away from the second substrate, and removing the second sapphire substrate;
Transferring a plurality of third color LEDs on the third sapphire substrate to one side of the bonding layer away from the second substrate, and removing the third sapphire substrate;
forming a second die bonding layer on the first substrate, wherein the second die bonding layer is non-solid;
and transferring the LEDs with the multiple colors on the second substrate to one side of the second die bonding layer, which is away from the first substrate, and curing the second die bonding layer to remove the second substrate.
It should be noted that, the thickness of the LEDs of different colors in the direction perpendicular to the plane of the array substrate is different, and optionally, when the LEDs of multiple colors are formed on the second substrate, the LEDs with larger thickness are preferentially transferred, and then the LEDs with smaller thickness are transferred, so that the process difficulty of transferring the LEDs of different colors onto the second substrate is reduced.
Specifically, in one embodiment of the present application, the display panel includes: and the first color is red, the second color is green, and the third color is blue, namely, the red LEDs are transferred onto the second substrate, the green LEDs are transferred onto the second substrate, and the blue LEDs are transferred onto the second substrate.
It should be noted that, after the LEDs of different colors are transferred to the second substrate, when the LEDs on the second substrate are transferred to the first substrate, all the LEDs are simultaneously transferred to the first substrate, that is, all the LEDs on the second substrate are transferred to the first substrate in the same process, so as to improve the transfer efficiency of the LEDs transferred to the first substrate.
S2: as shown in fig. 16, a plurality of first bridge structures 30 are formed on a side of the plurality of LEDs 20 facing away from the first substrate 83, the first bridge structures 30 include a first bridge region and a second bridge region, the second bridge region does not overlap the LEDs 20 in a direction perpendicular to a plane of the first substrate 83, and electrodes of the LEDs 20 are electrically connected to the first bridge region of the first bridge structures 30.
Optionally, in an embodiment of the present application, a wet etching process is used in the forming process of the first bridge structure, so as to avoid damage to the side surface of the light emitting layer caused by etching the first protective layer when the first bridge structure uses dry etching.
Specifically, in one embodiment of the present application, forming a plurality of first bridge structures on a side of the plurality of LEDs facing away from the first substrate includes:
Forming a first bridging metal layer on one side of the LEDs facing away from the first substrate;
and carrying out wet etching on the first bridging metal to form a plurality of first bridging structures.
On the basis of reducing the probability of damage to the light-emitting layer caused by the first bridge structure forming process, in order to avoid damage to the electrode of the LED caused by the first bridge structure forming process, the electrode of the LED is made of an acid-resistant metal material, i.e., a metal that is not easily corroded by the wet etching process. Optionally, in one embodiment of the present application, the material of the electrode of the LED includes gold, but the present application is not limited thereto, and in other embodiments of the present application, the electrode material of the LED may also include other acid-resistant metal materials, where appropriate.
As can be seen from the above, the process of transferring the LEDs onto the first substrate includes two processes of transferring the LEDs from the sapphire substrate onto the second substrate and transferring the LEDs from the second substrate onto the first substrate, so that in the present embodiment, the alignment tolerance σ between the LEDs and the first bridge structure C Comprising the following steps: alignment tolerance of the LEDs on the sapphire substrate transferred to the second substrate and alignment tolerance of the LEDs on the second substrate transferred to the first substrate.
S3: as shown in fig. 17, the plurality of LEDs 20 and the plurality of first bridge structures 30 are transferred onto the array substrate 10, as shown in fig. 18, and the first substrate 83 is removed, the electrodes of the LEDs 20 are located at a side of the light emitting layer near the array substrate 10, and the first bridge structures 30 are located between the electrodes of the LEDs 20 and the array substrate 10.
Optionally, in one embodiment of the present application, transferring the plurality of LEDs and the plurality of first bridge structures to the first side of the array substrate includes:
continuing to refer to fig. 18, forming a first die attach layer 85 on a first side of the array substrate, where the first die attach layer 85 is non-solid;
transferring the plurality of LEDs 20 and the plurality of first bridge structures 30 to a first side of the array substrate 10;
the first die bond layer 85 is cured.
In the embodiment of the present application, the materials of the first die bonding layer and the second die bonding layer may be the same or different, and may be specific according to circumstances.
S4: and a second bridging structure is formed on one side, away from the array substrate, of the first bridging structure, the second bridging structure is electrically connected with a second bridging region of the first bridging structure, and the second bridging structure is electrically connected with the array substrate through a via hole, so that the electrodes of the LEDs sequentially pass through the first bridging structure, the second bridging structure and the array substrate, and a mass transfer bonding process is not needed, the phenomenon of internal stress accumulation of the display panel caused by the introduction of the mass transfer bonding process is avoided, and the stability of the display panel is improved.
As can be seen from the foregoing, the forming process of the first bridge structure adopts a wet etching process, so in an alternative embodiment of the present application, the forming process of the second bridge structure is a dry etching process, so as to reduce damage to the first bridge structure during the manufacturing process of the second bridge structure.
Specifically, in one embodiment of the present application, the second bridge structure is electrically connected to the pixel circuit in the array substrate through a via hole, in this embodiment, a second bridge structure is formed on a side of the first bridge structure facing away from the array substrate, the second bridge structure is electrically connected to the second bridge region of the first bridge structure, and the second bridge structure is electrically connected to the array substrate through a via hole, where the second bridge structure includes:
as shown in fig. 19, a first portion of the second die attach layer 84 is removed, a second portion of the second die attach layer 84 is left, and a plurality of second through holes are formed in the second die attach layer 84, wherein the second through holes expose at least a second bridge region of the first bridge structure 30 and a region between adjacent first bridge structures 30;
as shown in fig. 20, removing a portion of the first die bonding layer 85, and forming a via hole 86 in the first die bonding layer 85, where the via hole 85 exposes a region of the pixel circuit in the array substrate 10 for electrically connecting with the second bridge structure;
As shown in fig. 21, a second bridge structure 40 is formed on a side of the first bridge structure 30 facing away from the array substrate 10, and the second bridge structure 40 is electrically connected to the second bridge region of the first bridge structure 30 and electrically connected to the pixel circuit in the array substrate 10 through a via hole.
As can be seen from the above process, the second through hole and the via hole are formed in different processes, and in a direction parallel to the plane of the array substrate, the cross-sectional area of the second through hole is far greater than that of the via hole, so as to avoid that the first die bonding layer is removed during the formation of the second through hole, in an embodiment of the present application, the etching selection ratio of the second die bonding layer to the first die bonding layer is greater than 2, that is, under the process condition of forming the second through hole, the etched rate of the second die bonding layer is greater than twice the etched rate of the first die bonding layer, but the present application is not limited thereto, and is specifically determined according to circumstances.
In one embodiment of the present application, if the process of forming the second bridge structures is a dry etching process and the difference between the etching selectivity of the second die attach layer and the etching selectivity of the first die attach layer is not greater than 2, the method further includes, before transferring the plurality of LEDs and the plurality of first bridge structures to the first side of the array substrate: as shown in fig. 22 and 23, a planarization layer 50 is formed on a side of the first bridge structure 30 facing away from the LED20, so as to protect the first die attach layer 85 during the formation of the second via by the planarization layer 50. It should be noted that, in the embodiment of the present application, the planarization layer has a plurality of first grooves and a plurality of second grooves, where the first bridge electrode is located in the first grooves, and the second bridge electrode is located in the second grooves.
On the basis of any one of the foregoing embodiments, in one embodiment of the present application, the second through hole is a trapezoidal through hole, and the method further includes: as shown in fig. 24, a second protection layer 70 is formed to cover the second die bonding layer 84 and the LED20, where the refractive index of the second protection layer 70 is smaller than that of the second die bonding layer 84, so that light emitted from the side of the LED20 to the second die bonding layer 84 is totally reflected at the interface between the second die bonding layer 84 and the second protection layer 70, and is reflected back to the LED, and finally emitted from the side of the LED away from the array substrate, thereby improving the light extraction efficiency of the display panel.
It should be noted that, in the embodiment of the present application, in a direction perpendicular to the plane where the array substrate is located, the second through hole is an inverted trapezoid through hole, that is, a side length of the second through hole away from the array substrate is greater than a side length of the second through hole close to the array substrate.
In summary, in the display panel and the manufacturing method thereof provided by the embodiments of the present application, the electrode of the LED is electrically connected to the first bridge area of the first bridge structure, the second bridge structure is electrically connected to the second bridge area of the first bridge structure, and the second bridge structure is electrically connected to the array substrate, so that the electrode of the LED is electrically connected to the array substrate through the first bridge structure and the second bridge structure sequentially, without using a huge transfer bonding process, thereby avoiding the phenomenon of internal stress accumulation of the display panel due to the introduction of the huge transfer bonding process, improving the stability of the display panel, being beneficial to the realization of a large-sized Micro/Mini LED display panel, and further improving the yield of the display panel.
In the description, each part is described in a parallel and progressive mode, and each part is mainly described as a difference with other parts, and all parts are identical and similar to each other.
The features described in the various embodiments of the present disclosure may be interchanged or combined with one another in the description to enable those skilled in the art to make or use the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (20)
1. A display panel, comprising:
an array substrate;
the LED comprises a light-emitting layer and an electrode, wherein the electrode is positioned on one side of the light-emitting layer close to the array substrate;
the first bridging structures comprise first bridging areas and second bridging areas, and the second bridging areas are not overlapped with the LEDs in the direction perpendicular to the plane of the array substrate;
The second bridging structures are electrically connected with the array substrate, and the second bridging structures and the electrodes of the LEDs are positioned on the same side of the first bridging structures in the direction perpendicular to the plane of the array substrate;
wherein the electrode of the LED is electrically connected with a first bridging region of the first bridging structure, and the second bridging structure is electrically connected with a second bridging region of the first bridging structure;
in the direction perpendicular to the plane of the array substrate, the first bridging structure at least partially overlaps the LED electrode; and in the direction parallel to the plane of the array substrate, the first bridging structure at least partially overlaps the LED electrode.
2. The display panel of claim 1, wherein the first bridge structure comprises a first bridge electrode and a second bridge electrode, the first bridge region comprising a first bridge region of the first bridge electrode and a first bridge region of the second bridge electrode, the second bridge region comprising a second bridge region of the first bridge electrode and a second bridge region of the second bridge electrode;
The first bridging region of the first bridging electrode is electrically connected with the N electrode of the LED, and the first bridging region of the second bridging electrode is electrically connected with the P electrode of the LED;
the second bridge structure includes a third bridge electrode electrically connected to the second bridge region of the first bridge electrode and a fourth bridge electrode electrically connected to the second bridge region of the second bridge electrode.
3. The display panel of claim 1, wherein an overlapping area of the first bridge structure and the N electrode of the LED is smaller than an overlapping area of the first bridge structure and the P electrode of the LED in a direction perpendicular to a plane of the array substrate, and an overlapping area of the first bridge structure and the N electrode of the LED is larger than an overlapping area of the first bridge structure and the P electrode of the LED in a direction parallel to the plane of the array substrate.
4. The display panel of claim 2, further comprising:
the planarization layer is positioned between the LEDs and the array substrate, a plurality of first grooves and a plurality of second grooves are formed in the planarization layer, the first bridging electrodes are positioned in the first grooves, and the second bridging electrodes are positioned in the second grooves.
5. The display panel of claim 1, wherein the first and second bridge regions of the first bridge structure are arranged along a first direction or the first and second bridge regions of the first bridge structure are arranged along a second direction;
the first direction and the second direction are parallel to the plane where the array substrate is located, the first direction is parallel to the direction from the P electrode to the N electrode of the LED, and the first direction and the second direction are intersected.
6. The display panel of claim 1, wherein the electrodes of the LEDs comprise: the P electrode is positioned on the surface of the P-type semiconductor layer in the light-emitting layer and is electrically connected with the P-type semiconductor layer of the light-emitting layer, and the N electrode is positioned on the surface of the N-type semiconductor layer in the light-emitting layer and is electrically connected with the N-type semiconductor layer of the light-emitting layer;
the LED further includes: and the first protection layer is positioned on the side surface of the light-emitting layer and covers the side surface of the light-emitting layer.
7. The display panel of claim 6, wherein the material of the P electrode comprises gold and the material of the N electrode comprises gold.
8. The display panel of claim 1, further comprising: the second bridging structure and the common cathode connecting wire in the display panel are positioned on the same layer.
9. The display panel of claim 1, further comprising:
the protection structures are located on one side, away from the array substrate, of the first bridging structure, the protection structures are in one-to-one correspondence with the LEDs, first through holes are formed in the protection structures, and the LEDs are located in the first through holes;
and a second protective layer covering the protective structure and the LED, wherein the refractive index of the second protective layer is smaller than that of the protective structure.
10. The display panel of claim 1, wherein an etch selectivity of a material of the second bridge structure and a material of the first bridge structure is greater than 2.
11. A method for manufacturing a display panel, comprising:
providing a first substrate, and forming a plurality of LEDs on a first side of the first substrate, wherein the LEDs comprise a light-emitting layer and an electrode positioned on one side of the light-emitting layer away from the first substrate;
forming a plurality of first bridging structures on one side of the LEDs, which is away from the first substrate, wherein the first bridging structures comprise first bridging areas and second bridging areas, the second bridging areas are not overlapped with the LEDs in the direction perpendicular to the plane of the first substrate, and the LED electrodes are electrically connected with the first bridging areas of the first bridging structures;
Transferring the LEDs and the first bridging structures to an array substrate, removing the first substrate, wherein the electrodes of the LEDs are positioned on one side of the light-emitting layer, which is close to the array substrate, and the first bridging structures are positioned between the electrodes of the LEDs and the array substrate;
forming a second bridging structure on one side of the first bridging structure, which is away from the array substrate, wherein the second bridging structure is electrically connected with a second bridging region of the first bridging structure, and the second bridging structure is electrically connected with the array substrate through a via hole;
in the direction perpendicular to the plane of the array substrate, the first bridging structure at least partially overlaps the LED electrode; and in the direction parallel to the plane of the array substrate, the first bridging structure at least partially overlaps the LED electrode.
12. The method of manufacturing of claim 11, wherein transferring the plurality of LEDs and the plurality of first bridging structures to the first side of the array substrate comprises:
forming a first die bonding layer on a first side of the array substrate, wherein the first die bonding layer is non-solid;
transferring the plurality of LEDs and the plurality of first bridging structures to a first side of the array substrate;
And solidifying the first crystal-fixing layer.
13. The method of manufacturing of claim 12, wherein forming a plurality of first bridge structures on a side of the plurality of LEDs facing away from the first substrate comprises:
forming a first bridging metal layer on one side of the LEDs facing away from the first substrate;
and carrying out wet etching on the first bridging metal to form a plurality of first bridging structures.
14. The method of manufacturing of claim 13, wherein forming a plurality of LEDs on the first side of the first substrate comprises:
forming a plurality of LEDs on a sapphire substrate;
providing a second substrate, and sequentially forming an alignment layer and an adhesive layer on the second substrate;
transferring a plurality of LEDs on the sapphire substrate to one side of the bonding layer away from the second substrate, and removing the sapphire substrate;
forming a second die bonding layer on the first substrate, wherein the second die bonding layer is non-solid;
and transferring the LEDs on the second substrate to one side of the second die bonding layer, which is away from the first substrate, and curing the second die bonding layer to remove the second substrate.
15. The method of manufacturing of claim 14, wherein forming a plurality of LEDs on a sapphire substrate comprises:
Forming a plurality of light emitting layers on a sapphire substrate;
forming a first protective layer on the surface and the side surface of the light-emitting layer;
removing at least part of the area of the first protective layer on the surface of the N-type layer in the light-emitting layer and at least part of the area of the surface of the P-type layer in the light-emitting layer;
and forming an N electrode in a region of the N type layer which is not covered by the first protective layer, and forming a P electrode in a region of the P type layer which is not covered by the first protective layer.
16. The method of claim 14, wherein the second bridge structure is formed by a dry etching process, and the etching selectivity of the second die attach layer to the first die attach layer is greater than 2.
17. The method of claim 14, wherein the second bridge structure forming process is a dry etching process, the second die attach layer and the first die attach layer having an etch selectivity difference of no greater than 2, the method further comprising, prior to transferring the plurality of LEDs and the plurality of first bridge structures to the first side of the array substrate:
and forming a planarization layer on one side of the first bridging structure, which is away from the LED, wherein the planarization layer is provided with a plurality of first grooves and a plurality of second grooves, the first bridging structure is positioned in the first grooves, and the second bridging structure is positioned in the second grooves.
18. The method of claim 14, wherein forming a second bridge structure on a side of the first bridge structure facing away from the array substrate comprises:
removing a first part of the second die bonding layer, reserving a second part of the second die bonding layer, and forming a plurality of second through holes in the second die bonding layer, wherein the second through holes at least expose a second bridging region of the first bridging structure and a region between adjacent first bridging structures;
forming a via hole in the first die bonding layer, wherein the via hole exposes a region of the pixel circuit in the array substrate for electrically connecting with the second bridging structure;
and forming a second bridging structure on one side of the first bridging structure, which is away from the array substrate, wherein the second bridging structure is electrically connected with a second bridging region of the first bridging structure and is electrically connected with a pixel circuit in the array substrate through a via hole.
19. The method of manufacturing of claim 18, wherein the second via is a trapezoidal via, the method further comprising:
and forming a second protection layer which covers the second die bonding layer and the LED, wherein the refractive index of the second protection layer is smaller than that of the second die bonding layer.
20. A display device comprising the display panel of any one of claims 1-10.
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| CN112928196A (en) * | 2021-01-29 | 2021-06-08 | 厦门天马微电子有限公司 | Display panel, manufacturing method thereof and display device |
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| CN109037239B (en) * | 2018-07-26 | 2020-11-17 | 上海天马微电子有限公司 | Array substrate, preparation method thereof and display panel |
| CN109273479B (en) * | 2018-09-20 | 2021-07-23 | 上海天马微电子有限公司 | Display panel and manufacturing method thereof |
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| CN111864038A (en) * | 2019-04-28 | 2020-10-30 | 陕西坤同半导体科技有限公司 | Display panel, display device and preparation method of display panel |
| CN112928196A (en) * | 2021-01-29 | 2021-06-08 | 厦门天马微电子有限公司 | Display panel, manufacturing method thereof and display device |
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