CN113421892A - Display panel, manufacturing method thereof and display device - Google Patents

Display panel, manufacturing method thereof and display device Download PDF

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Publication number
CN113421892A
CN113421892A CN202110671282.8A CN202110671282A CN113421892A CN 113421892 A CN113421892 A CN 113421892A CN 202110671282 A CN202110671282 A CN 202110671282A CN 113421892 A CN113421892 A CN 113421892A
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bridge
electrode
bridging
layer
leds
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CN113421892B (en
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戴文君
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Shanghai Tianma Microelectronics Co Ltd
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Shanghai Tianma Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Led Devices (AREA)

Abstract

The embodiment of the application discloses a display panel, a manufacturing method thereof and a display device, wherein the display panel comprises: the LED array substrate comprises an array substrate, a plurality of LEDs, a plurality of first bridging structures and a plurality of second bridging structures, wherein the first bridging structures comprise first bridging areas and second bridging areas, the second bridging areas are not overlapped with the LEDs in the direction perpendicular to the plane of the array substrate, the second bridging structures are electrically connected with the array substrate, and the electrodes of the second bridging structures and the LEDs are positioned on the same side of the first bridging structures in the direction perpendicular to the plane of the array substrate; and the electrodes of the LED are electrically connected with the first bridging area of the first bridging structure, and the second bridging structure is electrically connected with the second bridging area of the first bridging structure, so that the electrodes of the LED are electrically connected with the array substrate sequentially through the first bridging structure and the second bridging structure, and the stability of the display panel is improved.

Description

Display panel, manufacturing method thereof and display device
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a display panel, a method for manufacturing the display panel, and a display device including the display panel.
Background
With the development of display technology, the display panel has become more and more widely used, and has been gradually applied to various fields of work and life of people, thereby bringing great convenience to the work and life of people. The Micro LED display panel is a display panel which takes self-luminous micrometer LEDs as light-emitting pixel units and is assembled on a driving panel to form a high-density LED array, and compared with an LCD and an OLED, the Micro LED display panel has the advantages of higher brightness, higher resolution, higher contrast, higher energy consumption, longer service life, higher response speed, higher thermal stability and the like in the aspect of display. However, in the manufacturing process of the existing Micro LED display panel, a bulk transfer bonding process is used for transferring the Micro LEDs, and the bulk transfer bonding process has a pressurizing and heating process, which damages both the Micro LEDs and the back plate, thereby causing the reliability problem of the Micro LED display panel.
Disclosure of Invention
In order to solve the above technical problem, an embodiment of the present application provides a display panel to improve reliability of the display panel.
In order to solve the above problem, the embodiment of the present application provides the following technical solutions:
a display panel, comprising:
an array substrate;
the LEDs are positioned on the first side of the array substrate and comprise light-emitting layers and electrodes positioned on one sides, close to the array substrate, of the light-emitting layers;
a plurality of first bridge structures, each of the first bridge structures including a first bridge region and a second bridge region, and the second bridge regions do not overlap with the LEDs in a direction perpendicular to a plane of the array substrate;
the second bridge structures are electrically connected with the array substrate, and in the direction perpendicular to the plane of the array substrate, the second bridge structures and the electrodes of the LEDs are positioned on the same side of the first bridge structures;
wherein the electrodes of the LED are electrically connected to the first bridge region of the first bridge structure, and the second bridge structure is electrically connected to the second bridge region of the first bridge structure.
A manufacturing method of a display panel comprises the following steps:
providing a first substrate, and forming a plurality of LEDs on a first side of the first substrate, wherein the LEDs comprise a light-emitting layer and an electrode positioned on one side of the light-emitting layer, which is far away from the first substrate;
forming a plurality of first bridging structures on the side, away from the first substrate, of the plurality of LEDs, wherein each first bridging structure comprises a first bridging area and a second bridging area, the second bridging areas are not overlapped with the LEDs in the direction perpendicular to the plane of the first substrate, and the LED electrodes are electrically connected with the first bridging areas of the first bridging structures;
transferring the LEDs and the first bridging structures onto an array substrate, and removing the first substrate, wherein the electrodes of the LEDs are positioned on one side of the light-emitting layer close to the array substrate, and the first bridging structures are positioned between the electrodes of the LEDs and the array substrate;
and forming a second bridging structure on one side of the first bridging structure, which is far away from the array substrate, wherein the second bridging structure is electrically connected with the second bridging area of the first bridging structure, and the second bridging structure is electrically connected with the array substrate through a through hole.
A display device comprises the display panel.
Compared with the prior art, the technical scheme has the following advantages:
in the technical scheme provided by the embodiment of the application, the electrode of the LED is electrically connected with the first bridging area of the first bridging structure, the second bridging structure is electrically connected with the second bridging area of the first bridging structure, and the second bridging structure is electrically connected with the array substrate, so that the electrode of the LED sequentially passes through the first bridging structure, the second bridging structure and the array substrate, a large-amount transfer bonding process is not needed, the phenomenon of stress accumulation inside the display panel caused by introducing the large-amount transfer bonding process is avoided, the stability of the display panel is improved, and the yield of the display panel is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a structure of LEDs in the display panel of FIG. 1;
fig. 3 is a schematic structural diagram of a display panel according to another embodiment of the present application;
fig. 4 is a schematic structural diagram of a display panel according to another embodiment of the present application;
fig. 5 is a schematic layout view of a first bridge region and a second bridge region of a first bridge structure in a display panel according to an embodiment of the present disclosure;
fig. 6 is another schematic layout diagram of a first bridge region and a second bridge region of a first bridge structure in a display panel according to an embodiment of the present disclosure;
FIG. 7 is a schematic view of another structure of the LEDs in the display panel of FIG. 1;
FIG. 8 is a schematic diagram of another structure of the LED in the display panel of FIG. 1;
fig. 9 is a schematic structural diagram of a display panel according to yet another embodiment of the present application;
FIG. 10 is a schematic diagram of a display device according to an embodiment of the present application;
fig. 11 is a flowchart illustrating a method for manufacturing a display panel according to an embodiment of the present application;
fig. 12 to fig. 24 are partial structural cross-sectional views after the completion of each process step in the method for manufacturing a display panel according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be apparent to those of ordinary skill in the art that the present application is not limited to the specific embodiments disclosed below.
As described in the background section, in the conventional Micro LED display panel, a bulk transfer bonding process is used to transfer the Micro LEDs during the manufacturing process, and the bulk transfer bonding process has a pressure heating process and damages both the Micro LEDs and the back plate, thereby causing the reliability problem of the Micro LED display panel.
The inventor researches and discovers that the reason is that in the process of assembling the self-luminous micron-sized LED on the driving panel of the conventional Micro LED display panel, the LED is generally directly fixed on the driving panel through a mass transfer bonding process, and in the mass transfer bonding process, the contact area of the LED and the driving panel needs to be heated and pressurized, so that more stress accumulation exists in the manufactured Micro LED display panel, the Micro LED and a back plate of the display panel are damaged, and the reliability of the Micro LED display panel is influenced.
In view of this, an embodiment of the present application provides a display panel, as shown in fig. 1, including:
an array substrate 10;
a plurality of LEDs 20, wherein the plurality of LEDs 20 are located on the first side of the array substrate 10, as shown in fig. 2, the LEDs comprise a light-emitting layer 21 and an electrode 22 located on the side of the light-emitting layer 21 facing the array substrate 10;
a plurality of first bridge structures 30, wherein each first bridge structure 30 comprises a first bridge region 301 and a second bridge region 302, and the second bridge region 302 does not overlap with the LEDs 20 in a direction perpendicular to the plane of the array substrate 10;
a plurality of second bridge structures 40, wherein the second bridge structures 40 are electrically connected to the array substrate 10, and in a direction perpendicular to the plane of the array substrate 10, the second bridge structures 40 and the electrodes 22 of the LEDs 20 are located on the same side of the first bridge structures 30;
wherein the electrode 22 of the LED20 is electrically connected to the first bridging region 301 of the first bridging structure 30, and the second bridging structure 40 is electrically connected to the second bridging region 302 of the first bridging structure 30.
Optionally, on the basis of the above embodiments, in an embodiment of the present application, the second bridging structure is electrically connected to the array substrate through a via.
Specifically, in an embodiment of the application, the LED is a Micro LED or a Mini LED, but the application does not limit this, as the case may be.
Optionally, as shown in fig. 2, the LED20 further includes an intrinsic semiconductor layer 24 located on a side of the light emitting layer 21 away from the electrode 22, where the intrinsic semiconductor layer includes a buffer layer, a low temperature semiconductor layer and a high temperature semiconductor layer, where a surface of the buffer layer facing away from the light emitting layer has a protrusion to improve the light emitting efficiency of the LED, the high temperature semiconductor layer is used to improve the flatness of the plane formed by the light emitting layer, the low temperature semiconductor layer is a transition layer between the buffer layer and the high temperature semiconductor layer, in other embodiments of the present application, the LED may further include other structures, which is not limited in this application, as the case may be.
In the display panel provided by the embodiment of the application, the electrode of the LED is electrically connected with the first bridging area of the first bridging structure, the second bridging structure is electrically connected with the second bridging area of the first bridging structure, and the second bridging structure is electrically connected with the array substrate, so that the electrode of the LED sequentially passes through the first bridging structure, the second bridging structure and the array substrate, a large-amount transfer bonding process is not needed, the phenomenon of stress accumulation inside the display panel caused by introducing the large-amount transfer bonding process is avoided, the stability of the display panel is improved, and the yield of the display panel is improved.
Specifically, on the basis of the above-mentioned embodiments, in an embodiment of the present application, as shown in fig. 1, the first bridging structure 30 includes a first bridging electrode 31 and a second bridging electrode 32, the first bridging region includes a first bridging region of the first bridging electrode 31 and a first bridging region of the second bridging electrode 32, and the second bridging region includes a second bridging region of the first bridging electrode 31 and a second bridging region of the second bridging electrode 32; in this embodiment, the electrodes of the LED include an N electrode and a P electrode, the first bridge region of the first bridge electrode 31 is electrically connected to the N electrode of the LED, and the first bridge region of the second bridge electrode 32 is electrically connected to the P electrode of the LED; the second bridge structure 40 includes a third bridge electrode 41 and a fourth bridge electrode 42, the third bridge electrode 41 is electrically connected to the second region of the first bridge electrode 31, the fourth bridge electrode 42 is electrically connected to the second bridge region of the second bridge electrode 32, so that the N electrode of the LED sequentially passes through the first bridge region of the first bridge electrode 31, the second bridge region of the first bridge electrode 31, and the third bridge electrode 41 of the second bridge structure 40, and is electrically connected to the array substrate 10, and the P electrode of the LED sequentially passes through the first bridge region of the second bridge electrode 32, the second bridge region of the second bridge electrode 32, and the fourth bridge electrode 42 of the second bridge structure 40, and is electrically connected to the array substrate 10.
On the basis of any of the above embodiments, in an embodiment of the present application, as shown in fig. 1 and fig. 2, in a direction X perpendicular to a plane of the array substrate, the first bridging structure 30 at least partially overlaps the LED electrode 22 to ensure that the first bridging structure 30 can be electrically connected to at least a partial region of a side surface of the LED electrode 22 facing the array substrate 10, and in a direction Y parallel to the plane of the array substrate, the first bridging structure 30 at least partially overlaps the LED electrode 22 to enable the first bridging structure 30 to be electrically connected to at least a partial region of a side surface of the LED electrode 22, so that the first bridging structure 30 can be electrically connected to a bottom surface and a side surface of the LED electrode 22 at the same time to increase an electrical connection area of the first bridging structure 30 and the LED electrode 22, the electrical connection performance of the first bridge structure 30 and the LED electrode 22 is improved.
It should be noted that, in the embodiment of the present application, the first bridging structure and at least a partial region of a surface of the LED electrode facing the array substrate are electrically connected, where the first bridging structure and at least a partial region of a surface of the LED electrode facing the array substrate are directly in contact with each other, and the first bridging structure and at least a partial region of a surface of the LED electrode facing the array substrate are electrically connected through a conductive layer, which is not limited in this application, and is determined as the case may be.
Specifically, in an embodiment of the present application, as shown in fig. 1 and fig. 2 again, the first bridging structure 30 includes a first bridging electrode 31 and a second bridging electrode 32, the LED electrodes include an LED N electrode 221 and an LED P electrode 222, in this embodiment, an electrical connection region between the first bridging electrode 31 and the LED N electrode 221 includes at least a partial region of a side surface of the N electrode 221 facing the array substrate 10 and at least a partial region of a side surface of the N electrode 221, so as to increase an electrical connection area between the first bridging electrode 31 and the LED N electrode 221, and further improve electrical connection performance between the first bridging electrode 31 and the LED N electrode 221; similarly, the electrical connection region between the second bridge electrode 31 and the P-electrode 222 of the LED includes at least a partial region of a surface of the P-electrode 222 facing the array substrate 10 and at least a partial region of a side of the P-electrode 222, so as to increase an electrical connection area between the second bridge electrode 32 and the P-electrode 222 of the LED, and further improve an electrical connection performance between the second bridge electrode 32 and the P-electrode 222 of the LED. However, this is not limited in this application, and in other embodiments of the present application, as shown in fig. 3, the electrical connection region between the first bridge electrode 31 and the N electrode 221 of the LED may only include at least a partial region of the surface of the N electrode 221 facing the array substrate 10, and the electrical connection region between the second bridge electrode 32 and the P electrode 222 of the LED may only include at least a partial region of the surface of the P electrode 222 facing the array substrate 10, as the case may be.
Optionally, on the basis of the above embodiments, in an embodiment of the present application, the first bridge electrode directly contacts with the bottom surface and the side surface of the N electrode of the LED to further enhance the electrical connection performance of the first bridge electrode with the N electrode of the LED, and the second bridge electrode directly contacts with the bottom surface and the side surface of the P electrode of the LED to further enhance the electrical connection performance of the second bridge electrode with the P electrode of the LED, but the present application is not limited thereto.
On the basis of any one of the above embodiments, in an embodiment of the present application, the light emitting layer of the LED includes an N-type semiconductor layer, a quantum well layer, and a P-type semiconductor layer, which are stacked, wherein a stacked structure formed by the quantum well layer and the P-type semiconductor layer exposes a part of a surface of the N-type semiconductor layer, the P-electrode of the LED is electrically connected to the P-type semiconductor layer, and the N-electrode of the LED is electrically connected to the N-type semiconductor layer.
Optionally, on the basis of the above embodiment, in an embodiment of the present application, a surface of the P electrode facing the array substrate is flush with a surface of the N electrode facing the array substrate, so as to facilitate electrical connection between the electrode of the LED and the first bridging structure. It should be noted that, in this embodiment, since the P-type semiconductor layer is located on a side of the N-type semiconductor layer facing the array substrate, when a surface of the P-electrode facing the array substrate is flush with a surface of the N-electrode facing the array substrate, a thickness of the N-electrode is greater than a thickness of the P-electrode, and accordingly, a side area of the N-electrode is greater than a side area of the P-electrode.
As can be seen from the above, in this embodiment, the electrical connection area between the first bridge electrode and the N electrode includes the side surface of the N electrode in addition to the surface of the N electrode facing the array substrate, the thickness of the N electrode is larger, accordingly, the area of the side surface of the N electrode is larger, and the area of the side surface of the N electrode, which can be used to electrically connect with the first bridge electrode, is larger; similarly, the area of the electrical connection between the second bridge electrode and the P electrode includes the side surface of the P electrode facing the array substrate, and the side surface of the P electrode is smaller.
Therefore, on the basis of the above-mentioned embodiments, in one embodiment of the present application, as shown in fig. 4, in the direction X perpendicular to the plane of the array substrate 10, the overlapping area of the first bridge structure 30 and the N electrode 221 of the LED is smaller than the overlapping area of the first bridge structure 30 and the P electrode 222 of the LED, so that in the case that the distance between the N electrode 221 and the P electrode 222 in the LED is not changed, the distance between the first bridge structure 30 and the N electrode 221 of the LED is increased by reducing the overlapping area of the first bridge structure 30 and the N electrode 221 of the LED in the direction X perpendicular to the plane of the array substrate 10, that is, by reducing the overlapping area of the first bridge electrode 31 and the N electrode 221 of the LED in the direction X perpendicular to the plane of the array substrate 10, thereby reducing the probability of a short circuit between the first bridge electrode 31 and the second bridge electrode 32, and thus between the N-electrode 221 of the LED and the P-electrode 222 of the LED.
On the basis of the above embodiments, in an embodiment of the present application, as shown in fig. 4, in a direction Y parallel to a plane of the array substrate 10, an overlapping area of the first bridge structure 30 and the LED N electrode 221 is larger than an overlapping area of the first bridge structure 30 and the LED P electrode 222, that is, in the direction Y parallel to the plane of the array substrate 10, an overlapping area of the first bridge electrode 31 and the LED N electrode 221 is larger than an overlapping area of the second bridge electrode 32 and the LED P electrode 222, so that an electrical connection area of the first bridge electrode 31 and a side of the LED N electrode 221 is larger than an electrical connection area of the second bridge electrode 32 and a side of the LED P electrode 222, thereby reducing an electrical connection area in a direction X perpendicular to the plane of the array substrate 10, the overlapping area of the first bridging structure 30 and the N electrode 221 of the LED reduces the probability of short circuit between the N electrode 221 of the LED and the P electrode 222 of the LED, increases the electrical connection area between the first bridging electrode 31 and the N electrode 221 of the LED, and improves the electrical connection performance between the first bridging electrode 31 and the N electrode 221 of the LED.
Specifically, on the basis of any of the above embodiments, in one embodiment of the present application, in order to ensure the electrical connection performance between the first bridge electrode and the N electrode, the width W1 of the electrical connection region between the bottom surface of the N electrode (i.e., the surface of the N electrode facing the array substrate) and the first bridge electrode satisfies the following relationship:
W1≥∣σA∣+∣σB∣+∣σC∣+Dcontact1；
wherein σARepresenting the process error of the LED electrode in the plane direction parallel to the array substrate during the manufacturing process; sigmaBRepresenting the process error of the first bridging structure in the plane direction parallel to the array substrate during the manufacturing process; sigmaCIndicating the alignment tolerance between the LED and the first bridging structure;
dcontact1 represents the minimum width of the N electrode electrically connected to the first bridging structure.
Similarly, in order to ensure the electrical connection performance between the second bridge electrode and the P electrode, the width W2 of the electrical connection region between the bottom surface of the P electrode (i.e., the surface of the P electrode facing the array substrate) and the second bridge electrode satisfies the following relationship:
W2≥∣σA∣+∣σB∣+∣σC∣+Dcontact2；
wherein σARepresenting the process error of the LED electrode in the plane direction parallel to the array substrate during the manufacturing process; sigmaBRepresenting the process error of the first bridging structure in the plane direction parallel to the array substrate during the manufacturing process; sigmaCIndicating the alignment tolerance between the LED and the first bridging structure;
dcontact2 represents the minimum width of the P-electrode electrically connected to the first bridging structure.
On the basis of any one of the above embodiments, in one embodiment of the present application, in order to ensure electrical insulation between the P electrode and the N electrode in the LED, a width d of a distance between the P electrode and the N electrode in the LED satisfies the following relationship:
d≥∣σA∣+∣σB∣+∣σC∣+Dins；
wherein σARepresenting the process error of the LED electrode in the plane direction parallel to the array substrate during the manufacturing process; sigmaBRepresenting the process error of the first bridging structure in the plane direction parallel to the array substrate during the manufacturing process; sigmaCIndicating the alignment tolerance between the LED and the first bridging structure; dins represents the minimum width of the LED when the first bridge electrode is insulated from the P electrode, or the minimum width of the LED when the second bridge electrode is insulated from the N electrode.
On the basis of any of the above embodiments, in an embodiment of the present application, as shown in fig. 4, the display panel further includes: a planarization layer 50, the planarization layer 50 being located between the plurality of LEDs 20 and the array substrate 10, the planarization layer 50 having a plurality of first grooves and a plurality of second grooves therein, the first bridge electrode 31 being located in the first grooves, the second bridge electrode 32 being located in the second grooves to accommodate the first bridge structures 30 in the planarization layer 50, but the present application is not limited thereto, as the case may be.
On the basis of any of the above embodiments, in an embodiment of the present application, as shown in fig. 5, the first bridging region 301 and the second bridging region 302 of the first bridging structure 30 are arranged along a first direction C, the first direction C is parallel to the plane where the array substrate 10 is located, and the first direction C is parallel to the directions of the P electrode 222 to the N electrode 221 of the LED, so as to reduce the size of the first bridging structure 30 in a second direction D, so that the display panel is provided with more LEDs in the second direction D, and pixel points of the display panel in the second direction D are increased. The second direction is parallel to the plane of the array substrate and is intersected with the first direction. Optionally, the second direction is perpendicular to the first direction, but this is not limited in this application, as the case may be.
In another embodiment of the present application, as shown in fig. 6, the first bridge area 301 and the second bridge area 302 of the first bridge structure 30 are arranged along a second direction D, wherein the first direction C and the second direction D are parallel to the plane of the array substrate 10, the first direction C is parallel to the P-electrode 222 to N-electrode 221 directions of the LEDs, and the first direction C intersects with the second direction D to reduce the size of the first bridge structure 30 in the first direction C, so that the display panel can be provided with more LEDs in the first direction C, and pixel points of the display panel in the first direction C can be increased. However, the present application is not limited thereto, as the case may be.
On the basis of any one of the above embodiments, in an embodiment of the present application, the electrode of the LED includes: the P electrode is positioned on the surface of the P type semiconductor layer in the light emitting layer and is electrically connected with the P type semiconductor layer of the light emitting layer, and the N electrode is positioned on the surface of the N type semiconductor layer in the light emitting layer and is electrically connected with the N type semiconductor layer in the light emitting layer; in the embodiment of the present application, as shown in fig. 7, the LED further includes: the first protective layer 23 is located on the side surface of the light emitting layer 21 and covers the side surface of the light emitting layer 21 to protect the side surface of the light emitting layer 21, so that damage to the side surface of the light emitting layer 21 in the manufacturing process of the first bridging structure is avoided. Optionally, the first protection layer 23 further covers a part of the surfaces of the P-type semiconductor layer and the N-type semiconductor layer, but this is not limited in this application, and is determined as the case may be.
It should be noted that, in the embodiment of the present application, in the direction perpendicular to the plane of the array substrate, the first protection layer, the N electrode, and the P electrode may overlap, as shown in fig. 7, that is, the first protection layer 23 extends to a partial region between the N electrode 221 and the light emitting layer 21 and a partial region between the bottom surface of the P electrode 222 and the light emitting layer 21, or may not overlap, as shown in fig. 8, that is, the first protection layer 23 only covers the side surface of the light emitting layer 21 and a partial surface of the N-type semiconductor layer in the light emitting layer 21.
Optionally, as shown in fig. 7 and 8, when the LED further includes an intrinsic semiconductor layer 24 on a side of the light emitting layer 21 facing away from the electrode 22, the first protective layer 23 further covers a side surface of the intrinsic semiconductor layer 24.
It should be further noted that even if the side surface of the light emitting layer is protected by the first protection layer, when the forming process of the first bridge structure adopts a dry etching process, the dry etching process may also etch the first protection layer, so as to increase the probability of damage to the side surface of the light emitting layer.
It should be further noted that, since the first bridge structure is located on a side of the LED electrode facing away from the light emitting layer when the first bridge structure is manufactured, in order to avoid the failure of the LED electrode caused by the manufacturing process of the first bridge structure, in an embodiment of the present application, a manufacturing material of the LED electrode includes a metal that cannot be etched by a wet etching process. Optionally, in an embodiment of the present application, a material of the electrode of the LED includes gold, for example, a material of the P electrode includes gold, and a material of the N electrode includes gold, so as to prevent the electrical connection performance between the first bridging structure and the electrode of the LED from being affected due to failure of the electrode of the LED caused by a manufacturing process of the first bridging structure.
Optionally, in an embodiment of the present application, when the electrode of the LED includes other metal materials in addition to gold, the gold material layer is an outer surface layer of the electrode, so as to protect the other metal material layers of the LED electrode.
On the basis of any one of the above embodiments, in an embodiment of the present application, a process adopted in the manufacturing of the second bridge structure is a dry etching process, and a material selective etching ratio of the second bridge structure to the first bridge structure is greater than 2, that is, an etching rate of the second bridge structure is greater than 2 times of an etching rate of the first bridge structure, so as to reduce damage to the first bridge structure in a process of forming the second bridge structure. However, the present application is not limited thereto, as the case may be.
On the basis of any one of the above embodiments, in an embodiment of the present application, the display panel further includes: the LED display panel comprises a plurality of cathodes and a common cathode connecting wire electrically connected with the plurality of cathodes, so that one end of the plurality of LEDs electrically connected with the cathodes can transmit signals through one signal wire, and the number of the signal wires in the display panel is reduced.
On the basis of the foregoing embodiments, in an embodiment of the present application, the second bridging structure and the common cathode connection line in the display panel are located in the same layer, so as to reduce the thickness of the display panel, which is beneficial for the development of the lightness and thinness of the display panel.
On the basis of any one of the above embodiments, in an embodiment of the present application, as shown in fig. 9, the display panel further includes:
the protection structures 60 are located on the side, away from the array substrate 10, of the first bridge structure, the protection structures 60 correspond to the LEDs 20 one to one, a first through hole is formed in the protection structure 60, and the LED20 is located in the first through hole, so that the protection structure 60 is arranged around the LEDs 20;
and a second protective layer 70 covering the protective structure 60 and the LEDs 20, wherein a refractive index of the second protective layer 70 is smaller than a refractive index of the protective structure 60, so that light rays emitted from the side surface of the LED20 to the protective structure 60 are totally reflected at an interface between the protective structure 60 and the second protective layer 70, reflected back to the upper LED20, and finally emitted from a side of the LED20 away from the array substrate 10, thereby improving the light extraction efficiency of the display panel.
It should be noted that, in the embodiment of the present application, in a direction perpendicular to the plane of the array substrate 10, a cross-sectional view of the protection structure 60 is an inverted trapezoid, where the cross-sectional view of the protection structure is an inverted trapezoid, where the fact that the cross-sectional view of the protection structure is an inverted trapezoid means that, in the direction perpendicular to the plane of the array substrate, a side length of a side of the cross-sectional view of the protection structure facing away from the array substrate is greater than a side length of a side of the cross-sectional view of the protection structure close to the array substrate.
It should be noted that the display panel provided in the embodiment of the present application may be a frameless display panel, a flexible display panel, a transparent display panel, or any other display panel.
Correspondingly, as shown in fig. 10, an embodiment of the present application further provides a display device, including the display panel provided in any of the above embodiments, and optionally, the display device may be a device with a display function, such as a mobile phone, a computer, a television, and the like, which is not limited in this application, and is determined as the case may be.
In addition, an embodiment of the present application further provides a manufacturing method of a display panel, as shown in fig. 11, the manufacturing method includes:
s1: providing a first substrate, and forming a plurality of LEDs on a first side of the first substrate, wherein the LEDs comprise a light-emitting layer and an electrode positioned on one side of the light-emitting layer, which is far away from the first substrate.
Optionally, in an embodiment of the present application, the first substrate is a glass substrate, and forming the plurality of LEDs on the first side of the first substrate includes:
s11: as shown in fig. 12, a plurality of LEDs 20 are formed on a sapphire substrate 80, and the LED20 includes a light-emitting layer and an electrode electrically connected to the light-emitting layer.
In one embodiment of the present application, forming a plurality of LEDs on a sapphire substrate includes:
forming a plurality of light emitting layers on a sapphire substrate;
and forming an electrode electrically connected with the light-emitting layer on the side of the light-emitting layer, which is far away from the sapphire substrate.
Specifically, in one embodiment of the present application, as shown in fig. 12, the light emitting layer includes an N-type semiconductor layer 211, a quantum well layer 212, and a P-type semiconductor layer 213, which are stacked, wherein the stacked structure formed by the quantum well layer 212 and the P-type semiconductor layer 213 exposes a portion of the surface of the N-type semiconductor layer 211; the electrodes of the LED include an N electrode 221 and a P electrode 222, the N electrode 221 is located on the surface of the N-type semiconductor layer 211 and electrically connected to the N-type semiconductor layer 211, and the P electrode 222 is located on the surface of the P-type semiconductor layer 213 and electrically connected to the P-type semiconductor layer 213.
Optionally, in an embodiment of the present application, the N-type semiconductor layer is an N-type doped GaN layer, the P-type semiconductor layer is a P-type doped GaN layer, and the quantum well layer is an InGaN multi-quantum well layer.
On the basis of the above embodiments, in one embodiment of the present application, the LED further includes: an intrinsic semiconductor layer 24, such as an intrinsic GaN layer, on the side of the light-emitting layer facing away from the electrode. Wherein, intrinsic semiconductor layer includes buffer layer, low temperature semiconductor layer and high temperature semiconductor layer, wherein, the buffer layer deviates from luminous layer side surface has the arch, in order to improve LED's luminous efficiency, high temperature semiconductor layer is used for improving the planar roughness is formed to the luminous layer, low temperature semiconductor layer does the buffer layer with transition layer between the high temperature semiconductor layer is regarded as simultaneously the sapphire substrate with lattice constant transition layer between the luminous layer improves the growth quality of luminous layer, in other embodiments of this application, LED can also include other structures, and this application does not limit to this, and is specifically contingent on the circumstances.
Specifically, in an embodiment of the present application, taking the semiconductor layer as a GaN layer as an example, the forming a plurality of LEDs on a sapphire substrate includes:
carrying out patterning treatment on the surface of the sapphire substrate so as to enable the surface of the sapphire substrate to be provided with a plurality of grooves;
forming an intrinsic GaN layer, i.e., an undoped GaN layer, on a surface of the sapphire substrate on a side having the grooves such that the intrinsic GaN layer has a plurality of protrusions toward the sapphire substrate side;
forming an N-type GaN layer on one side of the intrinsic GaN layer, which is far away from the sapphire substrate;
forming an InGaN multi-quantum well layer on the side, away from the intrinsic GaN layer, of the N-type GaN layer;
forming a P-type GaN layer on the side of the InGaN multi-quantum well layer, which faces away from the N-type GaN layer;
etching a plurality of regions of the P-type GaN layer and the InGaN multi-quantum well layer to expose the partial surface of the N-type GaN layer;
cutting the N-type GaN layer and the intrinsic GaN layer to form a plurality of independent light emitting layers;
and forming an N electrode electrically connected with the N-type GaN layer and a P electrode electrically connected with the P-type GaN layer on one side of the light-emitting layer, which is far away from the sapphire substrate.
On the basis of any of the above embodiments, in an embodiment of the present application, as shown in fig. 12, the LED further includes: and the first protective layer 23 is positioned on the side surface of the light-emitting layer and covers the side surface of the light-emitting layer, so that the side surface of the light-emitting layer is prevented from being damaged in the subsequent process. Specifically, in the present embodiment, forming a plurality of LEDs on a sapphire substrate includes:
forming a plurality of light emitting layers on a sapphire substrate;
forming a first protective layer on the surface and the side face of the light-emitting layer;
removing at least partial region of the first protection layer on the surface of the N-type semiconductor layer in the light emitting layer and at least partial region of the surface of the P-type semiconductor layer in the light emitting layer;
and forming an N electrode in a region of the N-type semiconductor layer which is not covered by the first protective layer, and forming a P electrode in a region of the P-type semiconductor layer which is not covered by the first protective layer.
Optionally, the first protection layer is a silicon dioxide layer, but the application does not limit this, as the case may be.
Specifically, on the basis of any one of the above embodiments, in an embodiment of the present application, the LED is a Micro LED or a Mini LED.
S12: as shown in fig. 13, a second substrate 81 is provided, and an alignment layer (not shown in the figure) and an adhesive layer 82 are sequentially formed on the second substrate 81, optionally, the second substrate is a glass substrate, wherein the alignment layer is used for positioning a placement position of an LED when the LED is transferred subsequently, and the adhesive layer is used for fixedly connecting the LED and the second substrate after the LED is transferred subsequently.
S13: continuing with fig. 13, the plurality of LEDs 20 on the sapphire substrate are transferred to the side of the adhesive layer 82 facing away from the second base plate 81, and the sapphire substrate 80 is removed.
Optionally, in an embodiment of the present application, the plurality of LEDs on the sapphire substrate are transferred to a side of the adhesive layer facing away from the second base plate by using a laser lift-off technology, but the present application does not limit this, and in other embodiments of the present application, other technologies may also be used to transfer the plurality of LEDs on the sapphire substrate to a side of the adhesive layer facing away from the second base plate, as the case may be.
S14: as shown in fig. 14, a second solid crystal layer 84 is formed on the first substrate 83, and the second solid crystal layer 84 is a non-solid state, and optionally, in an embodiment of the present application, the second solid crystal layer is a transparent flexible layer, such as a polyimide layer, but the present application is not limited thereto, as the case may be.
It should be noted that, in the embodiment of the present application, before the second die attach layer is formed on the first substrate, an alignment layer may be formed on the first substrate, so that when the LED on the second substrate is transferred onto the first substrate, the alignment accuracy between the second substrate and the first substrate is improved. Optionally, the alignment layer on the first substrate is an annular metal layer, and the annular metal layer may be annularly disposed on one side of the second die attach layer close to the first substrate, and may also be located on the same layer as the second die attach layer corresponding to an edge area of the second die attach layer, and is annularly disposed around the second die attach layer.
S15: continuing with fig. 14, transferring the plurality of LEDs 20 on the second substrate 81 to a side of the second solid crystal layer 84 facing away from the first substrate 83, and curing the second solid crystal layer 84, as shown in fig. 15, removing the second substrate 81 to realize the transfer of the plurality of LEDs 20.
It should be noted that, in practical applications, the display panel may include LEDs of one color, and may also include LEDs of multiple colors. A process of forming a plurality of LEDs on the first side of the first substrate will be described below, taking the display panel including LEDs of three colors as an example.
Specifically, in one embodiment of the present application, the forming of the plurality of LEDs on the first substrate includes:
forming a plurality of first color LEDs on a first sapphire substrate;
forming a plurality of second color LEDs on a second sapphire substrate;
forming a plurality of third color LEDs on a third sapphire substrate;
sequentially forming an alignment layer and an adhesive layer on the second substrate;
transferring the plurality of first color LEDs on the first sapphire substrate to the side of the bonding layer away from the second base plate, and removing the first sapphire substrate;
transferring a plurality of second color LEDs on the second sapphire substrate to the side of the bonding layer away from the second base plate, and removing the second sapphire substrate;
transferring a plurality of third color LEDs on the third sapphire substrate to the side of the bonding layer away from the second base plate, and removing the third sapphire substrate;
forming a second solid crystal layer on the first substrate, wherein the second solid crystal layer is in an amorphous state;
and transferring the LEDs with the multiple colors on the second substrate to the side, away from the first substrate, of the second die bonding layer, curing the second die bonding layer, and removing the second substrate.
It should be noted that, the LEDs of different colors have different thicknesses in the direction perpendicular to the plane of the array substrate, and optionally, when the LEDs of multiple colors are formed on the second substrate, the LEDs with a larger thickness are transferred first, and then the LEDs with a smaller thickness are transferred, so that the difficulty in transferring the LEDs of different colors to the second substrate is reduced.
Specifically, in an embodiment of the present application, the display panel includes: and the first color is red, the second color is green, and the third color is blue, namely the red LED is firstly transferred to the second substrate, then the green LED is transferred to the second substrate, and finally the blue LED is transferred to the second substrate.
It should be noted that, when the LEDs of different colors are transferred to the second substrate and then the LEDs on the second substrate are transferred to the first substrate, all the LEDs are simultaneously transferred to the first substrate, that is, all the LEDs on the second substrate are transferred to the first substrate in the same step process, so as to improve the transfer efficiency of the LEDs transferred to the first substrate.
S2: as shown in fig. 16, a plurality of first bridge structures 30 are formed on a side of the plurality of LEDs 20 facing away from the first substrate 83, the first bridge structures 30 include a first bridge region and a second bridge region, the second bridge region does not overlap with the LEDs 20 in a direction perpendicular to a plane of the first substrate 83, and the electrodes of the LEDs 20 are electrically connected to the first bridge regions of the first bridge structures 30.
Optionally, in an embodiment of the application, a wet etching process is used in a process for forming the first bridge structure, so as to prevent the first protective layer from being etched away when the first bridge structure is etched by a dry etching method, and damage is caused to a side surface of the light emitting layer.
Specifically, in an embodiment of the present application, forming a plurality of first bridge structures on a side of the plurality of LEDs facing away from the first substrate includes:
forming a first bridging metal layer on one side of the LEDs, which faces away from the first substrate;
and carrying out wet etching on the first bridging metal to form a plurality of first bridging structures.
It should be noted that, on the basis of reducing the probability of damage to the light emitting layer caused by the first bridge structure forming process, in order to avoid damage to the electrode of the LED caused by the first bridge structure forming process, the electrode of the LED is made of an acid-resistant metal material, that is, a metal that is not easily corroded by a wet etching process. Optionally, in an embodiment of the present application, the material of the electrode of the LED includes gold, but the present application does not limit this, and in other embodiments of the present application, the material of the electrode of the LED may also include other acid-resistant metal materials, as the case may be.
As can be seen from the above, the process of transferring the plurality of LEDs onto the first substrate includes two processes of transferring the plurality of LEDs from the sapphire substrate onto the second substrate and from the second substrate onto the first substrate, and therefore, in the present embodiment, the alignment tolerance σ between the LEDs and the first bridging structureCThe method comprises the following steps: the alignment tolerance of the LED on the sapphire substrate transferred to the second substrate and the alignment tolerance of the LED on the second substrate transferred to the first substrate.
S3: as shown in fig. 17, the LEDs 20 and the first bridge structures 30 are transferred onto the array substrate 10, as shown in fig. 18, and the first substrate 83 is removed, the electrodes of the LEDs 20 are located on the side of the light-emitting layer close to the array substrate 10, and the first bridge structures 30 are located between the electrodes of the LEDs 20 and the array substrate 10.
Optionally, in an embodiment of the present application, transferring the plurality of LEDs and the plurality of first bridging structures to the first side of the array substrate includes:
continuing to refer to fig. 18, a first solid crystal layer 85 is formed on the first side of the array substrate, and the first solid crystal layer 85 is in a non-solid state;
transferring the plurality of LEDs 20 and the plurality of first bridging structures 30 to a first side of the array substrate 10;
the first solid crystal layer 85 is cured.
It should be noted that, in the embodiment of the present application, the materials of the first solid crystal layer and the second solid crystal layer may be the same or different, as the case may be.
S4: and a second bridging structure is formed on one side of the first bridging structure, which is deviated from the array substrate, and is electrically connected with a second bridging area of the first bridging structure, and the second bridging structure is electrically connected with the array substrate through a through hole, so that the electrodes of the LEDs are electrically connected with the array substrate through the first bridging structure and the second bridging structure in sequence, and a huge transfer bonding process is not needed, thereby avoiding the phenomenon of stress accumulation inside the display panel caused by introducing the huge transfer bonding process, and improving the stability of the display panel.
As can be seen from the foregoing, the forming process of the first bridge structure adopts a wet etching process, and therefore, in an optional embodiment of the present application, the forming process of the second bridge structure is a dry etching process, so as to reduce damage to the first bridge structure in the manufacturing process of the second bridge structure.
Specifically, in an embodiment of the present application, the second bridge structure is electrically connected to the pixel circuit in the array substrate through a via hole, in this embodiment, a second bridge structure is formed on a side of the first bridge structure away from the array substrate, the second bridge structure is electrically connected to the second bridge area of the first bridge structure, and the second bridge structure is electrically connected to the array substrate through a via hole, including:
as shown in fig. 19, removing a first portion of the second solid crystal layer 84, leaving a second portion of the second solid crystal layer 84, and forming a plurality of second vias in the second solid crystal layer 84, wherein the second vias expose at least a second bridge region of the first bridge structure 30 and a region between adjacent first bridge structures 30;
as shown in fig. 20, removing a portion of the first solid crystal layer 85, forming a via hole 86 in the first solid crystal layer 85, wherein the via hole 85 exposes a region of the array substrate 10 where the pixel circuit is electrically connected to the second bridge structure;
as shown in fig. 21, a second bridge structure 40 is formed on a side of the first bridge structure 30 away from the array substrate 10, and the second bridge structure 40 is electrically connected to the second bridge region of the first bridge structure 30 and electrically connected to the pixel circuit in the array substrate 10 through a via hole.
As can be seen from the above process, the second through hole and the via hole are formed in different processes, and in a direction parallel to the plane of the array substrate, the cross-sectional area of the second through hole is much larger than that of the via hole, so as to avoid that the first solid crystal layer is also removed in the process of forming the second through hole, on the basis of the embodiment of the present application, in an embodiment of the present application, an etching selectivity of the second solid crystal layer to the first solid crystal layer is greater than 2, that is, under the process condition of forming the second through hole, the etched rate of the second solid crystal layer is greater than twice the etched rate of the first solid crystal layer, but the present application does not limit this, depending on the situation.
In an embodiment of the application, if the forming process of the second bridge structure is a dry etching process, and the difference between the etching selectivity of the second solid crystal layer and the etching selectivity of the first solid crystal layer is not greater than 2, the method further includes, before transferring the plurality of LEDs and the plurality of first bridge structures to the first side of the array substrate: as shown in fig. 22 and 23, a planarization layer 50 is formed on a side of the first bridge structure 30 facing away from the LED20, so that the first solid crystal layer 85 is protected by the planarization layer 50 during the formation of the second through hole. It should be noted that, in the embodiment of the present application, the planarization layer has a plurality of first grooves and a plurality of second grooves, the first bridge electrode is located in the first grooves, and the second bridge electrode is located in the second grooves.
On the basis of any of the above embodiments, in an embodiment of the present application, the second through hole is a trapezoidal through hole, and the method further includes: as shown in fig. 24, a second passivation layer 70 covering the second solid crystal layer 84 and the LEDs 20 is formed, and a refractive index of the second passivation layer 70 is smaller than a refractive index of the second solid crystal layer 84, so that light emitted from the side of the LED20 toward the second solid crystal layer 84 is totally reflected at an interface between the second solid crystal layer 84 and the second passivation layer 70, reflected back to the LEDs, and finally emitted from a side of the LEDs away from the array substrate, thereby improving the light extraction efficiency of the display panel.
It should be noted that, in the embodiment of the present application, in a direction perpendicular to a plane of the array substrate, the second through hole is an inverted trapezoidal through hole, that is, a side length of the second through hole on a side away from the array substrate is greater than a side length of the second through hole on a side close to the array substrate.
To sum up, in the display panel and the manufacturing method thereof provided by the embodiment of the present application, the LED electrode is electrically connected to the first bridging area of the first bridging structure, the second bridging structure is electrically connected to the second bridging area of the first bridging structure, and the second bridging structure is electrically connected to the array substrate, so that the LED electrode sequentially passes through the first bridging structure and the second bridging structure to be electrically connected to the array substrate, and a bulk transfer bonding process is not required, thereby avoiding a phenomenon of stress accumulation inside the display panel caused by introducing the bulk transfer bonding process, improving the stability of the display panel, facilitating the realization of a large-size Micro/Mini LED display panel, and further improving the yield of the display panel.
All parts in the specification are described in a mode of combining parallel and progressive, each part is mainly described to be different from other parts, and the same and similar parts among all parts can be referred to each other.
In the above description of the disclosed embodiments, features described in various embodiments in this specification can be substituted for or combined with each other to enable those skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (21)

1. A display panel, comprising:
an array substrate;
the LEDs are positioned on the first side of the array substrate and comprise light-emitting layers and electrodes positioned on one sides, close to the array substrate, of the light-emitting layers;
a plurality of first bridge structures, each of the first bridge structures including a first bridge region and a second bridge region, and the second bridge regions do not overlap with the LEDs in a direction perpendicular to a plane of the array substrate;
the second bridge structures are electrically connected with the array substrate, and in the direction perpendicular to the plane of the array substrate, the second bridge structures and the electrodes of the LEDs are positioned on the same side of the first bridge structures;
wherein the electrodes of the LED are electrically connected to the first bridge region of the first bridge structure, and the second bridge structure is electrically connected to the second bridge region of the first bridge structure.
2. The display panel according to claim 1, wherein the first bridge structure comprises a first bridge electrode and a second bridge electrode, the first bridge region comprises a first bridge region of the first bridge electrode and a first bridge region of the second bridge electrode, and the second bridge region comprises a second bridge region of the first bridge electrode and a second bridge region of the second bridge electrode;
the first bridging area of the first bridging electrode is electrically connected with the N electrode of the LED, and the first bridging area of the second bridging electrode is electrically connected with the P electrode of the LED;
the second bridge structure comprises a third bridge electrode and a fourth bridge electrode, the third bridge electrode is electrically connected with the second bridge area of the first bridge electrode, and the fourth bridge electrode is electrically connected with the second bridge area of the second bridge electrode.
3. The display panel of claim 1, wherein the first bridge structure at least partially overlaps the LED electrode in a direction perpendicular to a plane of the array substrate; and in the direction parallel to the plane of the array substrate, the first bridging structure and the LED electrode are at least partially overlapped.
4. The display panel according to claim 3, wherein in a direction perpendicular to a plane of the array substrate, an overlapping area of the first bridge structure and the N electrode of the LED is smaller than an overlapping area of the first bridge structure and the P electrode of the LED, and in a direction parallel to the plane of the array substrate, an overlapping area of the first bridge structure and the N electrode of the LED is larger than an overlapping area of the first bridge structure and the P electrode of the LED.
5. The display panel according to claim 2, further comprising:
the planarization layer is located between the LEDs and the array substrate, the planarization layer is provided with a plurality of first grooves and a plurality of second grooves, the first bridging electrodes are located in the first grooves, and the second bridging electrodes are located in the second grooves.
6. The display panel according to claim 1, wherein the first bridge region and the second bridge region of the first bridge structure are arranged along a first direction, or the first bridge region and the second bridge region of the first bridge structure are arranged along a second direction;
the first direction and the second direction are parallel to the plane of the array substrate, the first direction is parallel to the direction from the P electrode to the N electrode of the LED, and the first direction and the second direction are crossed.
7. The display panel according to claim 1, wherein the electrodes of the LEDs comprise: the surface of the P-type semiconductor layer in the light emitting layer is electrically connected with the P-type semiconductor layer in the light emitting layer, and the surface of the N-type semiconductor layer in the light emitting layer is electrically connected with the N-type semiconductor layer in the light emitting layer;
the LED further includes: and the first protective layer is positioned on the side surface of the light-emitting layer and covers the side surface of the light-emitting layer.
8. The display panel according to claim 7, wherein the material of the P electrode comprises gold, and the material of the N electrode comprises gold.
9. The display panel according to claim 1, characterized in that the display panel further comprises: the second bridging structure and the common cathode connecting line in the display panel are positioned on the same layer.
10. The display panel according to claim 1, further comprising:
the protection structures are positioned on one side, away from the array substrate, of the first bridging structure, the protection structures correspond to the LEDs one to one, first through holes are formed in the protection structures, and the LEDs are positioned in the first through holes;
a second protective layer covering the protective structure and the LED, the second protective layer having a refractive index less than a refractive index of the protective structure.
11. The display panel according to claim 1, wherein an etching selection ratio of a material of the second bridge structure to a material of the first bridge structure is greater than 2.
12. A method for manufacturing a display panel is characterized by comprising the following steps:
providing a first substrate, and forming a plurality of LEDs on a first side of the first substrate, wherein the LEDs comprise a light-emitting layer and an electrode positioned on one side of the light-emitting layer, which is far away from the first substrate;
forming a plurality of first bridging structures on the side, away from the first substrate, of the plurality of LEDs, wherein each first bridging structure comprises a first bridging area and a second bridging area, the second bridging areas are not overlapped with the LEDs in the direction perpendicular to the plane of the first substrate, and the LED electrodes are electrically connected with the first bridging areas of the first bridging structures;
transferring the LEDs and the first bridging structures onto an array substrate, and removing the first substrate, wherein the electrodes of the LEDs are positioned on one side of the light-emitting layer close to the array substrate, and the first bridging structures are positioned between the electrodes of the LEDs and the array substrate;
and forming a second bridging structure on one side of the first bridging structure, which is far away from the array substrate, wherein the second bridging structure is electrically connected with the second bridging area of the first bridging structure, and the second bridging structure is electrically connected with the array substrate through a through hole.
13. The method of claim 12, wherein transferring the plurality of LEDs and the plurality of first bridging structures to the first side of the array substrate comprises:
forming a first fixed crystal layer on the first side of the array substrate, wherein the first fixed layer is non-solid;
transferring the plurality of LEDs and the plurality of first bridging structures to a first side of the array substrate;
and solidifying the first die bonding layer.
14. The method of manufacturing according to claim 13, wherein forming a plurality of first bridge structures on a side of the plurality of LEDs facing away from the first substrate comprises:
forming a first bridging metal layer on one side of the LEDs, which faces away from the first substrate;
and carrying out wet etching on the first bridging metal to form a plurality of first bridging structures.
15. The method of manufacturing of claim 14, wherein forming the plurality of LEDs on the first side of the first substrate comprises:
forming a plurality of LEDs on a sapphire substrate;
providing a second substrate, and sequentially forming an alignment layer and an adhesive layer on the second substrate;
transferring the plurality of LEDs on the sapphire substrate to the side, away from the second base plate, of the bonding layer, and removing the sapphire substrate;
forming a second solid crystal layer on the first substrate, wherein the second solid crystal layer is in an amorphous state;
and transferring the LEDs on the second substrate to one side of the second die bonding layer, which is far away from the first substrate, curing the second die bonding layer, and removing the second substrate.
16. The method of manufacturing according to claim 15, wherein forming a plurality of LEDs on a sapphire substrate comprises:
forming a plurality of light emitting layers on a sapphire substrate;
forming a first protective layer on the surface and the side face of the light-emitting layer;
removing at least partial region of the first protective layer on the surface of the N-type layer in the light-emitting layer and at least partial region of the surface of the P-type layer in the light-emitting layer;
and forming an N electrode in the area of the N-type layer not covered by the first protective layer, and forming a P electrode in the area of the P-type layer not covered by the first protective layer.
17. The manufacturing method according to claim 14, wherein the forming process of the second bridge structure is a dry etching process, and an etching selection ratio of the second solid crystal layer to the first solid crystal layer is greater than 2.
18. The manufacturing method according to claim 14, wherein the forming process of the second bridge structure is a dry etching process, and the difference between the etching selectivity of the second solid crystal layer and the etching selectivity of the first solid crystal layer is not greater than 2, and the method further comprises, before transferring the plurality of LEDs and the plurality of first bridge structures to the first side of the array substrate:
and forming a planarization layer on one side of the first bridging structure, which faces away from the LED, wherein the planarization layer is provided with a plurality of first grooves and a plurality of second grooves, the first bridging electrode is positioned in the first grooves, and the second bridging electrode is positioned in the second grooves.
19. The method for manufacturing the array substrate of claim 14, wherein forming the second bridge structure on a side of the first bridge structure facing away from the array substrate comprises:
removing a first part of the second solid crystal layer, reserving a second part of the second solid crystal layer, and forming a plurality of second through holes in the second solid crystal layer, wherein the second through holes at least expose a second bridging area of the first bridging structure and an area between adjacent first bridging structures;
forming a via hole in the first solid crystal layer, wherein the via hole exposes a region of the pixel circuit in the array substrate, which is used for being electrically connected with the second bridging structure;
and forming a second bridging structure on one side of the first bridging structure, which is far away from the array substrate, wherein the second bridging structure is electrically connected with the second bridging area of the first bridging structure and is electrically connected with the pixel circuit in the array substrate through a via hole.
20. The method of manufacturing of claim 19, wherein the second via is a trapezoidal via, the method further comprising:
and forming a second protective layer covering the second solid crystal layer and the LED, wherein the refractive index of the second protective layer is smaller than that of the second solid crystal layer.
21. A display device characterized by comprising the display panel according to any one of claims 1 to 11.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190115370A1 (en) * 2018-07-26 2019-04-18 Shanghai Tianma Micro-electronics Co., Ltd. Array substrate, method for manufacturing array substrate, and display panel
US20190165035A1 (en) * 2018-09-20 2019-05-30 Shanghai Tianma Micro-Electronics Co.,Ltd. Display panel and method for manufacturing display panel
US20190181317A1 (en) * 2017-12-13 2019-06-13 Au Optronics Corporation Pixel array substrate and manufacturing method thereof
CN111864038A (en) * 2019-04-28 2020-10-30 陕西坤同半导体科技有限公司 Display panel, display device and preparation method of display panel
US20200410909A1 (en) * 2019-06-28 2020-12-31 Lg Display Co., Ltd. Stretchable display device
CN112928196A (en) * 2021-01-29 2021-06-08 厦门天马微电子有限公司 Display panel, manufacturing method thereof and display device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190181317A1 (en) * 2017-12-13 2019-06-13 Au Optronics Corporation Pixel array substrate and manufacturing method thereof
US20190115370A1 (en) * 2018-07-26 2019-04-18 Shanghai Tianma Micro-electronics Co., Ltd. Array substrate, method for manufacturing array substrate, and display panel
US20190165035A1 (en) * 2018-09-20 2019-05-30 Shanghai Tianma Micro-Electronics Co.,Ltd. Display panel and method for manufacturing display panel
CN111864038A (en) * 2019-04-28 2020-10-30 陕西坤同半导体科技有限公司 Display panel, display device and preparation method of display panel
US20200410909A1 (en) * 2019-06-28 2020-12-31 Lg Display Co., Ltd. Stretchable display device
CN112928196A (en) * 2021-01-29 2021-06-08 厦门天马微电子有限公司 Display panel, manufacturing method thereof and display device

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