CN113421873A - 晶片级无源器件的集成 - Google Patents

晶片级无源器件的集成 Download PDF

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Publication number
CN113421873A
CN113421873A CN202110695084.5A CN202110695084A CN113421873A CN 113421873 A CN113421873 A CN 113421873A CN 202110695084 A CN202110695084 A CN 202110695084A CN 113421873 A CN113421873 A CN 113421873A
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China
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semiconductor substrate
integrated circuit
metallization
substrate
coupled
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CN202110695084.5A
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English (en)
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翟军
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Apple Inc
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Apple Inc
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Publication of CN113421873A publication Critical patent/CN113421873A/zh
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Abstract

本公开涉及晶片级无源器件的集成。本公开描述了一种半导体器件，该半导体器件包括利用位于第一基板上的第一组无源器件(例如，电感器)(102)耦合到第一半导体基板(100)的集成电路(500)。第二半导体基板(200)可利用第二组无源器件(例如，电容器)(202)耦合到第一基板。基板中的互连器(104)可允许在基板和集成电路之间互连。无源器件可用于向集成电路提供电压调节。基板和集成电路可利用金属覆膜(106,502)来耦合。

Description

晶片级无源器件的集成
本申请是国际申请日为2015年8月4日、国家申请号为201580044816.7、发明名称为“晶片级无源器件的集成”的进入中国国家阶段的PCT申请的分案申请。
背景技术
1.技术领域
本文所述实施方案涉及用于实现半导体器件中电源调节的系统和方法。更具体地，本文所述实施方案涉及具有用于电压调节的集成无源器件的半导体器件。
2.相关领域的描述
电力传送与功率节省越来越成为片上系统(SoC)器件、中央处理单元(CPU)和图形处理单元(GPU)的集成电路器件性能调节的考虑因素。更快速地将电力传送至设备可提高设备的速度和功率，同时通过在功率转变(例如，设备的通电/断电)期间降低损耗来节省功率。在未开发出更高效的电力传送和功率节省系统或技术的情况下，进一步的性能调节可能是有限的。因此，针对进一步的性能调节正在开发用于在集成电路芯片上或附近包含电压调节部件(例如，无源器件，诸如电感器和/或电容器)的方法和系统。
已开发出的一种在集成电路芯片上集成电压调节的方法为在用于制造芯片的工艺期间在芯片上形成电压调节部件(例如，在用于形成集成电路的CMOS工艺期间形成电感器和电容器)。然而，在CMOS工艺期间形成电感器和电容器需要可能增加成本、额外处理时间、需更多掩模和/或更多器件的复杂过程。由于在CMOS工艺期间在集成电路芯片上形成电感器和电容器涉及的复杂性，因此这种集成电路芯片的产量损失可能很高，这就导致额外的制造时间和成本。另外，由于电感器和电容器是在CMOS工艺期间形成的，因此电感器和电容器的规格受限于CMOS工艺参数。
针对在集成电路芯片上或附近包含电压调节部件所开发的另一方法为通过集成电路芯片提供封装的分立电感器和电容器。然而，提供封装的电感器和电容器可能需要用于部件的大量固定空间，涉及困难的物理布线，并且在电力上无法应对电损耗。
发明内容
在某些实施方案中，半导体器件包括耦合到第一半导体基板的集成电路。集成电路和第一基板可利用形成在集成电路和第一基板上的金属覆膜(metallization)来耦合。第一基板可包括位于基板上的第一组无源器件(例如，电感器)。第二半导体基板可被耦合到第一基板，使得第一基板位于集成电路和第二基板之间。第一基板和第二基板可利用形成在第一基板和第二基板上的金属覆膜来耦合。第二基板可包括第二组无源器件(例如，电容器)。在一些实施方案中，电绝缘材料填充在集成电路和第一基板之间围绕金属覆膜以及在第一基板和第二基板之间围绕金属覆膜的空间。在某些实施方案中，基板包括提供基板和集成电路之间互连的互连器。这些互连器可连接无源器件和集成电路以提供用于集成电路的电压调节。
在一些实施方案中，将柱耦合到集成电路的位于第一基板和第二基板的周边上的有源表面。柱可提供到集成电路上输入/输出端子的直接连接。因此，来自集成电路的输入/输出可直接出现，而无需利用无源器件穿过基板进行布线。
附图说明
当与附图结合时，参考根据本公开所述实施例的目前优选的但仅为示例性的实施方案的以下详细描述，将更充分地理解本公开所述实施例的方法与装置的特征和优点，在该附图中：
图1示出了具有无源器件和互连器形成在其上的半导体基板的实施方案的横截面侧视图图示。
图2示出了具有无源器件和互连器形成在其上的半导体基板的另一实施方案的横截面侧视图图示。
图3示出了形成在半导体基板上的金属覆膜的实施方案的横截面侧视图图示。
图4示出了形成在半导体基板上的金属覆膜的另一实施方案的横截面侧视图图示。
图5示出了具有耦合到集成电路的金属覆膜的半导体基板的实施方案的横截面侧视图图示。
图6示出了耦合到集成电路的半导体基板的实施方案的横截面侧视图图示。
图7示出了耦合到集成电路的半导体基板的实施方案的横截面侧视图图示，其中电绝缘材料填充基板和集成电路之间间隙并且基板的一部分被移除。
图8示出了耦合到基板(该基板耦合到集成电路)的半导体基板的实施方案的横截面侧视图图示。
图9示出了耦合到基板(该基板耦合到集成电路)的半导体基板的实施方案的横截面侧视图图示，其中电绝缘材料填充基板之间的空间。
图10示出了半导体器件的实施方案的横截面侧视图图示。
图11示出了具有分隔线的半导体基板的实施方案的横截面侧视图图示。
图12示出了具有分隔线的半导体基板的另一实施方案的横截面侧视图图示。
图13示出了集成电路的实施方案的横截面侧视图图示，其中柱耦合到位于集成电路的周边部分上的金属覆膜。
图14示出了集成电路的实施方案的横截面侧视图图示，其中柱和半导体基板耦合到集成电路。
图15示出了集成电路的实施方案的横截面侧视图图示，其中柱和半导体基板耦合到集成电路并且基板的一部分和柱被移除。
图16示出了集成电路的实施方案的横截面侧视图图示，其中柱和半导体基板耦合到集成电路、另一半导体基板耦合到半导体基板并且柱延伸部耦合到柱。
图17示出了集成电路的实施方案的横截面侧视图图示，其中柱和半导体基板耦合到集成电路、另一半导体基板耦合到半导体基板并且柱延伸部耦合到由电绝缘材料包围的柱。
图18示出了集成电路的实施方案的横截面侧视图图示，其中柱和半导体基板耦合到集成电路、另一半导体基板耦合到半导体基板并且柱延伸部耦合到柱，其中另一半导体基板的一部分和柱延伸部被移除。
图19示出了半导体器件的另一实施方案的横截面侧视图图示。
尽管本公开所述的实施方案可受各种修改形式和替代形式的影响，但其具体实施方案在附图中以举例的方式示出并在本文详细描述。附图可能不是按比例的。应当理解，附图和对其的详细描述并非旨在将本发明限制于所公开的具体形式，相反，本发明旨在涵盖落入到所附权利要求的实质和范围内的所有修改形式、等价形式和替代形式。
具体实施方式
图1示出了具有无源器件和互连器形成在其上的半导体基板的实施方案的横截面侧视图图示。基板100可为半导体基板，诸如但不限于硅基板或硅晶片。在某些实施方案中，无源器件102形成在基板100上或该基板中。在某些实施方案中，无源器件102为电感器。例如，无源器件102可为薄膜电感器。
在某些实施方案中，互连器104形成于基板100中。互连器104可为形成于基板100中的填充有导电材料(例如，如铜之类的金属)的部分通路或其他三维互连器。例如，互连器104可为基板100中的铜柱或铜/焊锡柱。无源器件102和/或互连器104可在基板100中具有所选择的最大深度。所选择的最大深度可允许在随后的基板100处理期间使无源器件102和/或互连器104的部分暴露(例如，在移除基板的底部部分之后暴露)。
图2示出了具有无源器件和互连器形成在其上的半导体基板的另一实施方案的横截面侧视图图示。基板200可为半导体基板，诸如但不限于硅基板或硅晶片。在某些实施方案中，无源器件202形成在基板200上或该基板中。在某些实施方案中，无源器件202为电容器。例如，无源器件202可为沟道式电容器。
在某些实施方案中，互连器104形成于基板200中。无源器件202和/或互连器104可在基板200中具有所选择的最大深度。所选择的最大深度可允许在随后的基板200处理期间使无源器件202和/或互连器104的部分暴露(例如，在移除基板的底部部分之后暴露)。
图3示出了形成在基板100上的金属覆膜106的实施方案的横截面侧视图图示。图4示出了形成在基板200上的金属覆膜106的实施方案的横截面侧视图图示。在一些实施方案中，金属覆膜106包括图案化在基板100的表面和/或基板200的表面上的金属膜。例如，金属覆膜106可为图案化在基板100和/或基板200的表面上的铜。金属覆膜106可包括连接至无源器件102,202和/或互连器104的焊盘或其他端子。
在某些实施方案中，如图3所述，具有金属覆膜106的基板100利用金属覆膜耦合到集成电路。图5示出了具有耦合到集成电路500的金属覆膜106的基板100的横截面侧视图图示。集成电路500可包括但不限于片上系统(SoC)、图形处理单元(GPU)、中央处理单元(CPU)、协处理器、桥式处理器和利用电压调节的任何其他主要、次要或周边半导体处理器。例如，集成电路500可为功耗型半导体器件(例如，具有诸如SOC之类电流消耗元件的器件)。在某些实施方案中，使用CMOS(互补金属氧化物半导体)工艺形成集成电路500。然而，应当理解，可使用本领域中已知的其他工艺来形成集成电路500。
在某些实施方案中，金属覆膜502被形成在集成电路500上。金属覆膜502可耦合到集成电路500的表面504(例如，有源侧)。有源表面504可包括到集成电路500中有源电路的端子或连接部。在某些实施方案中，金属覆膜502具有对基板100上的金属覆膜106进行镜像的图案，如图5所示。
在某些实施方案中，集成电路500位于载体上。该载体可支持多个集成电路。在一些实施方案中，半导体基板100为半导体晶片，该半导体晶片的尺寸被设定成耦合到载体上的所有多个集成电路(例如，在晶片级工艺中，半导体(晶片)基板耦合到集成电路)。然后，在之后处理期间，半导体基板100(例如，半导体晶片)被分离(例如，切割)以形成不同器件。在晶片级过程中使多个集成电路500和半导体基板100耦合可提供高产量过程。
在一些实施方案中，半导体基板100和/或半导体基板200为不同地耦合到集成电路500的单独基板(例如，将半导体基板的尺寸设定成匹配集成电路)。不同的半导体基板可通过切割或以其他方式使半导体晶片分离来形成，以形成不同的半导体基板。然后，不同的半导体基板可耦合到单独的集成电路500(经由载体或脱离载体)。在某些实施方案中，由于不同的半导体基板耦合到单独的集成电路，因此可能仅允许耦合所产生的半导体基板和集成电路。仅耦合所产生的半导体基板和集成电路可提高本文所述过程的总产率。
图6示出了耦合到集成电路500的基板100的横截面侧视图图示。在某些实施方案中，如图6所示，基板100通过将金属覆膜106耦合到金属覆膜502来形成组合的金属覆膜506以耦合到集成电路。金属覆膜506可利用本领域中用于接合金属覆膜的已知技术来形成。例如，金属覆膜506可利用铜/焊锡/铜技术或铜柱技术来形成。
在某些实施方案中，在半导体基板100耦合到集成电路500之后，将电绝缘材料508填充到基板的上表面和集成电路的下(有源)表面之间的空间(间隙)，如图7所示。电绝缘材料508可填充半导体基板100和集成电路500之间围绕金属覆膜600的空间(间隙)。电绝缘材料508例如可为聚合物或环氧材料，诸如底部填充材料或封装材料。底部填充材料可包括但不限于倒装芯片结合工艺中所使用的毛细管底部填充材料，诸如快速固化底部填充材料或薄型底部填充材料。封装材料可包括但不限于聚合物或模具化合物，诸如重叠注塑或暴露注塑。
在某些实施方案中，如图7所示，将半导体基板100的(下)部移除。可例如通过利用本领域中已知的技术(例如，CMP(化学机械抛光)或磨削)减薄基板来移除半导体基板100的下部。在某些实施方案中，移除半导体基板100的下部使位于基板下表面上的至少一些互连器104暴露在外。在一些实施方案中，移除半导体基板100的下部使至少一些无源器件102和至少一些互连器104暴露在外。
在一些实施方案中，重新分布层(RDL)510位于基板100的下部。RDL 510可包括一个或多个布线层。布线例如可为铜线或将位于RDL 510一侧上的连接部重新分布到位于RDL另一侧上的其他经移动(例如，水平地移位)位置的其他适当电导线(例如，布线将位于RDL的顶部和底部的水平偏移的连接部(端子)互连)。因此，RDL 510可用于重新分布互连器104和/或无源器件102的连接部。
在一些实施方案中，RDL 510被制成半导体基板100的一部分并且在移除半导体基板的下部之后暴露在外。在一些实施方案中，在移除半导体基板的下部之后，RDL 510形成在半导体基板100的下表面上。
在某些实施方案中，在移除半导体基板100的下部之后，将金属覆膜512形成在半导体基板的下表面上，如图8所示。金属覆膜512可直接形成在半导体基板100的下表面或RDL 510的表面上(如图7所示)。在一些实施方案中，金属覆膜512可被制成RDL 510的一部分(例如，RDL包括在RDL下表面上的金属覆膜)。
金属覆膜512可用于将半导体基板100耦合到半导体基板200，如图8所示。在一些实施方案中，半导体基板200为半导体晶片，该半导体晶片的尺寸被设定成耦合到载体上的所有多个集成电路(例如，在晶片级工艺中，半导体(晶片)基板随半导体基板100一起耦合到集成电路)。在一些实施方案中，半导体基板200为不同地耦合到半导体基板100的单独基板(例如，将半导体基板的尺寸设定成匹配集成电路500)。
在某些实施方案中，将金属覆膜512耦合到位于半导体基板200上的金属覆膜106以形成组合的金属覆膜514，如图9所示。金属覆膜514可利用本领域中用于接合金属覆膜的已知技术来形成。在某些实施方案中，在半导体基板100耦合到半导体基板200之后，将电绝缘材料508填充到半导体基板100的下表面和半导体基板200的上表面之间的空间(间隙)，如图9所示。电绝缘材料508可填充半导体基板100和半导体基板200之间围绕金属覆膜514的空间(间隙)。
在某些实施方案中，如图10所示，将半导体基板200的(下)部移除。可例如通过利用本领域中已知的技术减薄基板来移除半导体基板200的下部。在某些实施方案中，移除半导体基板200的下部使位于基板下表面上的至少一些互连器104暴露在外。在一些实施方案中，移除半导体基板200的下部使至少一些无源器件202和至少一些互连器104暴露在外。
在一些实施方案中，重新分布层(RDL)520位于基板200的下部。RDL 520可用于重新分布互连器104和/或无源器件202的连接部。在一些实施方案中，RDL 520被制成半导体基板200的一部分并且在移除半导体基板的下部之后暴露在外。在一些实施方案中，在移除半导体基板的下部之后，将RDL 520形成在半导体基板200的下表面上。
在某些实施方案中，在移除半导体基板200的下部之后，将金属覆膜522形成在半导体基板的下表面上，如图10所示。金属覆膜522可直接形成在半导体基板200的下表面或RDL 520的表面上。在一些实施方案中，金属覆膜522可被制成RDL 520的一部分(例如，RDL包括在RDL下表面上的金属覆膜)。金属覆膜522可提供用于连接到半导体基板200、半导体基板100和/或集成电路500的端子。半导体基板200可直接耦合到金属覆膜522。集成电路500和半导体基板100可利用一个或多个互连器104(在两个基板中)和/或基板上的RDL耦合到金属覆膜522。金属覆膜522继而可用于将集成电路500、半导体基板100和/或半导体基板200耦合到例如另一器件、封装或印刷电路板。
在某些实施方案中，集成电路500、半导体基板100、半导体基板200和它们的中间部件形成半导体器件1000，如图10所示。对于本文所述的晶片级工艺，可通过从载体移除集成电路500并沿所选择边界分离(切割)包括用于半导体基板100和半导体基板200的半导体晶片等结构以形成包括独立集成电路的不同半导体器件，来形成半导体器件1000。在一些实施方案中，在分离(切割)期间，集成电路500仍保持在载体上，并且在分离(切割)之后从载体移除半导体器件1000。在一些实施方案中，可将半导体器件1000进一步处理为位于封装或其他结构中。
在某些实施方案中，将包括半导体基板100、半导体基板200的半导体晶片分离以形成具有比集成电路500宽度小的基板。图11示出了具有分隔线的半导体基板100的实施方案的横截面侧视图图示。图12示出了具有分隔线的半导体基板200的实施方案的横截面侧视图图示。在分离(切割)基板之前，金属覆膜106可形成在半导体基板100和半导体基板200上。如图11所示，分离半导体基板100可形成半导体基板100’。如图12所示，分离半导体基板200可形成半导体基板200’。
图13示出了集成电路500的实施方案的横截面侧视图图示，其中柱550耦合到位于集成电路的周边部分上的金属覆膜502。柱550可为例如铜柱或由其他适当导体制成的柱。柱550可利用电镀(例如，电镀铜)来制成。在某些实施方案中，柱550耦合到集成电路500的有源表面504上的输入/输出端子。有源表面504上未用于输入/输出的端子可用于到集成电路500的电力(电压)调节连接。柱550可具有的高度大于金属覆膜502。例如，在一个实施方案中，柱550具有约60μm的高度，而金属覆膜502具有约10μm的高度。
柱550可形成在周边部分以允许半导体基板100’位于周边部分的内部并在没有柱550的情况下连接到金属覆膜502，如图14所示。然后将柱550定位在半导体基板100’的周边。半导体基板100’可利用金属覆膜106和金属覆膜502耦合到集成电路500以形成本文所述的组合的金属覆膜506。由于半导体基板100’在耦合到柱550的集成电路的周边部分内耦合到集成电路500，因此基板不同地耦合到集成电路(例如，基板在单独流程级别而不是晶片级别流程中耦合)。
在将半导体基板100’耦合到集成电路500之后，将电绝缘材料508填充到基板的上表面和集成电路的下(有源)表面之间的空间(间隙)。电绝缘材料508还围绕半导体基板100’和柱550，如图14所示。
在某些实施方案中，如图15所示，将半导体基板100’、柱550和电绝缘材料508的下部移除。可例如通过利用本领域中已知的技术(例如，CMP或磨削)减薄基板来移除下部。在某些实施方案中，移除半导体基板100’的下部使位于基板下表面上的至少一些互连器104暴露在外。在一些实施方案中，移除半导体基板100’的下部使至少一些无源器件102和至少一些互连器104暴露在外。如图15所示，将柱550和电绝缘材料508减薄至与半导体基板100’相同的程度，其中柱的至少一部分暴露在电绝缘材料的表面上。在一些实施方案中，重新分布层(RDL)510位于基板100’的下部。
在某些实施方案中，在移除半导体基板100’、柱550和电绝缘材料508的下部之后，将柱延伸部550’耦合到柱550的剩余部分，如图16所示。柱延伸部550’可例如通过电镀来形成。柱延伸部550’可形成在半导体基板100’的周边。
在某些实施方案中，半导体基板200’在由柱550和柱延伸部550’形成的周边部分内耦合到半导体基板100’，如图16所示。半导体基板200’可利用金属覆膜106和金属覆膜512耦合到半导体基板100’以形成本文所述的组合的金属覆膜514。
在将半导体基板200’耦合到半导体基板100’之后，将电绝缘材料508填充到半导体基板200’的上表面和半导体基板100’的下表面之间的空间(间隙)，如图17所示。电绝缘材料508还围绕半导体基板200’和柱延伸部550’。
在某些实施方案中，如图18所示，将半导体基板200’、柱延伸部550’和电绝缘材料508的下部移除。在某些实施方案中，移除半导体基板200’的下部使位于基板下表面上的至少一些互连器104暴露在外。在一些实施方案中，移除半导体基板200’的下部使至少一些无源器件202和至少一些互连器104暴露在外。在一些实施方案中，重新分布层(RDL)520位于基板200’的下部。
如图18所示，将柱延伸部550’和电绝缘材料508减薄至与半导体基板200’相同的程度，其中柱延伸部的至少一部分暴露在电绝缘材料的表面上。因此，柱550和柱延伸部550’(“柱”)提供到集成电路500的输入/输出端子的直接电连接，其中柱具有的高度约等于位于半导体基板200’的暴露表面上的连接件(例如，端子)的高度。
在某些实施方案中，在移除半导体基板200’、柱延伸部550’和电绝缘材料508的下部之后，将金属覆膜522形成在半导体基板、柱延伸部和电绝缘材料的下部，如图19所示。在一些实施方案中，至少一些金属覆膜522与柱延伸部550’接触。金属覆膜522可提供用于连接到半导体基板200’、半导体基板100’和/或集成电路500的端子。半导体基板200’可直接耦合到金属覆膜522。集成电路500可利用柱550和柱延伸部550’耦合到金属覆膜522(以提供用于集成电路的直接输入/输出端子)并且/或者集成电路可利用(在两个基板中的)一个或多个互连器104和/或基板上的RDL耦合到金属覆膜。半导体基板100’可利用一个或多个互连器104和/或基板上的RDL耦合到金属覆膜522。金属覆膜522继而可用于将集成电路500、半导体基板100’和/或半导体基板200’耦合到例如另一器件、封装或印刷电路板。
在某些实施方案中，集成电路500、半导体基板100’、半导体基板200’、柱550、柱延伸部550’和它们的中间部件形成半导体器件1000’，如图19所示。在一些实施方案中，可将半导体器件1000’进一步处理为位于封装或其他结构中。
尽管本文将半导体器件1000和半导体器件1000’示出为半导体基板100耦合在集成电路500和半导体基板200之间，使得无源器件102(例如，电感器)距集成电路的距离比无源器件202(例如，电容器)近。应当理解，半导体基板和/或无源器件的位置可根据需要改变。例如，半导体基板200可首先耦合到集成电路500，使得半导体基板200耦合在集成电路和半导体基板100之间。另一实施例包括将无源器件202置于半导体基板100上并将无源器件102置于半导体基板200上。这些实施例中的任一实施例可提供具有无源器件202(例如，电容器)的半导体器件，该无源器件202比无源器件102(例如，电感器)距集成电路近。
如本文所述，半导体器件1000和半导体器件1000’提供包括靠近集成电路的电压调节部件(例如，诸如电感器和电容器之类的无源器件)的半导体器件。因此，半导体器件1000和半导体器件1000’能够执行接近或等同于芯片上电压调节类型性能的电压调节性能。半导体器件1000和半导体器件1000’在小外形器件中提供以当前半导体器件形式能够实现的高电压调节性能。
另外，半导体器件1000和半导体器件1000’利用比在CMOS工艺期间集成电压调节部件的芯片形成工艺成本低且利用当前工艺易于集成的工艺来形成。由于基板和集成电路均可在耦合之前已产生，因此半导体器件1000和半导体器件1000’还可以高收率制成，特别是在各个基板耦合到各个集成电路的情况下。
在半导体器件100或半导体器件1000’中利用半导体基板100或100’和半导体基板200或200’还使得无源器件(诸如电感器和电容器)在与用于形成集成电路500的CMOS工艺分开的工艺中形成。使这些工艺分开允许无源器件在不影响CMOS工艺的情况下，作为期望的任何类型无源器件并且具备期望的任何特性或规格而制成。无源器件可具有定制特性或规格以提供具有比其他电压调节具体实施更好的性能特性的半导体器件1000或半导体器件1000’。此外，无源器件可针对不同具体实施按需调整。
制备在独立的基板上的无源器件还可使得用于形成无源器件的处理技术集中研究制备更好的无源器件(例如，尽可能接近理想地制备电感器或电容器)。使处理技术集中研究制备在单个基板上的无源器件而不是与另一工艺相结合来制备这些器件可为无源器件提供改善的可靠性和操作。例如，接近理想的电容器可具有较小等效串联电阻(ESR)并且/或者具有从它们的阳极端子或阴极端子到地的较小寄生电容。
根据本说明书，本公开中所述实施方案的各个方面的其他修改和替代实施例对于本领域的技术人员而言将是显而易见的。因此，将本说明书理解为仅是示例性的并且目的是用于教导本领域的技术人员执行实施方案的一般方式。应当理解，本文所示和所述的实施方案的形式将被当做目前优选的实施例。元素与材料可被本文所示和所述的那些元素与材料所替代，可反向部件和工艺并且可独立地利用实施方案的某些特征，在受益于本说明书之后，所有这些对于本领域的技术人员而言都将是显而易见的。可在不脱离以下权利要求书的实质和范围的情况下对本文所述的元素作出修改。

Claims (9)

1.一种半导体器件，包括：
集成电路，包括有源表面，其中所述集成电路包括功耗型半导体器件；
第一半导体基板，具有上表面，所述第一半导体基板利用所述第一半导体基板的所述上表面上的第一金属覆膜直接附接到所述集成电路的所述有源表面，其中所述第一半导体基板包括在所述第一半导体基板中的第一类型无源器件和穿过所述第一半导体基板的第一组互连器，所述第一类型无源器件中的至少一些位于所述第一半导体基板的所述上表面处，并且直接附接到所述第一半导体基板的所述上表面上的所述第一金属覆膜中的至少一些；和
第二半导体基板，所述第二半导体基板利用第二金属覆膜耦合到所述第一半导体基板，其中所述第二半导体基板包括在所述第二半导体基板中的第二类型无源器件和穿过所述第二半导体基板的第二组互连器；
其中第一类型无源器件和第二类型无源器件是不同类型的无源器件，第一类型无源器件包括电感器，且第二类型无源器件包括电容器。
2.根据权利要求1所述的器件，还包括填充围绕所述第一金属覆膜并位于所述第一半导体基板和所述集成电路之间的空间的电绝缘材料。
3.根据权利要求2所述的器件，其中所述电绝缘材料包括填充围绕所述第一金属覆膜并位于所述第一半导体基板和所述集成电路之间的空间的单个电绝缘材料层。
4.根据权利要求1所述的器件，还包括填充围绕所述第二金属覆膜并位于所述第二半导体基板和所述第一半导体基板之间的空间的电绝缘材料。
5.根据权利要求1所述的器件，其中所述有源表面包括到所述集成电路中的有源电路的端子，所述器件还包括一个或多个柱，所述一个或多个柱耦合到在所述第一半导体基板和所述第二半导体基板的周边上所述集成电路的所述有源表面，其中所述柱提供用于所述集成电路的输入/输出端子，并且其中所述有源表面上的端子包括所述输入/输出端子和用于使用第一类型无源器件和/或第二类型无源器件的到所述集成电路的电压调节连接的端子。
6.根据权利要求1所述的器件，其中所述第一半导体基板包括位于耦合到所述第二半导体基板的所述第一半导体基板的表面处的重新分布层，并且其中所述重新分布层将位于所述重新分布层的第一侧上的连接部重新分布到位于所述重新分布层的第二侧上的水平移位的连接部。
7.根据权利要求1所述的器件，其中所述第一组互连器中的至少一些将所述第一金属覆膜互连到所述第二金属覆膜。
8.根据权利要求1所述的器件，其中所述第一半导体基板和所述第二半导体基板具有与所述集成电路的宽度基本上相同的宽度。
9.根据权利要求1所述的器件，其中所述第二半导体基板利用所述第二半导体基板的上表面上的所述第二金属覆膜耦合到所述第一半导体基板，所述器件还包括耦合到所述第二半导体基板的下表面的第三金属覆膜，其中所述第三金属覆膜利用所述第一组互连器中的至少一个互连器和所述第二组互连器中的至少一个互连器耦合到所述集成电路。
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US20200027861A1 (en) 2020-01-23
US20160093592A1 (en) 2016-03-31
US20220320048A1 (en) 2022-10-06
WO2016053469A1 (en) 2016-04-07
KR102065899B1 (ko) 2020-01-13
CN106605298A (zh) 2017-04-26
DE112015004444B4 (de) 2021-12-09
US11398456B2 (en) 2022-07-26
TW201624677A (zh) 2016-07-01
KR20190015615A (ko) 2019-02-13
DE112015004444T5 (de) 2017-07-20
KR20170034909A (ko) 2017-03-29
US10468381B2 (en) 2019-11-05
KR101946504B1 (ko) 2019-02-12
CN106605298B (zh) 2021-07-06
TWI672803B (zh) 2019-09-21

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