CN113396537A

CN113396537A - Amplifier and amplifying device

Info

Publication number: CN113396537A
Application number: CN201980091191.8A
Authority: CN
Inventors: 王国瑞; 杨帆; 力争; 王晨; 张福泉; 李红云
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2019-04-30
Filing date: 2019-04-30
Publication date: 2021-09-14
Anticipated expiration: 2039-04-30
Also published as: WO2020220347A1; CN113396537B

Abstract

An amplifier and an amplifying device are provided to improve the linearity of the amplifier and reduce the gain and power consumption fluctuation of the amplifier. The amplifier includes: at least one first gain circuit for amplifying a first signal; each first gain circuit includes a first transistor and a second transistor; the channel of the first transistor is in a strong inversion state, and the channel of the second transistor is in a weak inversion state; at least one second gain circuit for amplifying a second signal; each second gain circuit includes a third transistor and a fourth transistor; the channel of the third transistor is in a strong inversion state, and the channel of the fourth transistor is in a weak inversion state; the first signal and the second signal constitute a differential signal. The gate bias voltages of the first transistor and the third transistor are first voltages, and the gate bias voltages of the second transistor and the fourth transistor are second voltages.

Description

Amplifier and amplifying device

Technical Field

The present application relates to the field of communications technologies, and in particular, to an amplifier and an amplifying device.

Background

With the development of broadband wireless communication, the performance index of an amplifier in a radio frequency front end is more and more strictly required, and the radio frequency front end amplifier must give consideration to indexes such as gain, noise, linearity and power consumption.

In the prior art, a schematic diagram of an amplifier of a radio frequency front end can be shown in fig. 1. In fig. 1, a signal input at a positive input terminal (Vip) is amplified by a plurality of metal-oxide semiconductor (MOS) transistors connected in parallel, and then transmitted to a negative output terminal (Von) after passing through a parallel resonant load; signals input by the negative input end (Vin) are amplified by the MOS tubes connected in parallel, and then transmitted to the positive output end (Vop) after passing through the parallel resonant load (namely the resistor R, the capacitor C and the inductor L in the figure 1), so that the differential input signals are amplified. That is, in this amplifier, an amplifying function is realized by a plurality of MOS transistors connected in parallel.

In general, in order to improve the linearity of the amplifier, the intrinsic nonlinearity of an active transistor (e.g., a MOS transistor) in the amplifier can be utilized to set the active transistor at a bias point where the n-order (e.g., third-order) nonlinearity is minimum. For the amplifier shown in fig. 1, the MOS transistor is set at a bias point with minimum n-order nonlinearity by adjusting the gate-source bias voltage Vgs. In a specific implementation, the gate-source bias voltage Vgs can be determined by a feedback circuit shown in fig. 2, and the output of the feedback circuit can be applied as the gate-source bias voltage Vgs at the Vgs terminal in fig. 1. The voltage values of the nodes and the current values of the branches in fig. 2 can be derived as follows: using the output of fig. 2 as the gate-source bias voltage can make the third order nonlinearity of the amplifier shown in fig. 1 to be 0.

However, the improvement of the linearity of the amplifier in the manner shown in fig. 2 has the following problems: since the feedback circuit shown in fig. 2 includes various electronic devices such as an active transistor, a current source, and an operational amplifier, when the active transistor is driven by the circuit shown in fig. 2, the output fluctuation of the circuit shown in fig. 2 is large (i.e., the Vgs fluctuation is large) due to the influence of the process, temperature, model accuracy, etc. of these electronic devices, and the gain of the amplifier shown in fig. 1 fluctuates greatly with the process, temperature, model accuracy, etc. of the electronic device shown in fig. 2. Therefore, by adopting the scheme for improving linearity shown in fig. 2, the yield of the amplifier is low due to poor consistency of gain and power consumption in mass production.

In summary, a solution for improving the linearity of an amplifier is needed to reduce the gain and power consumption fluctuation of the amplifier while improving the linearity of the amplifier.

Disclosure of Invention

The embodiment of the application provides an amplifier and an amplifying device, which are used for reducing the gain and power consumption fluctuation of the amplifier while improving the linearity of the amplifier.

In a first aspect, an embodiment of the present application provides an amplifier, including: at least one first gain circuit for amplifying a first signal; each first gain circuit includes a first transistor and a second transistor; the channel of the first transistor is in a strong inversion state, and the channel of the second transistor is in a weak inversion state; at least one second gain circuit for amplifying a second signal; each second gain circuit includes a third transistor and a fourth transistor; the channel of the third transistor is in a strong inversion state, and the channel of the fourth transistor is in a weak inversion state; the first signal and the second signal constitute a differential signal; the grid bias voltage of the first transistor and the third transistor is a first voltage, and the grid bias voltage of the second transistor and the fourth transistor is a second voltage.

By adopting the scheme, the channels of the first transistor and the third transistor are in a strong inversion state, so that the first signal and the second signal can be amplified through the first transistor and the third transistor respectively, and the channels of the second transistor and the fourth transistor are in a weak inversion state, so that the output signal of the first transistor and the output signal of the third transistor can be subjected to nonlinear compensation through the second transistor and the fourth transistor respectively, and the linearity of the amplifier is improved.

Further, in the amplifier provided in the first aspect, the channels of the second transistor and the fourth transistor are in a weak inversion state, and the gain is small and the power consumption is small. Therefore, the amplifier provided by the first aspect is provided in which the gain and the power consumption are mainly determined by the first transistor and the third transistor; the second transistor and the fourth transistor are responsible for cancelling the non-linearity and contribute only a very low proportion of power consumption and gain. Thus, in the amplifier, the linearity of the amplifier can be improved by the second transistor and the fourth transistor, and the gain fluctuation and the power consumption fluctuation of the amplifier can be reduced.

Specifically, since the channel of the first transistor is in a strong inversion state and the channel of the second transistor is in a weak inversion state, the first transistor can be used for amplifying the first signal, and the second transistor can be used for performing nonlinear compensation on the output signal of the first transistor; the third transistor may be used to amplify the second signal and the fourth transistor may be used to non-linearly compensate the output signal of the third transistor, since the channel of the third transistor is in a strong inversion state and the channel of the fourth transistor is in a weak inversion state.

In one possible design, a gate of the first transistor is used for receiving a first signal, a source of the first transistor is coupled to ground, and a drain of the first transistor is coupled to a load of the amplifier; the source electrode of the second transistor is coupled to the ground, and the drain electrode of the second transistor is coupled with the load of the amplifier; the grid electrode of the third transistor is used for receiving a second signal, the source electrode of the third transistor is coupled with the ground, and the drain electrode of the third transistor is coupled with the load of the amplifier; the source of the fourth transistor is coupled to ground and the drain of the fourth transistor is coupled to the load of the amplifier.

In a second aspect, an embodiment of the present application provides an amplifier, including: at least one first gain circuit, each first gain circuit comprising a first transistor and a second transistor; the channel of the first transistor is in a strong inversion state, and the channel of the second transistor is in a weak inversion state; at least one second gain circuit, each second gain circuit comprising a third transistor and a fourth transistor; the channel of the third transistor is in a strong inversion state, and the channel of the fourth transistor is in a weak inversion state; wherein the first signal and the second signal constitute a differential signal; the gate bias voltages of the first transistor and the third transistor are a first voltage, and the gate bias voltages of the second transistor and the fourth transistor are a second voltage.

Further, in the amplifier provided in the second aspect, the channels of the second transistor and the fourth transistor are in a weak inversion state, and the gain thereof is small and the power consumption generated is also small. Therefore, the second aspect provides an amplifier in which the gain and power consumption are mainly determined by the first transistor and the third transistor; the second transistor and the fourth transistor are responsible for cancelling the non-linearity and contribute only a very low proportion of power consumption and gain. Thus, in the amplifier, the linearity of the amplifier can be improved by the second transistor and the fourth transistor, and the gain fluctuation and the power consumption fluctuation of the amplifier can be reduced.

In a third aspect, embodiments of the present application provide an amplifying apparatus including an amplifier and a closed-loop feedback circuit. Wherein the amplifier comprises at least one first gain circuit for amplifying the first signal and at least one second gain circuit for amplifying the second signal. Each first gain circuit includes a first transistor and a second transistor; the channel of the first transistor is in a strong inversion state, and the channel of the second transistor is in a weak inversion state; each second gain circuit includes a third transistor and a fourth transistor; the channel of the third transistor is in a strong inversion state, and the channel of the fourth transistor is in a weak inversion state; the first signal and the second signal constitute a differential signal; the grid bias voltage of the first transistor and the third transistor is a first voltage generated by the first current source, and the grid bias voltage of the second transistor and the fourth transistor is a second voltage; a closed loop feedback circuit for generating the second voltage.

With the adoption of the scheme, because the channels of the first transistor and the third transistor are in a strong inversion state, the first signal and the second signal can be amplified through the first transistor and the third transistor respectively; since the channels of the second transistor and the fourth transistor are in a weak inversion state, the output signal of the first transistor and the output signal of the third transistor can be subjected to nonlinear compensation through the second transistor and the fourth transistor respectively, and the linearity of the amplifier is improved.

In addition, since the first transistor and the third transistor are biased by the first current source, fluctuation in gain and fluctuation in power consumption of the first transistor and the third transistor are also small. When the second transistor and the fourth transistor are biased by the closed-loop feedback circuit, although the bias provided by the closed-loop feedback circuit can cause gain fluctuation and power consumption fluctuation, the channels of the second transistor and the fourth transistor are in a weak inversion state, the gain is small, the generated power consumption is small, and even if the gain fluctuation and the power consumption fluctuation occur, the fluctuation value is difficult to have great influence on the first gain circuit and the second gain circuit. Therefore, in the amplifying device provided in the third aspect, the fluctuation in gain and the fluctuation in power consumption of the first gain circuit and the second gain circuit are small.

In summary, in the amplifying device provided by the third aspect, the gain and the power consumption are mainly determined by the first transistor and the third transistor; the second transistor and the fourth transistor are responsible for cancelling the non-linearity and contribute only a very low proportion of power consumption and gain. Thus, in the amplifying device provided by the third aspect, the linearity of the amplifier can be improved by the second transistor and the fourth transistor, and the gain fluctuation and the power consumption fluctuation of the amplifier can be reduced.

In one possible design, the closed-loop feedback circuit includes a first differential amplification circuit, a second differential amplification circuit, a third differential amplification circuit, and a fourth differential amplification circuit; the direct current bias of the first differential amplification circuit and the third differential amplification circuit is generated by a second current source; and the direct current bias of the second differential amplifying circuit and the fourth differential amplifying circuit is the output voltage of the closed loop feedback circuit.

Further, the gain factor of the third differential amplifying circuit may be 1/m of the gain factor of the first differential amplifying circuit, the ac input voltage of the third differential amplifying circuit may be m times the ac input voltage of the first differential amplifying circuit, and m > 1; the gain factor of the fourth differential amplifying circuit may be 1/m of the gain factor of the second differential amplifying circuit, and the ac input voltage of the fourth differential amplifying circuit may be m times the ac input voltage of the second differential amplifying circuit.

With the above arrangement, the first differential amplifier circuit and the second differential amplifier circuit may be configured as a differential amplifier circuit with a small input signal and a large gain coefficient, and the third differential amplifier circuit and the fourth differential amplifier circuit may be configured as a differential amplifier circuit with a large input signal and a small gain coefficient.

In one possible design, the closed-loop feedback circuit further includes: and the error amplifier is used for comparing the error of the output signal obtained by combining the first differential amplification circuit and the second differential amplification circuit with the error of the output signal obtained by combining the third differential amplification circuit and the fourth differential amplification circuit and outputting a second voltage.

By adopting the scheme, the output signal of the differential amplification circuit with small input signal and large gain coefficient can be compared with the output signal of the differential amplification circuit with large input signal and small gain coefficient, and the nonlinearity of the compensated transistor can be compensated by the nonlinear compensation transistor under the condition that the two output signals are approximately the same, so that the grid bias voltage meeting the design requirement can be obtained by the scheme.

In one possible design, the closed-loop feedback circuit further includes: the positive output end of the first differential amplification circuit and the positive output end of the second differential amplification circuit are coupled to the negative input end of the first transimpedance amplifier, and the negative output end of the first differential amplification circuit and the negative output end of the second differential amplification circuit are coupled to the positive input end of the first transimpedance amplifier; the positive output end of the third differential amplification circuit and the positive output end of the fourth differential amplification circuit are coupled to the negative input end of the second transimpedance amplifier, and the negative output end of the third differential amplification circuit and the negative output end of the fourth differential amplification circuit are coupled to the positive input end of the second transimpedance amplifier; the amplification factor of the second transimpedance amplifier is the same as that of the first transimpedance amplifier; and the positive output end of the first transimpedance amplifier and the positive output end of the second transimpedance amplifier are coupled to the negative input end of the error amplifier, and the negative output end of the first transimpedance amplifier and the negative output end of the second transimpedance amplifier are coupled to the positive input end of the error amplifier.

By adopting the scheme, the direct current bias of the first differential amplification circuit and the third differential amplification circuit is provided by the second current source; and the direct current bias of the second differential amplifying circuit and the fourth differential amplifying circuit is the output voltage of the closed loop feedback circuit. The second differential amplifying circuit can thus perform nonlinear compensation on the first differential amplifying circuit, and the fourth differential amplifying circuit can perform nonlinear compensation on the third differential amplifying circuit. The direct current biases of the second differential amplifying circuit and the fourth differential amplifying circuit found in the feedback mode can be used as the direct current biases of the second transistor and the fourth transistor in the amplifier, so that the second transistor can perform nonlinear compensation on the output signal of the first transistor, and the fourth transistor can perform nonlinear compensation on the output signal of the third transistor.

Furthermore, the first differential amplifier circuit comprises at least one fifth transistor and at least one sixth transistor, the gate of the fifth transistor is coupled to the positive input terminal of the first differential amplifier circuit, the gate of the sixth transistor is coupled to the negative input terminal of the first differential amplifier circuit, the number of the fifth transistors is obtained by reducing the number of the first transistors in the amplifier device by a first ratio, and the number of the sixth transistors is obtained by reducing the number of the third transistors in the amplifier device by the first ratio; the second differential amplification circuit comprises at least one seventh transistor and at least one eighth transistor, the grid of the seventh transistor is coupled with the positive input end of the second differential amplification circuit, the grid of the eighth transistor is coupled with the negative input end of the second differential amplification circuit, the number of the seventh transistors is obtained by reducing the number of the second transistors in the amplification device by a first proportion, and the number of the eighth transistors is obtained by reducing the number of the fourth transistors in the amplification device by the first proportion; the third differential amplification circuit comprises at least one ninth transistor and at least one tenth transistor, the grid of the ninth transistor is coupled with the positive input end of the third differential amplification circuit, the grid of the tenth transistor is coupled with the negative input end of the third differential amplification circuit, the number of the ninth transistors is obtained by reducing the number of the first transistors in the amplification device by a second proportion, and the number of the tenth transistors is obtained by reducing the number of the third transistors in the amplification device by the second proportion; the fourth differential amplifying circuit comprises at least one eleventh transistor and at least one twelfth transistor, wherein the grid electrode of the eleventh transistor is coupled with the positive input end of the fourth differential amplifying circuit, the grid electrode of the twelfth transistor is coupled with the negative input end of the fourth differential amplifying circuit, the number of the eleventh transistors is obtained by reducing the number of the second transistors in the amplifying device by a second proportion, and the number of the twelfth transistors is obtained by reducing the number of the fourth transistors in the amplifying device by the second proportion.

By adopting the scheme, the first differential amplification circuit, the second differential amplification circuit, the third differential amplification circuit and the fourth differential amplification circuit are formed by reducing the number of transistors in the amplification device to a certain extent, so that the power consumption of the closed-loop feedback circuit can be reduced, the power consumption of the amplifier is mainly used for amplifying input signals, and the gate bias voltages of the second transistor and the fourth transistor are determined only by using smaller power consumption to compensate the nonlinearity of output signals.

In addition, the closed loop feedback circuit may further include: the second current source is used for providing direct current bias for the first differential amplification circuit and the third differential amplification circuit; the buffer is used for providing direct current bias for the second differential amplifying circuit and the fourth differential amplifying circuit, and the input end of the buffer is coupled with the output end of the closed-loop feedback circuit; the first resistor, the second resistor, the third resistor and the fourth resistor are sequentially connected in series; the first resistor is coupled to a first power supply, the fourth resistor is coupled to the ground, and the second resistor and the third resistor are coupled with a second current source; the ratio of the resistance values of the first resistor and the second resistor is m-1, the ratio of the resistance values of the fourth resistor and the third resistor is m-1, and the resistance values of the second resistor and the third resistor are the same; the junction of the first resistor and the first power supply is coupled with the positive input end of the third differential amplifier circuit, and the coupling grounding end of the fourth resistor is coupled with the negative input end of the third differential amplifier circuit; the junction of the first resistor and the second resistor is coupled with the positive input end of the first differential amplifier circuit, and the junction of the third resistor and the fourth resistor is coupled with the negative input end of the first differential amplifier circuit; the fifth resistor, the sixth resistor, the seventh resistor and the eighth resistor are sequentially connected in series; the fifth resistor is coupled to the second power supply, the eighth resistor is coupled to the ground, and the sixth resistor and the seventh resistor are coupled to the output end of the buffer; the ratio of the resistance values of the fifth resistor to the sixth resistor is m-1, the ratio of the resistance values of the eighth resistor to the seventh resistor is m-1, and the resistance values of the sixth resistor and the seventh resistor are the same; the junction of the fifth resistor and the second power supply is coupled with the positive input end of the fourth differential amplifier circuit, and the coupling grounding end of the eighth resistor is coupled with the negative input end of the fourth differential amplifier circuit; the junction of the fifth resistor and the sixth resistor is coupled with the positive input end of the second differential amplifier circuit, and the junction of the seventh resistor and the eighth resistor is coupled with the negative input end of the second differential amplifier circuit.

With the adoption of the implementation scheme, alternating current input and direct current bias can be provided for the four differential amplification circuits through the second current source, the buffer and the resistors. The buffer can store and output the output voltage of the closed-loop feedback circuit, so that the direct current bias of the second differential amplification circuit and the fourth differential amplification circuit is a stable voltage value and cannot fluctuate along with the change of current.

The second current source can be obtained by mirror-biasing the first current source. For example, the second current source may include a first current source, an N-type MOS transistor (i.e., NMOS) and a P-type MOS transistor (i.e., PMOS), and the first current source is output after passing through the NMOS and the PMOS in sequence as a dc bias for the first differential amplifier circuit and the third differential amplifier circuit.

In one possible design, a gate of the first transistor is used for receiving a first signal, a source of the first transistor is coupled to ground, and a drain of the first transistor is coupled to a load of the amplifying device; the source electrode of the second transistor is coupled with the ground, and the drain electrode of the second transistor is coupled with the load of the amplifying device; the grid electrode of the third transistor is used for receiving a second signal, the source electrode of the third transistor is coupled with the ground, and the drain electrode of the third transistor is coupled with the load of the amplifying device; the source of the fourth transistor is coupled to ground and the drain of the fourth transistor is coupled to the load of the amplifying means.

By adopting the scheme, a specific connection mode of the first transistor, the second transistor, the third transistor and the fourth transistor is provided.

Drawings

Fig. 1 is a schematic structural diagram of an amplifier provided in the prior art;

fig. 2 is a schematic structural diagram of a feedback circuit provided in the prior art;

fig. 3 is a schematic structural diagram of an amplifier according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of another amplifier provided in the embodiment of the present application;

fig. 5 is a schematic structural diagram of an amplifying device according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of a series resistor according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of another series resistor provided in the embodiment of the present application;

fig. 8 is a schematic structural diagram of a closed-loop feedback circuit according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of another closed-loop feedback circuit provided in the embodiment of the present application;

fig. 10 is a schematic diagram of a variation curve of the total gain of an amplifier according to an embodiment of the present application.

Detailed Description

As described in the background, with the development of broadband wireless communication, the rf front-end amplifier needs to take into account multiple indexes, such as gain, noise, linearity, and power consumption.

To improve the linearity of the amplifier, the prior art typically uses the feedback circuit shown in fig. 2 to provide bias for the active transistors in the amplifier shown in fig. 1. Although the linearity of the amplifier can be improved by using the feedback circuit shown in fig. 2, the gain of the amplifier fluctuates greatly, i.e., it is difficult to achieve the gain, power consumption and linearity indexes of the amplifier.

Embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

In the embodiments of the present application, a plurality means two or more. In addition, it is to be understood that the terms first, second, etc. in the description of the present application are used for distinguishing between the descriptions and not necessarily for describing a sequential or chronological order. The term "coupled", as used herein, refers to an electrical connection, and may include both direct and indirect connections.

Referring to fig. 3, an amplifier 300 according to an embodiment of the present application is provided. The amplifier 300 comprises at least one first gain circuit 301 for amplifying a first signal and at least one second gain circuit 302 for amplifying a second signal. Each first gain circuit 301 includes a first transistor 301a and a second transistor 301 b; the channel of the first transistor 301a is in a strong inversion (strong inversion) state, and the channel of the second transistor 301b is in a weak inversion (weak inversion) state; each second gain circuit 302 includes a third transistor 302a and a fourth transistor 302 b; the channel of the third transistor 302a is in a strong inversion state and the channel of the fourth transistor 302b is in a weak inversion state. The first signal and the second signal constitute a differential signal, the gate bias voltages of the first transistor 301a and the third transistor 302a are a first voltage, and the gate bias voltages of the second transistor 301b and the fourth transistor 302b are a second voltage.

Wherein, the specific meaning of the strong inversion state can be: the gate-source voltage VGS of the transistor is much larger than the threshold voltage VT of the transistor, an inversion layer (channel) is formed below the gate oxide film, and a current flow is active between the drain and the source of the transistor, which is called a strong inversion state. Specific meanings of the weak inversion state may be: the gate-source voltage VGS of the transistor is smaller than the threshold voltage VT of the transistor and there is still little current activity at the drain, which state is called weak inversion state.

Specifically, in the amplifier 300, since the channel of the first transistor 301a is in a strong inversion state and the channel of the second transistor 301b is in a weak inversion state, the first transistor 301a can be used to amplify a first signal, and the second transistor 301b can be used to perform nonlinear compensation on an output signal of the first transistor 301 a; since the channel of the third transistor 302a is in a strong inversion state and the channel of the fourth transistor 302b is in a weak inversion state, the third transistor 302a may be used to amplify the second signal and the fourth transistor 302b may be used to non-linearly compensate the output signal of the third transistor 302 a.

In the amplifier 300 shown in fig. 3, the first transistor 301a and the third transistor 302a can be used to amplify the first signal and the second signal, and the second transistor 301b and the fourth transistor 302b can be used to nonlinearly compensate the output signal of the first transistor 301a and the output signal of the third transistor 302a, so as to improve the linearity of the amplifier 300.

In the amplifier 300, the channels of the second transistor 301b and the fourth transistor 302b are in a weak inversion state, and thus the gain is small and the power consumption is small. Therefore, the gain and power consumption of the amplifier 300 are mainly determined by the first transistor 301a and the third transistor 302 a; the second transistor 301b and the fourth transistor 302b are responsible for cancelling the non-linearity, contributing only a very low proportion of power consumption and gain. Thus, in the amplifier 300, the gain fluctuation and the power consumption fluctuation of the amplifier 300 can be reduced while the linearity of the amplifier 300 can be improved by the second transistor 301b and the fourth transistor 302 b.

In a specific implementation, in the amplifier 300, the first transistor 301a, the second transistor 301b, the third transistor 302a, and the fourth transistor 302b may be connected in a specific manner: the gate of the first transistor 301a is used for receiving a first signal, the source of the first transistor 301a is coupled to ground, and the drain of the first transistor 301a is coupled to the load of the amplifier 300; the source of the second transistor 301b is coupled to ground, and the drain of the second transistor 301b is coupled to the load of the amplifier 300; the gate of the third transistor 302a is used for receiving the second signal, the source of the third transistor 302a is coupled to the ground, and the drain of the third transistor 302a is coupled to the load of the amplifier 300; the source of the fourth transistor 302b is coupled to ground and the drain of the fourth transistor 302b is coupled to the load of the amplifier 300.

Wherein the source of the first transistor 301a is coupled to ground, which may mean: the first transistor 301a is directly grounded, or the first transistor 301a is grounded through an inductor, a capacitor, or the like. In addition, in other examples of the embodiments of the present application, the coupling to ground has the same meaning and will not be explained in detail later.

In the description of the embodiments of the present application, the transistors are illustrated by using a CMOS process as an example. In practical applications, other processes may be used for the transistor. When other processes are used for the transistor, the names of the ports of the transistor are different, but the functions are basically the same. Illustratively, when the transistor is a Bipolar Junction Transistor (BJT), the base of the BJT corresponds to the gate of the CMOS; the collector in the BJT corresponds to the drain in the CMOS; the emitter in the BJT is equivalent to the source in the CMOS. Therefore, the amplifier implemented based on CMOS transistor in this application can be equivalent to the amplifier implemented based on BJT.

Because the implementation manner and principle of the transistor adopting other processes are similar to those of the transistor adopting the CMOS process, the embodiment of the present application is illustrated by taking the transistor adopting the CMOS process as an example, and detailed description of the specific implementation manner of the transistor adopting other processes is not provided.

In addition, in each example of the present application, the transistor is in a mode of inputting a gate signal and coupling a source to ground, and in practical applications, the transistor may also be in a mode of inputting a source signal and coupling a gate to ground, which is not specifically limited in this embodiment of the present application.

Illustratively, when the transistors in the amplifier 300 are connected in the manner described above and the amplifier 300 includes a parallel resonant load, a possible structural schematic diagram of the amplifier 300 can be shown in fig. 4.

In the amplifier 300 shown in fig. 4, the transistor whose gate is coupled to the positive input terminal Vip may be regarded as a first transistor 301a, the transistor whose gate is coupled to the negative input terminal Vin may be regarded as a third transistor 302a, the transistor connected to the first transistor 301a and biased by Vgs _ Aux may be regarded as a second transistor 301b, and the transistor connected to the third transistor 302a and biased by Vgs _ Aux may be regarded as a fourth transistor 302 b. The RLC network forms an equivalent parallel resonance load, Vop is a positive output end, and Von is a negative output end. The first transistor 301a and the third transistor 302a amplify differential signals output from the positive input terminal and the negative input terminal, respectively, and may be collectively referred to as a "main transistor"; the second transistor 301b and the fourth transistor 302b perform nonlinear compensation on the output signals of the first transistor 301a and the third transistor 302a, respectively, and may be collectively referred to as "auxiliary compensation tubes". The interconnected "primary tube" and "auxiliary compensator tube" may be referred to as a "Gm cell".

Based on the same inventive concept, the embodiment of the application also provides an amplifying device. Referring to fig. 5, an amplifier 501 and a closed-loop feedback circuit 502 are included in the amplifying apparatus 500. Wherein the amplifier 501 comprises at least one first gain circuit for amplifying the first signal and at least one second gain circuit for amplifying the second signal.

Wherein each first gain circuit comprises a first transistor and a second transistor; the channel of the first transistor is in a strong inversion state, and the channel of the second transistor is in a weak inversion state; each second gain circuit includes a third transistor and a fourth transistor; the channel of the third transistor is in a strong inversion state, and the channel of the fourth transistor is in a weak inversion state; the first signal and the second signal constitute a differential signal; gate bias voltages of the first transistor and the third transistor are first voltages generated by a first current source, and gate bias voltages of the second transistor and the fourth transistor are second voltages; a closed loop feedback circuit for generating the second voltage.

In the amplifying apparatus 500, the specific implementation manner of the amplifier 501 can be referred to the related description in the amplifier 300 shown in fig. 3, and is not described herein again.

In the amplifying device 500 shown in fig. 5, the amplification of the first signal and the second signal may be achieved by the first transistor and the third transistor, respectively. Since the first transistor and the third transistor are biased by the first current source, it is difficult to ensure that the first transistor and the third transistor can be set at a bias point where the n-order nonlinearity is minimal. In the embodiment of the present application, the output signal of the first transistor and the output signal of the third transistor may be nonlinearly compensated by the second transistor and the fourth transistor, respectively, so that the linearity of the amplifying device 500 may be improved.

In addition, the first transistor and the third transistor are biased by the first current source, and the bias mode can be regarded as a fixed bias, the fluctuation of the bias voltage is small, and therefore the fluctuation of the gain and the fluctuation of the power consumption of the first transistor and the third transistor are also small. When the second transistor and the fourth transistor are biased by the closed-loop feedback circuit 502, although the bias provided by the closed-loop feedback circuit 502 may cause gain fluctuation and power consumption fluctuation, the second transistor and the fourth transistor are transistors for performing nonlinear compensation, and have smaller gains and smaller generated power consumption, so that even if the gain fluctuation and the power consumption fluctuation occur, the value of the fluctuation hardly has a large influence on the first gain circuit and the second gain circuit. Therefore, in the amplifying apparatus 500, the gain fluctuation and the power consumption fluctuation of the first gain circuit and the second gain circuit are small.

In summary, in the amplifying device 500, the gain and the power consumption are mainly determined by the first transistor and the third transistor; the second transistor and the fourth transistor are responsible for cancelling the non-linearity and contribute only a very low proportion of power consumption and gain. Thus, in the amplifying device 500, the linearity of the amplifier can be improved by the second transistor and the fourth transistor while reducing the gain fluctuation and the power consumption fluctuation of the amplifier.

In a specific implementation, in the amplifying device 500, the first transistor, the second transistor, the third transistor, and the fourth transistor may be connected in a specific manner: a gate of the first transistor is used for receiving a first signal, a source of the first transistor is coupled to ground, and a drain of the first transistor is coupled to a load of the amplifying device 500; the source of the second transistor is coupled to ground, and the drain of the second transistor is coupled to the load of the amplifying device 500; the gate of the third transistor is used for receiving the second signal, the source of the third transistor is coupled to the ground, and the drain of the third transistor is coupled to the load of the amplifying device 500; the source of the fourth transistor is coupled to ground and the drain of the fourth transistor is coupled to the load of the amplifying device 500.

In a possible implementation manner, the amplifying device 500 may further include a parallel resonant load, and the parallel resonant load may be regarded as an equivalent load of the amplifying device 300. The input end of the parallel resonant load is respectively coupled with the output end of the first gain circuit and the output end of the second gain circuit.

The parallel resonant load may be an output matching network or a balun (balun) device.

In particular implementations, the closed-loop feedback circuit 302 may include: the differential amplifier comprises a first differential amplifying circuit, a second differential amplifying circuit, a third differential amplifying circuit, a fourth differential amplifying circuit, a first transimpedance amplifier, a second transimpedance amplifier and error amplification. The direct current bias of the first differential amplifying circuit and the third differential amplifying circuit is provided by a second current source; and the direct current bias of the second differential amplifying circuit and the fourth differential amplifying circuit is the output voltage of the closed loop feedback circuit.

Furthermore, the gain coefficient of the third differential amplification circuit is 1/m of the gain coefficient of the first differential amplification circuit, the alternating current input voltage of the third differential amplification circuit is m times of the alternating current input voltage of the first differential amplification circuit, and m is greater than 1; the gain coefficient of the fourth differential amplifying circuit is 1/m of the gain coefficient of the second differential amplifying circuit, and the alternating current input voltage of the fourth differential amplifying circuit is m times of the alternating current input voltage of the second differential amplifying circuit.

It is obvious that, with the above-described configuration, the first differential amplifier circuit and the second differential amplifier circuit may be configured as a differential amplifier circuit for a small input signal and a large gain coefficient, and the third differential amplifier circuit and the fourth differential amplifier circuit may be configured as a differential amplifier circuit for a large input signal and a small gain coefficient.

In addition, the closed loop feedback circuit 502 may also include an error amplifier. The error amplifier is used for comparing errors of the output signals obtained by combining the first differential amplifying circuit and the second differential amplifying circuit and the output signals obtained by combining the third differential amplifying circuit and the fourth differential amplifying circuit, and outputting a second voltage.

The error amplifier can compare the output signal of the differential amplifying circuit with small input signal and large gain coefficient with the output signal of the differential amplifying circuit with large input signal and small gain coefficient, and the transistor for nonlinear compensation can compensate the nonlinearity of the transistor compensated by the transistor under the condition that the two output signals are approximately the same, so that the grid bias voltage meeting the design requirement can be obtained through the scheme.

Further, the closed loop feedback circuit 502 may also include a first transimpedance amplifier and a second transimpedance amplifier. The positive output end of the first differential amplification circuit and the positive output end of the second differential amplification circuit are coupled to the negative input end of the first transimpedance amplifier, and the negative output end of the first differential amplification circuit and the negative output end of the second differential amplification circuit are coupled to the positive input end of the first transimpedance amplifier; a positive output end of the third differential amplification circuit and a positive output end of the fourth differential amplification circuit are coupled to a negative input end of the second transimpedance amplifier, and a negative output end of the third differential amplification circuit and a negative output end of the fourth differential amplification circuit are coupled to a positive input end of the second transimpedance amplifier; the gain coefficient of the second transimpedance amplifier is the same as the gain coefficient of the first transimpedance amplifier. The positive output end of the first transimpedance amplifier and the positive output end of the second transimpedance amplifier are coupled to the negative input end of the error amplifier, and the negative output end of the first transimpedance amplifier and the negative output end of the second transimpedance amplifier are coupled to the positive input end of the error amplifier; the output of the error amplifier serves as the output of the closed loop feedback circuit 502.

Then, in one possible example, the closed-loop feedback circuit 502 may include a first differential amplification circuit, a second differential amplification circuit, a third differential amplification circuit, a fourth differential amplification circuit, a first transimpedance amplifier, a second transimpedance amplifier, and an error amplifier.

Assuming that the gain coefficient of the first differential amplifier circuit is a, the ac input voltage at the positive input terminal of the first differential amplifier circuit is a1, and the ac input voltage at the negative input terminal of the first differential amplifier circuit is a 2; the gain coefficient of the second differential amplifier circuit is B, the ac input voltage at the positive input terminal of the second differential amplifier circuit is B1, and the ac input voltage at the negative input terminal of the second differential amplifier circuit is B1. Then, the ac input voltages of the third differential amplifier circuit are m × a1 and m × a2, and the gain factor is a × 1/m; the ac input voltages of the fourth differential amplifier circuit are m × B1 and m × B2, and the gain coefficient is B × 1/m. Then, for the first transimpedance amplifier coupled to the first differential amplifier circuit and the second differential amplifier circuit, the input at its positive input terminal is a 1a + B1B, and the input at its negative input terminal is a 2a + B2B; for the second transimpedance amplifier coupled to the third and fourth differential amplifier circuits, the input at its positive input is m a 1a 1/m + m B1B 1/m a 1a + B1B, and the input at its negative input is m a 2a 1/m + m B2B 1/m a 2a + B2B. Since the gain coefficients of the first transimpedance amplifier and the second transimpedance amplifier are the same, the outputs of the first transimpedance amplifier and the second transimpedance amplifier should be the same when the linearity of the first differential amplification circuit, the second differential amplification circuit, the third differential amplification circuit, and the fourth differential amplification circuit is high.

In the above implementation, the dc bias of the first differential amplifying circuit and the third differential amplifying circuit is provided by the second current source; and the direct current bias of the second differential amplifying circuit and the fourth differential amplifying circuit is the output voltage of the closed loop feedback circuit. The second differential amplifying circuit can thus perform nonlinear compensation on the first differential amplifying circuit, and the fourth differential amplifying circuit can perform nonlinear compensation on the third differential amplifying circuit. The dc biases of the second differential amplifier circuit and the fourth differential amplifier circuit found by the feedback method can be used as the dc biases of the second transistor and the fourth transistor in the amplifier 500, so that the second transistor can perform nonlinear compensation on the output signal of the first transistor, and the fourth transistor can perform nonlinear compensation on the output signal of the third transistor.

In a specific implementation, the first differential amplifier circuit may include at least one fifth transistor and at least one sixth transistor, a gate of the fifth transistor is coupled to the positive input terminal of the first differential amplifier circuit, a gate of the sixth transistor is coupled to the negative input terminal of the first differential amplifier circuit, the number of the fifth transistors is obtained by reducing the number of the first transistors in the amplifier 500 by a first ratio, and the number of the sixth transistors is obtained by reducing the number of the third transistors in the amplifier 500 by the first ratio.

The second differential amplifying circuit may include at least one seventh transistor and at least one eighth transistor, a gate of the seventh transistor is coupled to the positive input terminal of the second differential amplifying circuit, a gate of the eighth transistor is coupled to the negative input terminal of the second differential amplifying circuit, the number of the seventh transistors is obtained by reducing the number of the second transistors in the amplifying device 500 by the first ratio, and the number of the eighth transistors is obtained by reducing the number of the fourth transistors in the amplifying device 500 by the first ratio.

The third differential amplifying circuit may include at least one ninth transistor and at least one tenth transistor, a gate of the ninth transistor is coupled to the positive input terminal of the third differential amplifying circuit, a gate of the tenth transistor is coupled to the negative input terminal of the third differential amplifying circuit, the number of the ninth transistors is obtained by reducing the number of the first transistors in the amplifying device 500 by the second ratio, and the number of the tenth transistors is obtained by reducing the number of the third transistors in the amplifying device 500 by the second ratio. The first ratio is m times the second ratio.

The fourth differential amplifying circuit may include at least one eleventh transistor and at least one twelfth transistor, a gate of the eleventh transistor is coupled to the positive input terminal of the fourth differential amplifying circuit, a gate of the twelfth transistor is coupled to the negative input terminal of the fourth differential amplifying circuit, a number of the eleventh transistors is obtained by reducing a number of the second transistors in the amplifying device 500 by the second ratio, and a number of the twelfth transistors is obtained by reducing a number of the fourth transistors in the amplifying device 500 by the second ratio.

That is to say, the first differential amplifier circuit and the third differential amplifier circuit can be formed by removing the second transistor and the fourth transistor in the amplifier 501 and reducing the number of the first transistor and the third transistor to a certain extent, and both the first differential amplifier circuit and the third differential amplifier circuit can be used for simulating the operating state of the transistors used for amplifying the input signal in the amplifier 501, and the difference is only that the gain coefficients of the first differential amplifier circuit and the second differential amplifier circuit are different; the second differential amplifier circuit and the fourth differential amplifier circuit can be formed by removing the first transistor and the third transistor from the amplifier 501 and reducing the number of the second transistor and the fourth transistor to a certain extent, and both the second differential amplifier circuit and the fourth differential amplifier circuit can be used for simulating the operating state of the transistors for performing nonlinear compensation in the amplifier 501.

By reducing the number of transistors in the amplifier 501 to a certain extent to form four differential amplifier circuits, the power consumption of the closed-loop feedback circuit 502 can be reduced, so that the power consumption of the amplifier 500 is mainly used for amplifying the input signal, and the bias of the second transistor and the bias of the fourth transistor are determined only by using smaller power consumption to compensate the nonlinearity of the output signal.

The fifth transistor and the first transistor may have the same specification, and the sixth transistor and the third transistor may have the same specification; the seventh transistor and the second transistor may have the same specification, and the eighth transistor and the fourth transistor may have the same specification; the ninth transistor and the first transistor may have the same specification, and the tenth transistor and the third transistor may have the same specification; the eleventh transistor and the second transistor may have the same specification, and the twelfth transistor and the fourth transistor may have the same specification.

In addition, the closed loop feedback circuit 502 may further include: the second current source is used for providing direct current bias for the first differential amplification circuit and the third differential amplification circuit; a buffer for providing a dc bias to the second differential amplifying circuit and the fourth differential amplifying circuit, an input terminal of the buffer being coupled to an output terminal of the closed-loop feedback circuit 502; the first resistor, the second resistor, the third resistor and the fourth resistor are sequentially connected in series; and the fifth resistor, the sixth resistor, the seventh resistor and the eighth resistor are sequentially connected in series.

The second current source can be obtained by mirror-biasing the first current source. The buffer may store and output the output voltage of the closed-loop feedback circuit 502, so that the dc bias of the second differential amplifier circuit and the fourth differential amplifier circuit is a stable voltage value and will not fluctuate with the current change.

Specifically, the specific connection mode of the first resistor to the fourth resistor connected in series may be: the first resistor is coupled to a first power supply, the fourth resistor is coupled to the ground, and the second resistor and the third resistor are coupled with a second current source; the ratio of the resistance values of the first resistor and the second resistor is m-1, the ratio of the resistance values of the fourth resistor and the third resistor is m-1, and the resistance values of the second resistor and the third resistor are the same; the junction of the first resistor and the first power supply is coupled with the positive input end of the third differential amplifier circuit, and the coupling grounding end of the fourth resistor is coupled with the negative input end of the third differential amplifier circuit; the junction of the first resistor and the second resistor is coupled with the positive input end of the first differential amplifier circuit, and the junction of the third resistor and the fourth resistor is coupled with the negative input end of the first differential amplifier circuit. Wherein the first power source may be an alternating current source.

Specifically, the connection manner of the fifth resistor to the eighth resistor connected in series may be: the fifth resistor is coupled to the second power supply, the eighth resistor is coupled to the ground, and the sixth resistor and the seventh resistor are coupled to the output end of the buffer; the ratio of the resistance values of the fifth resistor to the sixth resistor is m-1, the ratio of the resistance values of the eighth resistor to the seventh resistor is m-1, and the resistance values of the sixth resistor and the seventh resistor are the same; the junction of the fifth resistor and the second power supply is coupled with the positive input end of the fourth differential amplifier circuit, and the coupling grounding end of the eighth resistor is coupled with the negative input end of the fourth differential amplifier circuit; the junction of the fifth resistor and the sixth resistor is coupled with the positive input end of the second differential amplifier circuit, and the junction of the seventh resistor and the eighth resistor is coupled with the negative input end of the second differential amplifier circuit. Wherein the second power source may be an alternating current source.

With the adoption of the implementation scheme, alternating current input and direct current bias can be provided for the four differential amplification circuits through the second current source, the buffer and the resistors.

For example, the outputs of the first resistor, the second resistor, the third resistor and the fourth resistor connected in series in sequence and the nodes thereof can be as shown in fig. 6. As can be seen from fig. 6, the dc bias of the first differential amplifying circuit and the third differential amplifying circuit are both provided by the second current source. Since the ratio of the resistance values of the first resistor to the second resistor is m-1, the ratio of the resistance values of the fourth resistor to the third resistor is m-1, and the resistance values of the second resistor and the third resistor are the same, the input of the positive input end of the third differential amplifier circuit is m times of the input of the positive input end of the first differential amplifier circuit, and the input of the negative input end of the third differential amplifier circuit is m times of the input of the negative input end of the first differential amplifier circuit. Thus, it is possible to realize "the ac input voltage of the third differential amplifier circuit is m times the ac input voltage of the first differential amplifier circuit, and the dc offsets of the first differential amplifier circuit and the third differential amplifier circuit are provided by the second current source" by the four resistors connected in series in this order as shown in fig. 6.

For example, the outputs of the fifth resistor, the sixth resistor, the seventh resistor and the eighth resistor connected in series in sequence and the nodes thereof may be as shown in fig. 7. In fig. 7, the input of the buffer is coupled to the output of the closed-loop feedback circuit, and thus the dc bias of the second and fourth differential amplification circuits is the output voltage of the closed-loop feedback circuit 502. Since the resistance value ratio of the fifth resistor to the sixth resistor is m-1, the resistance value ratio of the eighth resistor to the seventh resistor is m-1, and the resistance values of the sixth resistor and the seventh resistor are the same, the input of the positive input end of the fourth differential amplifier circuit is m times of the input of the positive input end of the second differential amplifier circuit, and the input of the negative input end of the fourth differential amplifier circuit is m times of the input of the negative input end of the second differential amplifier circuit. Therefore, the four resistors connected in series in sequence as shown in fig. 7 can realize that "the ac input voltage of the fourth differential amplifier circuit is m times of the ac input voltage of the second differential amplifier circuit, and the dc bias of the second differential amplifier circuit and the fourth differential amplifier circuit is the output voltage of the closed-loop feedback circuit".

A schematic diagram of one possible configuration of the closed-loop feedback circuit 502 may be shown in fig. 8, in conjunction with the above description of the closed-loop feedback circuit 502. In fig. 8, the closed-loop feedback circuit 502 includes a first differential amplifier circuit, a second differential amplifier circuit, a third differential amplifier circuit, a fourth differential amplifier circuit, a first transimpedance amplifier, a second transimpedance amplifier, an error amplifier, a second current source, a buffer, and a series resistor (a first resistor, a second resistor, a third resistor, and a fourth resistor connected in series, and a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor connected in series). With the closed loop feedback circuit 502 shown in fig. 8, the second transistor and the fourth transistor in the amplifying apparatus 500 shown in fig. 5 can be provided with a bias, so that the second transistor performs non-linear compensation on the first transistor, and the fourth transistor performs non-linear compensation on the third transistor.

Illustratively, for the amplifier shown in fig. 4, a closed-loop feedback circuit shown in fig. 9 may be employed to provide Vgs _ Aux (equivalent to the bias voltage of the second transistor and the fourth transistor) for the amplifier. I.e., the closed loop feedback circuit shown in fig. 9 is connected to the Vgs _ Aux terminal in fig. 4. The amplifier shown in fig. 4 and the closed-loop feedback circuit shown in fig. 9 may constitute an amplifying apparatus, which may be regarded as a specific example of the amplifying apparatus 500 shown in fig. 5.

In FIG. 9, Main Gm in the upper half (denoted by 4 x) corresponds to the case where "auxiliary compensating pipe" and "Main pipe" in FIG. 4 are removed by a reduced amount of 4/n, and Aux Gm in the upper half corresponds to the case where "Main pipe" and "auxiliary compensating pipe" in FIG. 4 are removed by a reduced amount of 4/n; the Main Gm in the lower half (denoted by 1 x) is formed by removing the "auxiliary compensating pipe" and the "Main pipe" in FIG. 4 by a reduced amount of 1/n, and the Aux Gm in the lower half is formed by removing the "Main pipe" and the "auxiliary compensating pipe" in FIG. 4 by a reduced amount of 1/n. Illustratively, n may be 100. That is, the Gm cell in fig. 9 can be obtained by duplicating the "main tube" and the "auxiliary compensation tube" in the Gm cell in fig. 4 in two copies having sizes of 1/n and 4/n, respectively. Wherein the common mode of the Main tube (Main Gm) is biased by a conventional mirror and the common mode of the auxiliary compensation tube (Aux Gm) is biased by the voltage of the closed-loop feedback circuit (i.e., Vgs _ Aux).

Differential signals having different magnitudes can be applied to the Gm cell in the upper half and the Gm cell in the lower half by the buffer and the current source in fig. 9. For example, the ratio of the gain coefficients of the Gm cell in the upper half and the Gm cell in the lower half is 4:1, and then the ratio of the input signals of the Gm cell in the upper half and the Gm cell in the lower half may be 1: 4. Then, the two paths of differential output currents are converted into voltages through trans-impedance amplifiers in opposite proportion. The two differential voltages are amplified by an Error Amplifier (EA) and used for controlling the state of the auxiliary compensating tube in fig. 4 to form closed-loop negative feedback.

The closed-loop negative feedback has a function of equalizing the outputs of the small signal path (the upper half of fig. 9, where the input signal is 1 × and is referred to as a small signal path) and the large signal path (the lower half of fig. 9, where the input signal is 4 × and is referred to as a large signal path), and equalizing the outputs of the upper and lower portions, that is, achieving "linearity". At this time, the output Vgs _ Aux voltage found by the closed-loop feedback circuit just enables the auxiliary compensating tube to fill up the nonlinear fluctuation of the main tube, and the self-adaptive closed-loop regulation is realized.

In summary, with the amplifying device 500 provided in the embodiment of the present application, since the channels of the first transistor 301a and the third transistor 302a are in a strong inversion state, the first transistor 301a and the third transistor 302a can respectively amplify the first signal and the second signal; since the channels of the second transistor 301b and the fourth transistor 302b are in a weak inversion state, the output signal of the first transistor 301a and the output signal of the third transistor 302a can be nonlinearly compensated by the second transistor 301b and the fourth transistor 302b, respectively, thereby improving the linearity of the amplifier 501.

Since the first transistor and the third transistor are biased by the first current source, the bias mode can be regarded as a fixed bias, the fluctuation of the bias voltage is small, and the fluctuation of the gain and the power consumption of the first transistor and the third transistor are also small. When the second transistor and the fourth transistor are biased by the closed-loop feedback circuit 502, although the bias provided by the closed-loop feedback circuit 502 may cause gain fluctuation and power consumption fluctuation, the channels of the second transistor and the fourth transistor are in a weak inversion state, the gain is small, the generated power consumption is small, and even if the gain fluctuation and the power consumption fluctuation occur, the fluctuation value hardly has a great influence on the first gain circuit and the second gain circuit. Therefore, in the amplifying apparatus 500, the gain fluctuation and the power consumption fluctuation of the first gain circuit and the second gain circuit are small.

In summary, in the amplifying device 500 provided in the embodiment of the present application, the gain and the power consumption are mainly determined by the first transistor and the third transistor; the second transistor and the fourth transistor are responsible for cancelling the non-linearity and contribute only a very low proportion of power consumption and gain. Thus, in the amplifying apparatus 500, the linearity of the amplifier 501 can be improved by the second transistor and the fourth transistor, and at the same time, the gain fluctuation and the power consumption fluctuation of the amplifier 501 can be reduced.

Illustratively, with the amplifying device 500 provided by the embodiment of the present application, the total gain of the amplifier, the main transistor (i.e., the first transistor and the third transistor) gain, and the auxiliary compensation transistor (i.e., the second transistor and the fourth transistor) gain can vary with the input signal as shown in fig. 10. As can be seen from fig. 10, the linearity of the overall gain of the amplifier is better. When the input signal changes, the auxiliary compensation pipe can perform nonlinear compensation on the main pipe, so that the total gain of the amplifier is stable along with the input signal.

Particularly, if the gain of the auxiliary compensating pipe fluctuates (for example, fluctuates by 50%) due to process, temperature, model accuracy and the like of each device in the closed-loop feedback circuit, since the gain of the main pipe is much larger than the gain of the auxiliary compensating pipe, the fluctuation of the gain of the auxiliary compensating pipe does not have a large influence on the total gain of the amplifier, and thus compared with the scheme provided in the prior art, the gain and power consumption fluctuation of the amplifier can be reduced by using the amplifying device 500 provided in the embodiment of the present application.

In addition, the amplifier total gain and the input referred 3rd-order intercept point (IIP 3) change can be shown in table 1 and table 2, respectively, before and after compensation with the auxiliary compensation tube at different temperatures and processes. Wherein before compensation, the amplifier does not comprise an auxiliary compensation tube, and the main tube adopts a current source bias condition; the compensated amplification device refers to the situation of the amplification device provided by the embodiment of the application.

TABLE 1

Gm (gain)	Uncompensated (Gm)	After compensation (Gm)
tt 55	10.6	11.1
ss-40	11.6	11.9
ss 125	9.4	10
ff-40	12.4	12.7
ff 125	10	10.6

TABLE 2

IIP3	Uncompensated (dBm)	After compensation (dBm)
tt 55	10.2	16.7

ss-40	10.3	17.3
ss 125	11.3	17.9
ff-40	10.1	16.2
ff 125	11.2	16.6

In tables 1 and 2, "tt", "ss", "ff" indicate different process angles, and the numbers following represent temperatures. As can be seen from Table 1, the fluctuation of the total gain of the amplifier after compensation is reduced under different processes and temperatures (the fluctuation of the gain before compensation is 9.4-12.4, and the fluctuation of the gain after compensation is 10-12.7); as can be seen from table 2, the IIP3 is significantly improved after the amplifier is compensated under different processes and temperatures, i.e. the linearity of the amplifier is improved.

In addition, the amplifier 300 and the amplifying device 500 provided in the embodiment of the present application may be applied to various terminal devices, for example, a mobile phone (mobile phone), a tablet computer (pad), a Virtual Reality (VR) terminal, an Augmented Reality (AR) terminal, and the like.

It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present application without departing from the scope of the embodiments of the present application. Thus, if such modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to encompass such modifications and variations.

Claims

An amplifier, comprising:

at least one first gain circuit for amplifying a first signal; each first gain circuit includes a first transistor and a second transistor; the channel of the first transistor is in a strong inversion state, and the channel of the second transistor is in a weak inversion state;

at least one second gain circuit for amplifying a second signal; each second gain circuit includes a third transistor and a fourth transistor; the channel of the third transistor is in a strong inversion state, and the channel of the fourth transistor is in a weak inversion state; the first signal and the second signal constitute a differential signal;

wherein gate bias voltages of the first transistor and the third transistor are a first voltage, and gate bias voltages of the second transistor and the fourth transistor are a second voltage.
The amplifier of claim 1, wherein the first transistor is configured to amplify a first signal, and the second transistor is configured to nonlinearly compensate an output signal of the first transistor; the third transistor is used for amplifying a second signal, and the fourth transistor is used for carrying out nonlinear compensation on an output signal of the third transistor.
The amplifier of claim 1 or 2, wherein a gate of the first transistor is to receive the first signal, a source of the first transistor is coupled to ground, and a drain of the first transistor is coupled to a load of the amplifier;

the source of the second transistor is coupled to ground, and the drain of the second transistor is coupled to the load of the amplifier;

the grid electrode of the third transistor is used for receiving the second signal, the source electrode of the third transistor is coupled to the ground, and the drain electrode of the third transistor is coupled with the load of the amplifier;

the source of the fourth transistor is coupled to ground and the drain of the fourth transistor is coupled to the load of the amplifier.
An amplifying device, comprising an amplifier and a closed loop feedback circuit; the amplifier comprises at least one first gain circuit for amplifying a first signal and at least one second gain circuit for amplifying a second signal;

wherein each first gain circuit comprises a first transistor and a second transistor; the channel of the first transistor is in a strong inversion state, and the channel of the second transistor is in a weak inversion state; at least one second gain circuit, each second gain circuit comprising a third transistor and a fourth transistor; the channel of the third transistor is in a strong inversion state, and the channel of the fourth transistor is in a weak inversion state; the first signal and the second signal constitute a differential signal; wherein gate bias voltages of the first transistor and the third transistor are a first voltage generated by a first current source, and gate bias voltages of the second transistor and the fourth transistor are a second voltage;

the closed loop feedback circuit is used for generating the second voltage.
The amplifying device according to claim 4, wherein the first transistor is for amplifying a first signal, and the second transistor is for non-linearly compensating an output signal of the first transistor; the third transistor is used for amplifying a second signal, and the fourth transistor is used for carrying out nonlinear compensation on an output signal of the third transistor.
The amplifying device according to claim 4 or 5, wherein the closed-loop feedback circuit includes a first differential amplifying circuit, a second differential amplifying circuit, a third differential amplifying circuit, and a fourth differential amplifying circuit;

wherein the DC bias of the first and third differential amplification circuits is generated by a second current source; and the direct current bias of the second differential amplifying circuit and the fourth differential amplifying circuit is the output voltage of the closed loop feedback circuit.
The amplifying device according to claim 6, wherein a gain factor of the third differential amplifying circuit is 1/m of a gain factor of the first differential amplifying circuit, an ac input voltage of the third differential amplifying circuit is m times the ac input voltage of the first differential amplifying circuit, and m > 1;

the gain coefficient of the fourth differential amplification circuit is 1/m of the gain coefficient of the second differential amplification circuit, and the alternating current input voltage of the fourth differential amplification circuit is m times of the alternating current input voltage of the second differential amplification circuit.
The amplifying apparatus of claim 6 or 7, wherein the closed loop feedback circuit further comprises:

and the error amplifier is used for comparing the error of the output signal obtained by combining the first differential amplifying circuit and the second differential amplifying circuit with the error of the output signal obtained by combining the third differential amplifying circuit and the fourth differential amplifying circuit, and outputting the second voltage.
The amplification apparatus of claim 8, wherein the closed-loop feedback circuit further comprises:

a first transimpedance amplifier, a positive output of the first differential amplification circuit and a positive output of the second differential amplification circuit being coupled to a negative input of the first transimpedance amplifier, a negative output of the first differential amplification circuit and a negative output of the second differential amplification circuit being coupled to a positive input of the first transimpedance amplifier;

a second transimpedance amplifier, a positive output terminal of the third differential amplification circuit and a positive output terminal of the fourth differential amplification circuit being coupled to a negative input terminal of the second transimpedance amplifier, a negative output terminal of the third differential amplification circuit and a negative output terminal of the fourth differential amplification circuit being coupled to a positive input terminal of the second transimpedance amplifier; the amplification factor of the second transimpedance amplifier is the same as that of the first transimpedance amplifier;

wherein a positive output terminal of the first transimpedance amplifier and a positive output terminal of the second transimpedance amplifier are coupled to a negative input terminal of the error amplifier, and a negative output terminal of the first transimpedance amplifier and a negative output terminal of the second transimpedance amplifier are coupled to a positive input terminal of the error amplifier.
The amplifying device according to any one of claims 7 to 9, wherein the first differential amplifying circuit includes at least one fifth transistor and at least one sixth transistor, a gate of the fifth transistor is coupled to the positive input terminal of the first differential amplifying circuit, a gate of the sixth transistor is coupled to the negative input terminal of the first differential amplifying circuit, the number of the fifth transistors is obtained by reducing the number of first transistors in the amplifying device by a first ratio, and the number of the sixth transistors is obtained by reducing the number of third transistors in the amplifying device by the first ratio;

the second differential amplifier circuit comprises at least one seventh transistor and at least one eighth transistor, the gate of the seventh transistor is coupled with the positive input terminal of the second differential amplifier circuit, the gate of the eighth transistor is coupled with the negative input terminal of the second differential amplifier circuit, the number of the seventh transistors is obtained by reducing the number of the second transistors in the amplifier device by the first ratio, and the number of the eighth transistors is obtained by reducing the number of the fourth transistors in the amplifier device by the first ratio;

the third differential amplifying circuit comprises at least one ninth transistor and at least one tenth transistor, wherein the gate of the ninth transistor is coupled with the positive input end of the third differential amplifying circuit, the gate of the tenth transistor is coupled with the negative input end of the third differential amplifying circuit, the number of the ninth transistors is obtained by reducing the number of the first transistors in the amplifying device by a second proportion, and the number of the tenth transistors is obtained by reducing the number of the third transistors in the amplifying device by the second proportion; the first ratio is m times the second ratio;

the fourth differential amplifying circuit comprises at least one eleventh transistor and at least one twelfth transistor, a gate of the eleventh transistor is coupled to the positive input terminal of the fourth differential amplifying circuit, a gate of the twelfth transistor is coupled to the negative input terminal of the fourth differential amplifying circuit, the number of the eleventh transistors is obtained by reducing the number of the second transistors in the amplifying device by the second proportion, and the number of the twelfth transistors is obtained by reducing the number of the fourth transistors in the amplifying device by the second proportion.
The amplifying apparatus according to any one of claims 7 to 10, wherein the closed loop feedback circuit further comprises:

the second current source is used for providing direct current bias for the first differential amplification circuit and the third differential amplification circuit;

a buffer for providing a dc bias to the second differential amplifier circuit and the fourth differential amplifier circuit, an input of the buffer being coupled to an output of the closed-loop feedback circuit;

the first resistor, the second resistor, the third resistor and the fourth resistor are sequentially connected in series; the first resistor is coupled to a first power source, the fourth resistor is coupled to ground, and the second resistor and the third resistor are coupled to the second current source; the ratio of the resistance values of the first resistor to the second resistor is m-1, the ratio of the resistance values of the fourth resistor to the third resistor is m-1, and the resistance values of the second resistor and the third resistor are the same; the junction of the first resistor and the first power supply is coupled to the positive input terminal of the third differential amplifier circuit, and the coupled ground terminal of the fourth resistor is coupled to the negative input terminal of the third differential amplifier circuit; the junction of the first resistor and the second resistor is coupled with the positive input end of the first differential amplifier circuit, and the junction of the third resistor and the fourth resistor is coupled with the negative input end of the first differential amplifier circuit;

the fifth resistor, the sixth resistor, the seventh resistor and the eighth resistor are sequentially connected in series; the fifth resistor is coupled to a second power supply, the eighth resistor is coupled to ground, and the sixth resistor and the seventh resistor are coupled to the output of the buffer; the ratio of the resistance values of the fifth resistor to the sixth resistor is m-1, the ratio of the resistance values of the eighth resistor to the seventh resistor is m-1, and the resistance values of the sixth resistor and the seventh resistor are the same; a junction of the fifth resistor and the second power supply is coupled to a positive input terminal of the fourth differential amplifier circuit, and a coupled ground terminal of the eighth resistor is coupled to a negative input terminal of the fourth differential amplifier circuit; the junction of the fifth resistor and the sixth resistor is coupled to the positive input terminal of the second differential amplifier circuit, and the junction of the seventh resistor and the eighth resistor is coupled to the negative input terminal of the second differential amplifier circuit.
The amplifying device according to any of claims 3 to 11, wherein the second current source is mirror-biased by the first current source.
The amplifying device according to any one of claims 1 to 12, wherein a gate of the first transistor is configured to receive the first signal, a source of the first transistor is coupled to ground, and a drain of the first transistor is coupled to a load of the amplifying device;

the source of the second transistor is coupled to the ground, and the drain of the second transistor is coupled with the load of the amplifying device;

the grid electrode of the third transistor is used for receiving the second signal, the source electrode of the third transistor is coupled to the ground, and the drain electrode of the third transistor is coupled with the load of the amplifying device;

the source of the fourth transistor is coupled to ground, and the drain of the fourth transistor is coupled to a load of the amplifying device.