CN113394287A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

Info

Publication number
CN113394287A
CN113394287A CN202010176333.5A CN202010176333A CN113394287A CN 113394287 A CN113394287 A CN 113394287A CN 202010176333 A CN202010176333 A CN 202010176333A CN 113394287 A CN113394287 A CN 113394287A
Authority
CN
China
Prior art keywords
source
initial
stress layer
layer
drain opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010176333.5A
Other languages
Chinese (zh)
Inventor
赵猛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN202010176333.5A priority Critical patent/CN113394287A/en
Publication of CN113394287A publication Critical patent/CN113394287A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor structure and method of forming the same, wherein the structure comprises: the surface of the substrate is provided with a grid structure, and two sides of the grid structure are provided with first side walls; source and drain openings in the substrate at two sides of the gate structure; the first stress layer is positioned on the surface of the side wall of the source drain opening; and the second stress layer is positioned in the source-drain opening and covers the surface of the side wall of the first stress layer, and the source-drain opening is filled with the second stress layer. The semiconductor structure has better performance.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in the integrated circuit is continuously reduced, so that the operation speed of the whole integrated circuit can be effectively increased.
In very large scale integrated circuits, the drive current of a transistor is typically increased by creating stress on the transistor, thereby increasing the carrier mobility of the transistor.
However, the performance of the semiconductor devices formed by the prior art needs to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which are used for improving the performance of a semiconductor device.
To solve the above technical problem, an embodiment of the present invention provides a semiconductor structure, including: the surface of the substrate is provided with a grid structure, and two sides of the grid structure are provided with first side walls; source and drain openings in the substrate at two sides of the gate structure; the first stress layer is positioned on the surface of the side wall of the source drain opening; and the second stress layer is positioned in the source-drain opening and covers the surface of the side wall of the first stress layer, and the source-drain opening is filled with the second stress layer.
Optionally, the material of the first stress layer includes: germanium and silicon, wherein germanium in the germanium and silicon material of the first stress layer has a first concentration; the material of the second stress layer comprises: germanium in the germanium-silicon material of the second stress layer has a second concentration, and the second concentration is greater than the first concentration; the range of the first concentration is 0.1-0.5; the second concentration is in the range of 0.4-0.8.
Optionally, the first sidewall has a second thickness; the second thickness is in a range of 3 nanometers to 7 nanometers.
Optionally, the method further includes: and the doped layer is positioned between the top surface of the substrate and the bottom of the second stress layer.
Optionally, when a distance between the first stress layers in the source-drain openings on the two sides of the gate structure is smaller than a preset value, second conductive type ions are doped in the doping layers, and the conductive types of the second conductive type ions are opposite to the conductive types of the first conductive type ions.
Optionally, when a distance between the first stress layers in the source-drain openings on the two sides of the gate structure is greater than a preset value, the doped layer is doped with first conductivity type ions.
Optionally, the source drain opening includes: the source drain opening includes: the semiconductor device comprises a first region and a second region located on the first region, wherein a source drain opening of the first region has a first distance in the extending direction of the fin portion, a source drain opening of the second region has a second distance in the extending direction of the fin portion, and the second distance is smaller than the first distance.
Optionally, the method further includes: and the second side wall is positioned on the surface of the side wall of the first side wall.
Optionally, the substrate includes a substrate and a fin portion located on a surface of the substrate, and the gate structure covers a portion of a top surface sidewall surface of the fin portion; the source and drain openings are located in the fin portions on two sides of the grid structure.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the surface of the substrate is provided with a grid structure, and two sides of the grid structure are provided with initial first side walls; etching the substrate on two sides of the gate structure by taking the initial first side wall and the gate structure as masks, and forming a source drain opening in the substrate; forming an initial first stress layer on the surface of the side wall and the surface of the bottom of the source drain opening; thinning the initial first side wall to form a first side wall; etching the initial first stress layer by taking the first side wall as a mask until the bottom surface of the source-drain opening is exposed, and forming a first stress layer on the surface of the side wall of the source-drain opening; and forming a second stress layer covering the surface of the side wall of the first stress layer in the source drain opening, wherein the source drain opening is filled with the second stress layer.
Optionally, the initial first sidewall has a first thickness, the first sidewall has a second thickness, and the second thickness is smaller than the first thickness; the first thickness is in the range of 7-12 nanometers; the second thickness is in a range of 3 nanometers to 7 nanometers.
Optionally, the initial first stress layer located on the surface portion of the sidewall of the source-drain opening has a first size, the first stress layer located on the surface portion of the sidewall of the source-drain opening has a second size, and the second size is smaller than the first size; the first size ranges from 6 nanometers to 10 nanometers; the second dimension is in a range of 3 nanometers to 6 nanometers.
Optionally, the material of the first stress layer includes: germanium and silicon, wherein germanium in the germanium and silicon material of the first stress layer has a first concentration; the material of the second stress layer comprises: and germanium in the germanium-silicon material of the second stress layer has a second concentration, and the second concentration is greater than the first concentration.
Optionally, the first concentration range is 0.1-0.5; the second concentration range is 0.4-0.8.
Optionally, the method further includes: after the first stress layer is formed and before the second stress layer is formed, carrying out an ion implantation process on the substrate exposed at the bottom of the source-drain opening, so that an initial doping layer is formed on part of the substrate at the bottom of the source-drain opening; and annealing the initial doping layer to form the doping layer on the initial doping layer.
Optionally, when a distance between the first stress layers in the source-drain openings on the two sides of the gate structure is smaller than a preset value, second conductive type ions are doped in the doping layers, and the conductive types of the second conductive type ions are opposite to the conductive types of the first conductive type ions.
Optionally, when a distance between the first stress layers in the source-drain openings on the two sides of the gate structure is greater than a preset value, the doped layer is doped with first conductivity type ions.
Optionally, the method further includes: and forming a second side wall on the surface of the side wall of the first side wall after the first stress layer is formed.
Optionally, the method for forming the source/drain opening includes: forming initial source-drain openings in the substrate on two sides of the gate structure by using the initial first side walls as masks; performing a first amorphization process on the substrate exposed at the bottom of the initial source-drain opening, so that a first amorphization layer (not shown in the figure) is formed on the substrate exposed at the bottom of the initial source-drain opening; removing the first amorphous layer to enable the initial source drain opening to form the source drain opening; and removing the first amorphous layer to enable the initial source and drain opening to form the source and drain opening.
Optionally, the method further includes: after the initial first stress layer is formed and before the initial first stress layer is etched, second non-crystallizing treatment is carried out on the initial first stress layer exposed at the bottom of the source drain opening; after the second non-crystallization treatment, etching the initial first stress layer by taking the first side wall as a mask; the second amorphization layer treatment comprises: an ion implantation process; the parameters of the ion implantation process include: the implantation angle is 5-20 degrees, the implantation angle is an included angle between the ion implantation direction and a reference surface, and the reference surface is a plane which is perpendicular to the surface of the substrate and parallel to the width direction of the channel.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the semiconductor structure provided by the technical scheme of the invention, the initial first side wall is thinned, so that the thickness of the formed first side wall is thinner. And then, etching the initial first stress layer by taking the first side wall with the smaller thickness as a mask, wherein the initial first stress layer is etched and removed relative to the exposed part of the first side wall, so that the initial first stress layer positioned on the bottom surface of the source-drain opening is removed, meanwhile, the thickness of the initial first stress layer positioned on the side wall surface of the source-drain opening is also thinned to form the first stress layer, and further the space for subsequently forming the second stress layer is correspondingly increased.
Further, a channel is formed between the adjacent source-drain openings and on the substrate at the bottom of the gate structure, and when the distance between the first stress layers in the source-drain openings at the two sides of the gate structure is smaller than a preset value, namely, the channel length is smaller. The doping layer is doped with second conductive type ions, the conductive types of the second conductive type ions are opposite to that of the first conductive type ions, and the second conductive type ions can neutralize the first conductive type ions in the first stress layer and the second stress layer, so that the influence on a channel is reduced, the short channel effect is reduced, and the performance of the formed semiconductor structure is better.
Furthermore, a channel is formed between adjacent source-drain openings and on the substrate at the bottom of the gate structure, and when the distance between the first stress layers in the source-drain openings at two sides of the gate structure is greater than a preset value, the first conductive type ions are doped in the doping layer, and the doping layer is the same as the first stress layer and the second stress layer in conductive type, so that the concentration of the first conductive type ions in the first stress layer and the second stress layer is increased, the driving current of the semiconductor structure is further improved, and the performance of the formed semiconductor structure is better.
Furthermore, after the initial first stress layer is formed, the initial first stress layer exposed at the bottom of the source-drain opening is subjected to second non-crystallization treatment, so that the material performance of the initial first stress layer positioned on the bottom surface of the source-drain opening is changed, the subsequent etching of the initial first stress layer by taking the first side wall as a mask is facilitated, the etching rate of the initial first stress layer subjected to second non-crystallization treatment is increased, and on one hand, the initial first stress layer positioned on the bottom surface of the source-drain opening is more favorably etched and removed; on the other hand, the second crystallization treatment is ion implantation with a certain inclination angle, and the second amorphization treatment can also change the material performance of the initial first stress layer positioned at the groove at the bottom of the source-drain opening, that is, the initial first stress layer positioned at the groove of the source-drain opening is also easily removed, so that the space for subsequently forming the second stress layer is increased.
Drawings
FIGS. 1-3 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure;
fig. 4 to 13 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
As described in the background, the performance of the semiconductor devices formed by the prior art needs to be improved.
Fig. 1 to 3 are schematic structural diagrams of steps of a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 100 is provided; forming a gate structure 110 on the surface of the substrate 100; and etching parts of the substrate 100 on two sides of the gate structure 110 to form an opening 120 in the substrate 10, wherein the opening 120 is exposed on the surface of the substrate 100.
Referring to fig. 2, a first stress layer 130 is formed on the sidewall surface and the bottom surface of the opening 120.
Referring to fig. 3, after the first stress layer 130 is formed, a second stress layer 140 is formed in the opening 120, and the first stress layer 130 and the second stress layer 140 form a source-drain doped layer, so that a transistor device is formed.
In the above method, the semiconductor structure is a PMOS transistor, the first stress layer 130 and the second stress layer 140 are formed by an epitaxial growth process, and the material of the first stress layer 130 includes: germanium-silicon, wherein the germanium in the germanium-silicon material has a first concentration; the material of the second stress layer 140 includes: germanium in the germanium-silicon material has a second concentration, the first concentration is smaller than the second concentration, and the first stress layer 130 with the smaller concentration is beneficial to enabling interface defects between the first stress layer 130 and the substrate 100 to be smaller, so that the first stress layer 130 serves as a buffer layer between the substrate 100 and the second stress layer 140 and is beneficial to improving interface reliability. The second stress layer 140 with a higher concentration has a higher stress, which is beneficial to improving the driving current of the device.
However, since the first stress layer 130 occupies a certain space of the source-drain opening 120, the space for forming the second stress layer 140 is smaller, so that the stress generated by the source-drain doped layer formed by the first stress layer 130 and the second stress layer 140 to the channel is still smaller, which leads to a reduction in the driving current of the transistor device, and thus, the performance of the semiconductor structure is deteriorated.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the surface of the substrate is provided with a grid structure, and two sides of the grid structure are provided with initial first side walls; etching the substrate on two sides of the gate structure by taking the initial first side wall as a mask, and forming a source drain opening in the substrate; forming an initial first stress layer on the surface of the side wall and the surface of the bottom of the source drain opening; after the initial first stress layer is formed, thinning the initial first side wall to form a first side wall; etching the initial first stress layer by taking the first side wall as a mask until the bottom surface of the source-drain opening is exposed, and forming a first stress layer on the surface of the side wall of the source-drain opening; and forming a second stress layer covering the surface of the side wall of the first stress layer in the source drain opening, wherein the source drain opening is filled with the second stress layer. The semiconductor structure formed by the method has better performance.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 13 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 4, a substrate 200 is provided, wherein a gate structure 210 is formed on a surface of the substrate 200, and initial first sidewalls 220 are formed on two sides of the gate structure 210.
In this embodiment, the base 200 includes a substrate 201 and a fin 202 located on a surface of the substrate 201, and the gate structure 210 covers a portion of a top surface and a sidewall surface of the fin 202.
In other embodiments, the substrate does not have fins thereon.
In this embodiment, the method for forming the substrate 200 includes: providing an initial substrate (not shown); the initial substrate is provided with a first patterning layer, and the first patterning layer exposes a part of the surface of the initial substrate; and etching the initial substrate by taking the first patterning layer as a mask to form the substrate 201 and the fin part 202 positioned on the surface of the substrate 201.
In this embodiment, the material of the initial substrate is silicon. Accordingly, the material of the substrate 201 and the fin 202 is silicon.
In other embodiments, the material of the initial substrate comprises: germanium, silicon on insulator or germanium on insulator. Accordingly, the material of the substrate comprises: germanium, silicon on insulator or germanium on insulator. The material of the fin portion includes: germanium, silicon on insulator or germanium on insulator.
In this embodiment, the gate structure 210 includes a gate dielectric layer 211 and a gate electrode layer 212 on the surface of the gate dielectric layer 211.
In this embodiment, the process of forming the gate dielectric layer 211 includes: a deposition process; the gate dielectric layer 211 is made of silicon oxide.
In another embodiment, the material of the gate dielectric layer includes a material with a K value greater than 3.9, such as titanium oxide, aluminum oxide, hafnium oxide, tantalum oxide, or lanthanum oxide.
In this embodiment, the material of the gate electrode layer 212 includes polysilicon.
In another embodiment, the material of the gate electrode layer includes a metal material, such as a combination of one or more of tungsten, cobalt, copper, nickel, titanium, and titanium nitride.
In this embodiment, the gate structure 210 further includes: a barrier layer 213 on a top surface of the gate electrode layer 212. The barrier layer 213 is used to protect the gate structure 210 from the process during the subsequent process, thereby maintaining a better profile.
The initial first sidewall spacers 220 are used in subsequent process steps, on one hand, to protect the gate structure 210 from the process, thereby maintaining a better profile; on the other hand, the mask is used for forming source and drain openings subsequently, so that the positions and the sizes of the source and drain openings are defined.
The material of the initial first sidewall spacer 220 includes: one or a combination of several of silicon oxide, silicon nitride, silicon oxynitride, titanium dioxide or titanium nitride.
The initial first sidewall 220 has a first thickness W1.
The first thickness W1 ranges from 7 nm to 12 nm.
Then, with the initial first sidewall 220 and the gate structure 210 as masks, the substrate 200 on both sides of the initial first sidewall 220 and the gate structure 210 is etched, a source-drain opening is formed in the substrate 200, and specifically, refer to fig. 5 to 6 for a process of forming the source-drain opening.
Referring to fig. 5, initial source/drain openings 230 are formed in the substrate 200 at two sides of the initial first sidewall 220 and the gate structure 210.
Specifically, the initial first sidewall 220 and the gate structure 210 are used as masks, the fin portions 202 on two sides of the initial first sidewall 220 and the gate structure 210 are etched until the surface of the substrate 201 is exposed, and an initial source-drain opening 230 is formed in the fin portion 202.
The process of etching the fin portion 202 with the initial first sidewall 220 and the gate structure 210 as masks includes: anisotropic dry etching process.
Referring to fig. 6, a first amorphization process is performed on the substrate 200 exposed at the bottom of the initial source-drain opening 230, so that a first amorphization layer (not shown) is formed on the substrate 200 exposed at the bottom of the initial source-drain opening 230; and removing the first amorphization layer to form the source drain opening 240 in the initial source drain opening 230.
It should be noted that, by removing the first amorphization layer, the source-drain opening 240 is formed in the initial source opening 230, and the source-drain opening 240 includes: a first region I and a second region II located on the first region I, where the first region I is a region of the source/drain opening 240 corresponding to the initial source/drain opening 230 after the first amorphized layer is removed, and the second region II is a region of the source/drain opening 240 on the first region I.
In this embodiment, the formed source/drain openings 240 of the first region I have a first distance in the fin extending direction, and the source/drain openings 240 of the second region II have a second distance in the fin extending direction, where the second distance is smaller than the first distance.
Due to the fact that the performance of the materials of the first amorphized layer and the fin portion 202 is different, an etching process adopted for subsequently removing the first amorphized layer can have different etching rates for the first amorphized layer and the fin portion 202, so that when the first amorphized layer is removed to increase the size of the initial source/drain opening 230 at the bottom along the extending direction of the fin portion 202, that is, the size of the first region I of the source/drain opening 240 along the extending direction of the fin portion 202 is increased, and etching of the initial source/drain opening 230 of the second region II cannot be caused. And then, a source-drain doping layer is formed in the source-drain opening 240 in a subsequent step, the size of the source-drain doping layer in the second region II along the extending direction of the fin portion 202 is kept unchanged, the effective length of a channel below the gate structure 210 is ensured to be longer, and therefore the short channel effect is reduced. Meanwhile, the size of the first region I of the source-drain opening 240 is increased, so that the space of the source-drain opening 240 is increased, which is beneficial to increasing the stress of the source-drain doping layer, and thus the driving current of the formed device is increased. In conclusion, the semiconductor structure has high performance.
In other embodiments, the first amorphization process may not be performed, and the substrate on both sides of the initial first sidewall and the gate structure is etched with the initial first sidewall and the gate structure as masks, so as to form the source-drain opening in the substrate.
It should be noted that, in this embodiment, a groove (not shown in the figure) is formed at the bottom of the source/drain opening 240, and an included angle a is formed between a sidewall of the groove and the bottom of the source/drain opening 240.
Referring to fig. 7, an initial first stress layer 250 is formed on the sidewall surface and the bottom surface of the source/drain opening 240.
The initial first stress layer 250 provides material for the subsequent formation of a first stress layer.
The initial first stress layer 250 at the sidewall surface portion of the source drain opening 240 has a first dimension H1.
The first dimension H1 ranges from 6 nanometers to 10 nanometers.
The material of the initial first stress layer 240 includes: silicon germanium, silicon phosphide or silicon carbide.
In this embodiment, the initial first stress layer 250 is made of silicon germanium, and germanium in the silicon germanium material of the initial first stress layer 250 has a first concentration.
The first concentration range is 0.1-0.5.
It should be noted that the germanium in the germanium-silicon material has the first concentration, which refers to the ratio of the amount of the substance of germanium to the amount of the substance of silicon.
Referring to fig. 8, a second amorphization process is performed on the initial first stress layer 250 exposed at the bottom of the source/drain opening 240.
The second amorphization layer treatment comprises: an ion implantation process; the parameters of the ion implantation process include: the implantation angle is 5 to 20 degrees, the implantation angle is an included angle between the direction of ion implantation and a reference surface, and the reference surface is a plane perpendicular to the surface of the substrate 200 and parallel to the channel width direction.
After the initial first stress layer 250 is formed, the initial first stress layer 250 exposed at the bottom of the source-drain opening 240 is subjected to second amorphization treatment, so that the material performance of the initial first stress layer 250 on the bottom surface of the source-drain opening 240 is changed, and the etching rate of the initial first stress layer 250 subjected to second amorphization treatment is increased in the subsequent process of etching the initial first stress layer 250 by using the first side wall as a mask, so that on one hand, the initial first stress layer 250 on the bottom surface of the source-drain opening 240 is removed by etching; on the other hand, the second crystallization process is ion implantation with a certain inclination angle, and the second amorphization process may also change the material properties of the initial first stress layer 250 located in the groove at the bottom of the source-drain opening 240, that is, the initial first stress layer 250 located in the groove of the source-drain opening 240 is also easily removed, so as to increase the space for subsequently forming the second stress layer.
In other embodiments, the second amorphization process may not be performed on the initial first stressed layer exposed at the bottom of the source-drain opening.
Referring to fig. 9, the initial first sidewall 220 is thinned to form a first sidewall 221.
Specifically, in this embodiment, after the second amorphization process is performed on the initial first stress layer 250, the initial first sidewall 220 is thinned to form the first sidewall 221.
The initial first sidewall 220 has a first thickness W1, the first sidewall 221 has a second thickness W2, and the second thickness W2 is smaller than the first thickness W1.
The range of the first thickness W1 is 7-12 nanometers; the second thickness W2 ranges from 3 nm to 7 nm.
In this embodiment, after the initial first stress layer 250 is formed, the initial first sidewall 220 is thinned to form a first sidewall 221, and then the initial first stress layer 250 is etched by using the first sidewall 221 as a mask.
In other embodiments, the initial first sidewall may be thinned, after the first sidewall is formed, an initial first stress layer is formed on the surface of the sidewall and the surface of the bottom of the source/drain opening, and then the initial first stress layer is etched by using the first sidewall as a mask.
Referring to fig. 10, the initial first stress layer 250 is etched by using the first sidewall 221 as a mask until the bottom surface of the source/drain opening 240 is exposed, and a first stress layer 260 is formed on the sidewall surface of the source/drain opening 240.
The first stress layer 260 located on the sidewall surface portion of the source drain opening 240 has a second dimension H2, and the second dimension H2 is smaller than the first dimension H1.
In the present embodiment, the second dimension H2 is in a range of 3 nm to 6 nm.
Since the first stress layer 260 is formed by etching the initial first stress layer 250, the initial first stress layer 250 is made of sige, and ge in the sige material of the initial first stress layer 250 has a first concentration, correspondingly, the first stress layer 260 is made of sige, and ge in the sige material of the first stress layer 260 has a first concentration.
By thinning the initial first sidewall 220, the thickness of the formed first sidewall 221 is thinner. Further, the first sidewall 221 with a smaller thickness is used as a mask to etch the initial first stress layer 250, and the portion of the initial first stress layer 250 exposed with respect to the first sidewall is etched and removed, so that the initial first stress layer 250 on the bottom surface of the source-drain opening 240 is removed, and meanwhile, the thickness of the initial first stress layer 250 on the sidewall surface of the source-drain opening 210 is also reduced to form the first stress layer 260, and further, the space for forming the second stress layer subsequently is correspondingly increased. Because the stress of the second stress layer is greater than that of the first stress layer, the increase of the space of the second stress layer is beneficial to the increase of the stress on the channel, and therefore the driving current of the formed semiconductor structure is improved.
Referring to fig. 11, an ion implantation process is performed on the substrate 200 exposed at the bottom of the source/drain opening 240, so that an initial doped layer (not shown) is formed on a portion of the substrate 200 at the bottom of the source/drain opening 240; annealing the initial doping layer to form a doping layer 270 on the initial doping layer.
The distance between the first stress layers 260 in the source-drain openings 240 on both sides of the gate structure 210 is smaller than a preset value, the doping layer 270 is doped with second conductive type ions, and the conductive types of the second conductive type ions are opposite to the conductive types of the first conductive type ions.
Because the substrate 200 between the adjacent source-drain openings 240 and at the bottom of the gate structure 210 forms a channel, when the distance between the first stress layers 260 in the source-drain openings 240 on both sides of the gate structure 210 is smaller than a preset value, that is, the channel length is smaller. By doping the doped layer 270 with second conductive type ions, and the conductive types of the second conductive type ions are opposite to the conductive types of the first conductive type ions, the second conductive type ions can neutralize the first conductive type ions in the first stress layer 260 and the second stress layer 280, so that the influence on the channel is reduced, the short channel effect is reduced, and the performance of the formed semiconductor structure is better.
In another embodiment, when the distance between the first stress layers in the source-drain openings at the two sides of the gate structure is greater than a preset value, the first conductive type ions are doped in the doped layers.
Because the substrate between the adjacent source-drain openings and at the bottom of the gate structure forms a channel, when the distance between the first stress layers in the source-drain openings at the two sides of the gate structure is greater than a preset value, the doping layer is doped with first conductive type ions, and the conductive types of the doping layer and the first stress layer are the same as the conductive types of the second stress layer, so that the concentration of the first conductive type ions in the first stress layer and the second stress layer 280 can be increased, the driving current of the semiconductor structure can be further improved, and the performance of the formed semiconductor structure is better.
In other embodiments, the doped layer may not be formed.
Referring to fig. 12, a second stress layer 280 covering the sidewall surface of the first stress layer 260 is formed in the source/drain opening 240, and the source/drain opening 240 is filled with the second stress layer 280.
In this embodiment, the second stress layer 280 also covers the surface of the doped layer 270.
The material of the second stress layer 280 comprises: germanium and silicon, and germanium in the germanium and silicon material of the second stress layer 270 has a second concentration, and the second concentration is greater than the first concentration.
The second concentration range is 0.4-0.8.
Germanium in the silicon germanium material of the first stress layer 260 has a first concentration; germanium in the silicon germanium material of the second stress layer 280 has a second concentration, and the first concentration is less than the second concentration. On one hand, the first stress layer 260 with a smaller concentration is favorable for making the interface defect between the first stress layer 260 and the substrate 200 smaller, so that the first stress layer 260 is used as a buffer layer between the substrate 200 and the second stress layer 280, and is favorable for improving the interface reliability. The second stress layer 280 with a higher concentration has a higher stress, which is beneficial to improving the driving current of the device, and the increase of the space of the second stress layer 280 is beneficial to improving the driving current of the device.
Referring to fig. 13, after the second stress layer 280 is formed, a second sidewall 222 is formed on the sidewall surface of the first sidewall 221.
The first sidewall 221 and the second sidewall 222 are used as a sidewall structure (not shown) of the gate structure 210, and the sidewall structure functions to protect the sidewall surface of the gate structure 210 and reduce the influence of the subsequent process, and on the other hand, prevent the generation of leakage current due to too short distance between the subsequently formed conductive plug and the gate structure 210.
In this embodiment, the method for forming a semiconductor structure further includes: after forming the second sidewalls 222, forming a dielectric layer (not shown) on the substrate 200; and forming a conductive plug electrically connected with the second stress layer 280 in the dielectric layer.
Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 13, including: the substrate 200, the surface of the substrate 200 has a gate structure 210, and two sides of the gate structure 210 have first sidewalls 221; source-drain openings 240 in the substrate 200 at both sides of the gate structure 210; a first stress layer 260 located on the surface of the sidewall of the source-drain opening 240; and the second stress layer 280 is positioned in the source-drain opening 240 and covers the surface of the side wall of the first stress layer 260, and the source-drain opening 240 is filled with the second stress layer 280.
The following detailed description is made with reference to the accompanying drawings.
The substrate 200 comprises a substrate 201 and a fin portion 202 located on the surface of the substrate 201, and the gate structure 210 covers part of the top surface sidewall surface of the fin portion 202; the source and drain openings 240 are located in the fin 202 at two sides of the gate structure 210.
The material of the first stress layer 260 includes: germanium-silicon, wherein germanium in the germanium-silicon material of the first stress layer 260 has a first concentration; the material of the second stress layer 280 comprises: germanium and silicon, wherein germanium in the germanium and silicon material of the second stress layer 280 has a second concentration, and the second concentration is greater than the first concentration; the first concentration range is 0.1-0.5; the second concentration range is 0.4-0.8.
The first sidewall 222 has a second thickness; the second thickness is in a range of 3 nanometers to 7 nanometers.
In this embodiment, the semiconductor structure further includes: and a doped layer 270 between the top surface of the substrate 200 and the bottom of the second stress layer 280.
In this embodiment, the distance between the first stress layers 260 in the source-drain openings 240 on both sides of the gate structure 210 is smaller than a predetermined value, the doping layer 270 is doped with second conductive type ions, and the second conductive type ions and the first conductive type ions have opposite conductive types.
In other embodiments, when the distance between the first stress layers 260 in the source-drain openings 240 on the two sides of the gate structure 210 is greater than a predetermined value, the first conductive type ions are doped in the doping layer 270.
The source-drain opening 240 includes: the source and drain openings 240 of the first region I have a first distance in the extending direction of the fin portion 202, the source and drain openings 240 of the second region II have a second distance in the extending direction of the fin portion 202, and the second distance is smaller than the first distance.
In this embodiment, the semiconductor structure further includes: and a second sidewall 222 formed on a sidewall surface of the first sidewall 221.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A semiconductor structure, comprising:
the surface of the substrate is provided with a grid structure, and two sides of the grid structure are provided with first side walls;
source and drain openings in the substrate at two sides of the gate structure;
the first stress layer is positioned on the surface of the side wall of the source drain opening;
and the second stress layer is positioned in the source-drain opening and covers the surface of the side wall of the first stress layer, and the source-drain opening is filled with the second stress layer.
2. The semiconductor structure of claim 1, wherein the material of the first stressor layer comprises: germanium and silicon, wherein germanium in the germanium and silicon material of the first stress layer has a first concentration; the material of the second stress layer comprises: germanium in the germanium-silicon material of the second stress layer has a second concentration, and the second concentration is greater than the first concentration; the range of the first concentration is 0.1-0.5; the second concentration is in the range of 0.4-0.8.
3. The semiconductor structure of claim 1, wherein the first sidewall has a second thickness; the second thickness is in a range of 3 nanometers to 7 nanometers.
4. The semiconductor structure of claim 1, further comprising: and the doped layer is positioned between the top surface of the substrate and the bottom of the second stress layer.
5. The semiconductor structure of claim 4, wherein when a distance between the first stress layers in the source-drain openings on both sides of the gate structure is smaller than a predetermined value, the doped layer is doped with second conductivity type ions, and the second conductivity type ions and the first conductivity type ions have opposite conductivity types.
6. The semiconductor structure of claim 4, wherein when a distance between the first stress layers in the source-drain openings on both sides of the gate structure is greater than a predetermined value, the doped layers are doped with first conductivity type ions.
7. The semiconductor structure of claim 1, wherein the source drain openings comprise: the semiconductor device comprises a first region and a second region located on the first region, wherein a source drain opening of the first region has a first distance in the extending direction of the fin portion, a source drain opening of the second region has a second distance in the extending direction of the fin portion, and the second distance is smaller than the first distance.
8. The semiconductor structure of claim 1, further comprising: and the second side wall is positioned on the surface of the side wall of the first side wall.
9. The semiconductor structure of claim 1, wherein the base comprises a substrate and a fin portion located on a surface of the substrate, and the gate structure covers a portion of a top surface sidewall surface of the fin portion; the source and drain openings are located in the fin portions on two sides of the grid structure.
10. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the surface of the substrate is provided with a grid structure, and two sides of the grid structure are provided with initial first side walls;
etching the substrate on two sides of the gate structure by taking the initial first side wall and the gate structure as masks, and forming a source drain opening in the substrate;
forming an initial first stress layer on the surface of the side wall and the surface of the bottom of the source drain opening;
thinning the initial first side wall to form a first side wall;
etching the initial first stress layer by taking the first side wall as a mask until the bottom surface of the source-drain opening is exposed, and forming a first stress layer on the surface of the side wall of the source-drain opening;
and forming a second stress layer covering the surface of the side wall of the first stress layer in the source drain opening, wherein the source drain opening is filled with the second stress layer.
11. The method of forming a semiconductor structure of claim 10, wherein the initial first sidewall has a first thickness, the first sidewall has a second thickness, and the second thickness is less than the first thickness; the first thickness is in the range of 7-12 nanometers; the second thickness is in a range of 3 nanometers to 7 nanometers.
12. The method for forming a semiconductor structure according to claim 10, wherein the initial first stressor layer located on the sidewall surface portion of the source-drain opening has a first dimension, the first stressor layer located on the sidewall surface portion of the source-drain opening has a second dimension, and the second dimension is smaller than the first dimension; the first size ranges from 6 nanometers to 10 nanometers; the second dimension is in a range of 3 nanometers to 6 nanometers.
13. The method of forming a semiconductor structure of claim 10, wherein the material of the first stressor layer comprises: germanium and silicon, wherein germanium in the germanium and silicon material of the first stress layer has a first concentration; the material of the second stress layer comprises: and germanium in the germanium-silicon material of the second stress layer has a second concentration, and the second concentration is greater than the first concentration.
14. The method of claim 13, wherein the first concentration range is 0.1-0.5; the second concentration range is 0.4-0.8.
15. The method of forming a semiconductor structure of claim 10, further comprising: after the first stress layer is formed and before the second stress layer is formed, carrying out an ion implantation process on the substrate exposed at the bottom of the source-drain opening, so that an initial doping layer is formed on part of the substrate at the bottom of the source-drain opening; and annealing the initial doping layer to form the doping layer on the initial doping layer.
16. The method for forming a semiconductor structure according to claim 15, wherein when a distance between the first stress layers in the source-drain openings on both sides of the gate structure is smaller than a predetermined value, the doped layer is doped with second conductivity type ions, and the second conductivity type ions and the first conductivity type ions have opposite conductivity types.
17. The method for forming a semiconductor structure according to claim 15, wherein when a distance between the first stress layers in the source-drain openings on both sides of the gate structure is greater than a predetermined value, the doped layer is doped with first conductivity type ions.
18. The method of forming a semiconductor structure of claim 10, further comprising: and forming a second side wall on the surface of the side wall of the first side wall after the first stress layer is formed.
19. The method for forming the semiconductor structure according to claim 10, wherein the method for forming the source and drain openings comprises: forming initial source-drain openings in the substrate on two sides of the gate structure by using the initial first side walls as masks; performing a first amorphization process on the substrate exposed at the bottom of the initial source-drain opening, so that a first amorphization layer (not shown in the figure) is formed on the substrate exposed at the bottom of the initial source-drain opening; removing the first amorphous layer to enable the initial source drain opening to form the source drain opening; and removing the first amorphous layer to enable the initial source and drain opening to form the source and drain opening.
20. The method of forming a semiconductor structure of claim 10, further comprising: after the initial first stress layer is formed and before the initial first stress layer is etched, second non-crystallizing treatment is carried out on the initial first stress layer exposed at the bottom of the source drain opening; after the second non-crystallization treatment, etching the initial first stress layer by taking the first side wall as a mask; the second amorphization layer treatment comprises: an ion implantation process; the parameters of the ion implantation process include: the implantation angle is 5-20 degrees, the implantation angle is an included angle between the ion implantation direction and a reference surface, and the reference surface is a plane which is perpendicular to the surface of the substrate and parallel to the width direction of the channel.
CN202010176333.5A 2020-03-13 2020-03-13 Semiconductor structure and forming method thereof Pending CN113394287A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010176333.5A CN113394287A (en) 2020-03-13 2020-03-13 Semiconductor structure and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010176333.5A CN113394287A (en) 2020-03-13 2020-03-13 Semiconductor structure and forming method thereof

Publications (1)

Publication Number Publication Date
CN113394287A true CN113394287A (en) 2021-09-14

Family

ID=77616117

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010176333.5A Pending CN113394287A (en) 2020-03-13 2020-03-13 Semiconductor structure and forming method thereof

Country Status (1)

Country Link
CN (1) CN113394287A (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102832128A (en) * 2011-06-17 2012-12-19 中芯国际集成电路制造(上海)有限公司 Manufacturing method of semiconductor device
CN103367399A (en) * 2012-03-31 2013-10-23 中芯国际集成电路制造(上海)有限公司 Transistor and method for forming same
CN103545213A (en) * 2012-07-16 2014-01-29 中国科学院微电子研究所 Semiconductor device and method for manufacturing the same
CN104124167A (en) * 2013-04-28 2014-10-29 中芯国际集成电路制造(上海)有限公司 Mos transistor and forming method thereof
US20140353732A1 (en) * 2013-05-31 2014-12-04 International Business Machines Corporation Halo region formation by epitaxial growth
CN104299970A (en) * 2013-07-17 2015-01-21 台湾积体电路制造股份有限公司 MOS devices having epitaxy regions with reduced facets
CN106856170A (en) * 2015-12-09 2017-06-16 中芯国际集成电路制造(上海)有限公司 The forming method of fin formula field effect transistor

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102832128A (en) * 2011-06-17 2012-12-19 中芯国际集成电路制造(上海)有限公司 Manufacturing method of semiconductor device
CN103367399A (en) * 2012-03-31 2013-10-23 中芯国际集成电路制造(上海)有限公司 Transistor and method for forming same
CN103545213A (en) * 2012-07-16 2014-01-29 中国科学院微电子研究所 Semiconductor device and method for manufacturing the same
CN104124167A (en) * 2013-04-28 2014-10-29 中芯国际集成电路制造(上海)有限公司 Mos transistor and forming method thereof
US20140353732A1 (en) * 2013-05-31 2014-12-04 International Business Machines Corporation Halo region formation by epitaxial growth
CN104299970A (en) * 2013-07-17 2015-01-21 台湾积体电路制造股份有限公司 MOS devices having epitaxy regions with reduced facets
CN106856170A (en) * 2015-12-09 2017-06-16 中芯国际集成电路制造(上海)有限公司 The forming method of fin formula field effect transistor

Similar Documents

Publication Publication Date Title
TWI591827B (en) Mechanisms for forming finfet device
US10741453B2 (en) FinFET device
US20060068591A1 (en) Fabrication of channel wraparound gate structure for field-effect transistor
US20200381516A1 (en) Semiconductor structure and method for forming the same
US8580634B1 (en) Methods of forming 3-D semiconductor devices with a nanowire gate structure wherein the nanowire gate structure is formed prior to source/drain formation
TWI749363B (en) Finfet having insulating layers between gate and source/drain contacts
TW201733116A (en) Semiconductor device
CN113809011B (en) Semiconductor structure and forming method thereof
CN107579108B (en) Method for forming semiconductor structure
CN114256336A (en) Semiconductor device and manufacturing method thereof
CN113314605B (en) Semiconductor structure and forming method thereof
CN111554635B (en) Semiconductor structure and forming method thereof
CN113394287A (en) Semiconductor structure and forming method thereof
US11695035B2 (en) Semiconductor structure and fabrication method thereof
CN113314595B (en) Semiconductor structure and forming method thereof
CN112652578B (en) Method for forming semiconductor structure and transistor
CN113823600B (en) Semiconductor structure, forming method thereof and mask
CN113113310B (en) Semiconductor device and method of forming the same
CN110875185B (en) Semiconductor structure and forming method thereof
CN113394271A (en) Semiconductor structure and forming method thereof
KR100516153B1 (en) Method for fabricating a SOI MOSFET device having elevated source/drain formed by using a reflow process
CN117672856A (en) Method for forming semiconductor structure
CN117637612A (en) Method for forming semiconductor structure
CN114551240A (en) Method for forming semiconductor structure
CN113764273A (en) Semiconductor structure and forming method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination