CN113394228B - Three-dimensional memory and preparation method thereof - Google Patents
Three-dimensional memory and preparation method thereof Download PDFInfo
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- CN113394228B CN113394228B CN202110628570.5A CN202110628570A CN113394228B CN 113394228 B CN113394228 B CN 113394228B CN 202110628570 A CN202110628570 A CN 202110628570A CN 113394228 B CN113394228 B CN 113394228B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Abstract
The application provides a three-dimensional memory and a preparation method thereof. The method comprises the following steps: forming a stacked structure including dielectric layers and sacrificial layers alternately stacked on a substrate, and forming a channel hole penetrating the stacked structure; removing a portion of the sacrificial layer facing the channel hole through the channel hole to form a first trench; sequentially forming a barrier layer and a charge trapping layer in the first trench; and forming a tunneling layer on sidewalls of the channel hole to cover the charge trapping layer and the blocking layer. The three-dimensional memory and the preparation method thereof can effectively inhibit charge diffusion in the charge trapping layer corresponding to each gate layer, thereby improving the storage reliability of the charge trapping layer and further improving the storage and retention characteristics of the prepared three-dimensional memory.
Description
Technical Field
The present application relates to the field of semiconductor technology, and more particularly, to a three-dimensional memory and a method for fabricating the same.
Background
The functional layer of the channel structure in the three-dimensional memory (3D NAND) is a critical structure in which the memory function is actually implemented. Specifically, the functional layers comprise a silicon oxide-silicon nitride-silicon oxide (ONO) structure from the inside to the outside in the radial direction, and each gate layer may be in contact with a corresponding functional layer of the ONO structure to form a memory cell. In addition, the grid layer can control the corresponding ONO structure to realize the storage function in a charge capturing mode.
In the prior art, a silicon nitride layer is generally used as a charge trap (SiN charge trap) to hold charges (holes or electrons) in a charge trapping layer. However, during the storage process, the charges stored in the charge traps may laterally diffuse (laterally diffuse) in the axial direction of the channel structure, which may cause the storage reliability of the charge trapping layer corresponding to the gate layer to be reduced, thereby reducing the retention (retention) characteristics of the three-dimensional memory.
Therefore, how to improve the lateral diffusion of charges in the charge traps is one of the technical problems that the skilled person is trying to solve.
Disclosure of Invention
The application provides a preparation method of a three-dimensional memory. The preparation method comprises the following steps: forming a laminated structure including dielectric layers and sacrificial layers alternately stacked on a substrate, and forming a channel hole penetrating the laminated structure; removing a portion of the sacrificial layer facing the channel hole through the channel hole to form a first trench; sequentially forming a barrier layer and a charge trapping layer in the first trench; and forming a tunneling layer on sidewalls of the channel hole to cover the charge trapping layer and the blocking layer.
In some embodiments, the step of sequentially forming the blocking layer and the charge trapping layer within the first trench may include: forming a barrier layer on the inner wall of the first trench; and forming a charge trapping layer in the first trench in which the blocking layer is formed.
In some embodiments, the step of sequentially forming the blocking layer and the charge trapping layer within the first trench may include: forming a blocking layer and a charge trapping layer on the side wall of the channel hole and the inner wall of the first trench in sequence; and removing portions of the blocking layer and the charge trapping layer on sidewalls of the channel hole.
In some embodiments, the sequentially forming a blocking layer and a charge trapping layer within the first trench may further include: a portion of the barrier layer on the inner wall of the first trench and toward the channel hole is removed to form a second trench.
In some embodiments, forming a tunneling layer on sidewalls of the channel hole to cover the charge trapping layer and the blocking layer may include: and forming the tunneling layer in the second groove.
In some embodiments, the step of sequentially forming the blocking layer and the charge trapping layer within the first trench may include: a blocking layer and a charge trapping layer are sequentially formed on a surface of the first trench facing the channel hole such that the blocking layer and the charge trapping layer are in contact with the adjacent dielectric layer.
The application also provides a three-dimensional memory. The three-dimensional memory includes: a substrate; a stacked structure on the substrate, including dielectric layers and gate layers stacked alternately; a channel structure, through the stack structure, comprising: a dielectric core; a tunneling layer surrounding the dielectric core; the charge trapping layer and the blocking layer are sequentially positioned outside the tunneling layer; wherein the charge trapping layer comprises a plurality of charge trapping moieties, the blocking layer comprises a plurality of blocking moieties, and the charge trapping moieties and the blocking moieties are located between adjacent dielectric layers.
In some embodiments, the blocking portion may at least partially surround the charge trapping portion, and the tunneling layer extends between the adjacent dielectric layers in a direction toward the blocking layer and surrounds the charge trapping portion together with the blocking portion.
In some embodiments, the charge trapping part and the blocking part may be located on the surface of the tunneling layer in order from inside to outside in the radial direction of the dielectric core and both in contact with the adjacent dielectric layer.
In some embodiments, a surface of the blocking layer in contact with the gate layer may have a predetermined distance from a surface of the tunneling layer in contact with the dielectric layer.
In some embodiments, the material of the blocking layer may include silicon oxide, the material of the charge trapping layer may include silicon nitride, and the material of the tunneling layer may include silicon oxide.
According to the three-dimensional memory and the preparation method thereof, the groove is formed in the sacrificial layer, the charge trapping layer is formed in the groove, and the charge trapping layer is located between the adjacent dielectric layers, so that the transverse diffusion of charges in the charge trapping layer corresponding to the gate layer can be effectively inhibited, the storage reliability of the charge trapping layer is improved, and the retention characteristic of the prepared three-dimensional memory is improved.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
FIG. 1 is a schematic diagram of a lateral diffusion of charge for a conventional three-dimensional memory;
FIG. 2 is a flow chart of a method of fabricating a three-dimensional memory according to an embodiment of the present application;
fig. 3A to 3F are schematic process cross-sectional views illustrating a method for fabricating a three-dimensional memory according to an embodiment of the present disclosure;
FIG. 4 is a schematic process cross-sectional view illustrating a method for fabricating a three-dimensional memory according to another embodiment of the present application; and
FIG. 5 is a schematic cross-sectional view of a trench structure after formation in accordance with an embodiment of the present application; and
fig. 6 is a schematic cross-sectional view of a gate replacement operation according to an embodiment of the present disclosure.
Detailed Description
For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way.
The terminology used herein is for the purpose of describing particular example embodiments and is not intended to be limiting. The terms "comprises," "comprising," "includes" and/or "including," when used in this specification, specify the presence of stated features, integers, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, elements, components, and/or groups thereof.
This description is made with reference to schematic illustrations of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the particular shapes and dimensions shown, but are to include various equivalent structures capable of performing the same function, as well as deviations in shapes and dimensions that result, for example, from manufacturing. The locations shown in the drawings are schematic in nature and are not intended to limit the location of the various components.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Fig. 1 is a schematic diagram illustrating a charge lateral diffusion principle of a conventional three-dimensional memory. As shown in fig. 1, the conventional three-dimensional memory may include a channel structure 1, a gate layer 2 in contact with the channel structure 1, and a dielectric layer 3 between adjacent gate layers 2. Specifically, the channel structure 1 may include a dielectric core 4, and a channel layer 5, a tunneling layer 6, a charge trapping layer 7, and a blocking layer 8, which are located outside the dielectric core 4 in this order and extend along an axial direction of the dielectric core 4. The gate layer 2 may contact the blocking layer 8 in the channel structure 1, and form a memory cell n with the corresponding blocking layer 8, charge trapping layer 7, and tunneling layer 6.
In the programming operation of the memory cell n, a high voltage may be applied to the memory cell n through the gate layer 2, and charges in the channel layer 5 may be injected into the charge trap layer 7 and retained in the charge trap layer 7 under the action of an electric field, thereby implementing the programming of the memory cell n.
However, in the process of programming the memory cell n, the fringe electric field of the gate layer 2 corresponding to the memory cell n causes a case where there is charge injection (in the direction indicated by arrow (r) in fig. 1) at the position of the dielectric layer 3 adjacent thereto, so that there is a case where the charge to be injected into the memory cell n is laterally diffused in the axial direction of the dielectric core 4. And this situation is exacerbated as the voltage applied to the gate layer 2 increases.
On the other hand, as the number of stacked layers of the three-dimensional memory is increased, the thicknesses of the dielectric layer 3 and the gate layer 2 are also reduced to reduce the stress effect and control the cost. The interaction among the memory cells is enhanced, and the phenomenon of lateral diffusion in the charge trapping layer 7 along the axial direction of the channel structure 1 is more obvious (the direction shown by an arrow in fig. 1), thereby causing the retention characteristic of the three-dimensional memory to be lowered.
In addition, the diffusion phenomenon of the conventional three-dimensional memory tends to be aggravated in a high-temperature environment. Illustratively, the storage medium in the three-dimensional memory can be preserved for only three months to one year at 30 ℃. Although the three-dimensional memory can solve the problem of storage duration through periodic refreshing or frequent backup, the lateral charge diffusion is still one of the technical problems of poor retention characteristics of the three-dimensional memory due to the physical structure.
Based on the above technical problem, the present application provides a method 1000 for manufacturing a three-dimensional memory. Fig. 2 is a flowchart of a method 1000 for fabricating a three-dimensional memory according to an embodiment of the present application. As shown in fig. 2, a method 1000 for fabricating a three-dimensional memory includes the following steps.
S110, forming a laminated structure comprising dielectric layers and sacrificial layers which are alternately stacked on the substrate, and forming a channel hole penetrating through the laminated structure.
S120, a portion of the sacrificial layer facing the channel hole is removed through the channel hole to form a first trench.
And S130, sequentially forming a blocking layer and a charge trapping layer in the first groove.
And S140, forming a tunneling layer on the side wall of the channel hole to cover the charge trapping layer and the blocking layer.
Fig. 3A to 3F are schematic process cross-sectional views illustrating a method 1000 for fabricating a three-dimensional memory according to an embodiment of the present disclosure. Fig. 3B to 3F are partially enlarged views of the area a in fig. 3A. It should be understood that the steps shown in the method 1000 of preparation are not exclusive and that other steps may be performed before, after, or between any of the steps shown. Further, some of the steps may be performed simultaneously or may be performed in a different order than shown in fig. 2. The above-described steps S110 to S140 will be described in detail with reference to fig. 3A to 3F.
S110, forming a laminated structure including dielectric layers and sacrificial layers alternately stacked on a substrate and forming a penetration
A channel hole of the stacked structure.
In step S110, as shown in fig. 3A, the substrate 10 may be used to support device structures thereon. The substrate 10 may be a single crystal silicon (Si) substrate, a single crystal germanium (Ge) substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or the like. The material of the substrate 10 may also be a compound semiconductor. For example, the substrate 10 may be a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, a silicon carbide (SiC) substrate, or the like. It is noted that the substrate 10 described herein may also be fabricated using at least one of the other semiconductor materials known in the art. Further, the substrate 10 may also be a semiconductor substrate doped with P-type or N-type dopants.
The stacked structure 20 may include a plurality of dielectric layers 21 and a plurality of sacrificial layers 22 overlapped in a direction perpendicular to the substrate 10. The formation method of the stacked structure 20 may include a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof. In the stacked structure 20, the thicknesses of the dielectric layers 21 may be the same or different, and the thicknesses of the sacrificial layers 22 may be the same or different, and may be set according to specific process requirements. In addition, in the manufacturing process of the stacked structure 20, different stacking layers correspond to different stacking heights, for example, the number of stacked layers of the stacked structure 20 may be 8, 32, 64, 128, and the like, the greater the number of stacked layers of the stacked structure 20, the higher the integration level, the greater the number of memory cells formed therefrom, and the stacking layers and the stacking heights of the stacked structure 20 may be designed according to actual memory requirements, which is not specifically limited in the present application.
In some embodiments, the dielectric layer 21 and the sacrificial layer 22 may have different etching selectivity, and the sacrificial layer 22 may be removed and replaced by a conductive material in a subsequent process, thereby forming a gate layer, i.e., a word line. Alternatively, the material of the dielectric layer 21 may include silicon oxide, and the material of the sacrificial layer 22 may include silicon nitride.
In this step, a channel hole 31 vertically penetrating the stacked structure 20 may be formed using, for example, a wet etching process or a dry etching process such as plasma etching, ion mill etching, and reactive ion etching, and the channel hole 31 may extend to the substrate 10, thereby exposing the substrate 10.
S120, a portion of the sacrificial layer facing the channel hole is removed through the channel hole to form a first trench.
In step S120, as shown in fig. 3B, a portion of the sacrificial layer 22 facing the channel hole 31 may be removed using, for example, a wet etching process or a dry etching process such as plasma etching, ion mill etching, and reactive ion etching, using the channel hole 31 formed in step S110 described above, thereby forming the first trench 23. The first trench 23 may be composed of surfaces of adjacent dielectric layers 21 and a surface of the sacrificial layer 22 located between the adjacent dielectric layers 21.
In some embodiments, a surface of the first trench 23 facing the channel hole 31 may have a predetermined distance, for example, 20nm, from a sidewall of the channel hole 31. The first channel 23 may be used to accommodate a blocking layer and a charge trapping layer formed during subsequent processes.
And S130, sequentially forming a blocking layer and a charge trapping layer in the first groove.
In step S130, a blocking layer and a charge trapping layer may be sequentially formed within the first trench 23 in a direction toward the channel hole using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, such that the charge trapping layer is formed between adjacent dielectric layers 21 in the stacked-layer structure 20. It is understood that the charge trap layer, which serves as a structure for storing charges, is formed between the adjacent dielectric layers 21 to advantageously prevent the charges stored therein from being laterally diffused in the axial direction of the channel hole 31.
In some embodiments, the step of forming the blocking layer and the charge trapping layer may comprise: a blocking layer is formed on an inner wall of the first trench 23 and a charge trap layer is formed in the first trench 23 in which the blocking layer is formed.
In the step of forming the barrier layer on the inner walls of the first trenches 23, as shown in fig. 3C, the barrier layer 32 may be formed on the inner walls of the first trenches 23 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The barrier layer 32 may be selected from, for example, silicon oxide (SiO)x) And (4) preparation. Alternatively, during the process of forming the barrier layer 32 on the inner wall of the first trench 23, the same process method may be used to form the barrier layer 32 on the sidewall of the trench hole 31, thereby forming a continuous layer structure covering the inner wall of the first trench 23 and the sidewall of the trench hole 31.
In the step of forming the charge trap layer within the first trench 23 in which the blocking layer 32 is formed, as shown in fig. 3D, a charge trap layer 33 may be formed within the first trench 23 in which the blocking layer 32 is formed using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The charge trapping layer 33 may be, for example, silicon nitride (SiN)x) And (4) preparation. Alternatively, during the process of forming the charge trap layer 33 in the first trench 23, the same process method may be used to further form the surface of the barrier layer 32 on the sidewall of the channel layer 31The charge trap layer 33 is formed such that the charge trap layer 33 filled in the first trench 23 and located on the sidewall of the channel hole 31 has a continuous layer structure.
In some embodiments, as shown in fig. 3E, after the blocking layer 32 and the charge trapping layer 33 are sequentially formed on the sidewalls of the channel hole 31, the blocking layer 32 and the charge trapping layer 33 on the sidewalls of the channel hole 31 may be removed using, for example, a dry or wet etching process, so as to ensure that the charge trapping layer 33 is located between the adjacent dielectric layers 21. Alternatively, the same process method may be used to form the second trench 24 formed by the surfaces of the dielectric layer 21, the blocking layer 32, and the charge trapping layer 33 by removing a portion of the blocking layer 32 on the inner wall of the first trench 23 and toward the channel hole 31 while removing portions of the blocking layer 32 and the charge trapping layer 33 on the sidewall of the channel hole 31. The second trench 24 may include two portions adjacent to the adjacent dielectric layer 21.
And S140, forming a tunneling layer on the side wall of the channel hole to cover the charge trapping layer and the blocking layer.
In step S140, as shown in fig. 3F, a tunneling layer 34 may be formed on the sidewalls of the channel hole 31 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, so as to cover the blocking layer 32 and the charge trapping layer 33 formed within the first trench 23. The tunneling layer 34 can be made of silicon oxide (SiO)x) And (4) preparation. In addition, the tunneling layer 34 may further contact the charge trapping layer 33, and together with the blocking layer 32 and the charge trapping layer 33 formed in the first trench 23, constitute a functional layer of a channel structure formed in a subsequent process for implementing a memory function.
In some embodiments, during the process of forming the tunneling layer 34 on the sidewall of the trench hole 31, the tunneling layer 34 may be formed in the second trench 24 formed in step S130 by using the same process. In other words, the tunneling layer 34 may extend between adjacent dielectric layers 21 and surround the charge trapping layer 33 together with the blocking layer 32. It should be appreciated that an etching process may be used to remove portions of the tunneling layer 34 corresponding to the dielectric layer 21 so that the tunneling layer 34 remains on the sidewalls of the channel hole and corresponds to the sacrificial layer 22, thereby forming the tunneling layer 34 into a discrete layer structure on the sidewalls of the channel hole.
Fig. 4 is a schematic process cross-sectional view illustrating a method for fabricating a three-dimensional memory according to another embodiment of the present application. As shown in fig. 4, a blocking layer 32 and a charge trap layer 33 may be sequentially formed on a surface of the first trench 23 facing the channel hole 31 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, such that the blocking layer 32 is in contact with the sacrificial layer 22 and the adjacent dielectric layer 21, and such that the charge trap layer 33 is in contact with the blocking layer 32 and the adjacent dielectric layer 21. After the above processes, the surface of the charge trapping layer 33 facing the channel hole 31 may be flush with the sidewall of the channel hole 31, so that the tunneling layer 34 is formed on the sidewall of the channel hole 31. Alternatively, the surface of the charge trap layer 33 facing the channel hole 31 may have a predetermined distance from the sidewall of the channel hole 31. In other words, the charge trapping layer 33 may form a trench with the adjacent dielectric layer 21 such that the tunneling layer 34 extends further into the trench while being formed on the sidewalls of the channel hole 31 and in contact with the charge trapping layer 33 and the adjacent dielectric layer 21. Alternatively, a portion of the sacrificial layer 22 may be oxidized such that the oxidized portion of the sacrificial layer 22 forms the barrier layer 32.
In some embodiments, the method 1000 for manufacturing a three-dimensional memory provided in the embodiments of the present application may further include a step of forming a channel structure. Fig. 5 is a schematic cross-sectional view of a channel structure after formation according to an embodiment of the present application.
In this step, as shown in fig. 5, before the step of forming the functional layer composed of the blocking layer 32, the charge trapping layer 33, and the tunneling layer 34 using the above-described process method 1000, an epitaxial layer 35 may be formed at the bottom of the channel hole 31 using, for example, a Selective Epitaxial Growth (SEG) process, the epitaxial layer 35 may cover a previously formed active region of the substrate 10 exposed in the step of forming the channel hole 31, and the epitaxial layer 35 may correspond to the at least one sacrificial layer 22. The epitaxial layer 35 may form a bottom select transistor of the channel structure 30 with its corresponding sacrificial layer 22. In addition, the epitaxial layer 35 may form an electrical coupling region between the channel layer 36 and the substrate 10. It should be understood that the substrate 10 may be a P-type substrate in the case where the channel layer 36 and the substrate 10 form a circuit loop using a selective epitaxial growth process. In addition, the substrate 10 may also be an N-type substrate or a composite substrate structure, and the process of forming the channel layer 36 in the channel structure 30 and the substrate 10 into a circuit loop is not specifically limited in this application.
Further, a functional layer composed of the blocking layer 32, the charge trapping layer 33 and the tunneling layer 34 may be formed by the above-mentioned process 1000, and may also be formed on the surface of the epitaxial layer 35 away from the substrate 10.
Further, a portion of the functional layer at the surface of the epitaxial layer 35 remote from the substrate 10 may be removed using, for example, a dry or wet etching process to form an opening exposing the epitaxial layer 35. Optionally, during the process of removing a portion of the functional layer located on the surface of the epitaxial layer 35 remote from the substrate 10, the opening may also be extended further into the epitaxial layer 35.
Further, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be employed to form the channel layer 36 at the opening formed in the above step and at the surface of the tunneling layer 34 within the channel hole 31. The material of the channel layer 36 may be made of polysilicon. It should be understood that the material of the channel layer 36 is not limited thereto, and may be made of other conductive materials.
Further, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to fill the trench hole 31 with a dielectric material such as silicon oxide (SiO)x) To form a channel structure 30. Optionally, one or more air gaps may be formed during the filling process to relieve structural stress by controlling the filling process.
In some embodiments, a portion of the dielectric material filled in the channel hole 31 away from the substrate 10 may be etched back and filled with a conductive material using, for example, a dry or wet etching process, thereby forming a channel plug (not shown) in contact with the channel layer 36. The channel plug may be made of the same material as the channel layer 36, such as polysilicon, and may serve as a drain terminal of the channel structure 30.
In some embodiments, the method 1000 for manufacturing a three-dimensional memory provided by the embodiments of the present application may further include a step of performing a "gate replacement" operation. Fig. 6 is a schematic cross-sectional view of a gate replacement operation according to an embodiment of the present disclosure.
In this step, as shown in fig. 6, a gate slit (not shown) extending through the stacked structure 20 and to the substrate 10 may be formed using, for example, a dry or wet etching process. Further, the gate slits formed after the above process can be used as a passage for an etchant, and the sacrificial layer 22 in the stacked-layer structure 20 can be removed by, for example, a wet etching process to form a plurality of sacrificial gaps. Further, the gate layer 24 may be formed by filling the sacrificial gap with a conductive material using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The gate layer 24 may be made of materials such as tungsten, cobalt, copper, aluminum, or doped crystalline silicon. After the above process, the sacrificial layer 22 in the stacked structure 20 can be replaced by the gate layer 24. The gate layer 24 is in contact with the channel structure 30. More specifically, the gate layer 24 may contact the blocking layer 32 in the channel structure 30 and control a memory cell including the blocking layer 32, the charge trapping layer 33, and the tunneling layer 34 in the channel structure 30, so that the charge trapping layer 33 in the memory cell can be in a storage state in a charge-retaining manner.
According to the preparation method of the three-dimensional memory, the groove is formed in the sacrificial layer, the charge trapping layer is formed in the groove, the charge trapping layer is located between the adjacent dielectric layers, the transverse diffusion of charges in the charge trapping layer corresponding to the grid layer can be effectively inhibited, the storage reliability of the charge trapping layer is improved, and the retention characteristic of the prepared three-dimensional memory is improved.
The application also provides a three-dimensional memory. The three-dimensional memory can be obtained by any one of the above-described manufacturing methods. The three-dimensional memory may include: a substrate, a stack structure and a channel structure.
The stacked structure is located on the substrate and includes dielectric layers and gate layers which are alternately stacked. A channel structure extends through the stack. The channel structure includes: the charge trapping layer includes a dielectric core, a tunneling layer surrounding the dielectric core, and a charge trapping layer and a blocking layer located sequentially outside the tunneling layer. The charge trapping layer comprises a plurality of charge trapping parts, the blocking layer comprises a plurality of blocking parts, and the charge trapping parts and the blocking parts are located between the adjacent dielectric layers, so that the charge trapping parts are spaced by the adjacent dielectric layers, the transverse diffusion of charges in the charge trapping parts corresponding to the gate layer can be effectively inhibited, and the storage reliability of the charge trapping layer is improved. At the same time, the retention characteristics of the three-dimensional memory can be improved.
Since the contents and structures referred to in the above description of the method 1000 may be fully or partially applicable to the three-dimensional memory described herein, the contents related or similar thereto will not be described in detail.
The above description is only a preferred embodiment of the present application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.
Claims (8)
1. The preparation method of the three-dimensional memory is characterized by comprising the following steps:
forming a stacked structure including dielectric layers and sacrificial layers alternately stacked on a substrate, and forming a channel hole penetrating the stacked structure;
removing a portion of the sacrificial layer facing the channel hole through the channel hole to form a first trench;
sequentially forming a blocking layer and a charge trapping layer in the first trench, the charge trapping layer including a plurality of charge trapping portions, the blocking layer including a plurality of blocking portions, the blocking portions at least partially surrounding the charge trapping portions; and
and forming a tunneling layer on the side wall of the channel hole and extending to the direction of the blocking layer and between the adjacent dielectric layers so as to cover the charge trapping layer and the blocking layer and surround the charge trapping part together with the blocking part.
2. The method of claim 1, wherein the step of sequentially forming a blocking layer and a charge trapping layer in the first trench comprises:
forming the barrier layer on the inner wall of the first trench; and
forming the charge trap layer in the first trench in which the blocking layer is formed.
3. The method of claim 1, wherein the step of sequentially forming a blocking layer and a charge trapping layer in the first trench comprises:
forming the blocking layer and the charge trapping layer in sequence on the side wall of the channel hole and the inner wall of the first trench; and
removing portions of the blocking layer and the charge trapping layer on sidewalls of the channel hole.
4. The method of claim 2 or 3, wherein the step of sequentially forming a blocking layer and a charge trapping layer in the first trench further comprises:
removing a portion of the barrier layer on an inner wall of the first trench and toward the channel hole to form a second trench.
5. The method of claim 4, wherein forming a tunneling layer on sidewalls of the channel hole to cover the charge trapping layer and the blocking layer comprises:
and forming the tunneling layer in the second groove.
6. A three-dimensional memory, comprising:
a substrate;
the stacked structure is positioned on the substrate and comprises dielectric layers and gate layers which are alternately stacked;
a channel structure extending through the stack structure, comprising:
a dielectric core;
a tunneling layer surrounding the dielectric core; and
the charge trapping layer and the blocking layer are sequentially positioned outside the tunneling layer;
wherein the charge trapping layer comprises a plurality of charge trapping moieties, the blocking layer comprises a plurality of blocking moieties, and the charge trapping moieties and the blocking moieties are located between adjacent dielectric layers;
the blocking portion at least partially surrounds the charge trapping portion, and the tunneling layer extends between the adjacent dielectric layers in a direction toward the blocking portion and surrounds the charge trapping portion together with the blocking portion.
7. The three-dimensional memory according to claim 6,
the surface of the blocking layer in contact with the gate layer has a predetermined distance from the surface of the tunneling layer in contact with the dielectric layer.
8. The three-dimensional memory according to claim 6, wherein the material of the blocking layer comprises silicon oxide, the material of the charge trapping layer comprises silicon nitride, and the material of the tunneling layer comprises silicon oxide.
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110628570.5A CN113394228B (en) | 2021-06-07 | 2021-06-07 | Three-dimensional memory and preparation method thereof |
| CN202180003162.9A CN113924646A (en) | 2020-10-19 | 2021-08-31 | Three-dimensional memory device and method for forming the same |
| PCT/CN2021/115807 WO2022083299A1 (en) | 2020-10-19 | 2021-08-31 | Three-dimensional memory device and method for forming the same |
| CN202180003163.3A CN113924647B (en) | 2020-10-19 | 2021-08-31 | Three-dimensional memory device and method for forming the same |
| PCT/CN2021/115782 WO2022083298A1 (en) | 2020-10-19 | 2021-08-31 | Three-dimensional memory device and method for forming the same |
| US17/488,879 US20220123016A1 (en) | 2020-10-19 | 2021-09-29 | Three-dimensional memory device and method for forming the same |
| US17/488,915 US20220123017A1 (en) | 2020-10-19 | 2021-09-29 | Three-dimensional memory device and method for forming the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110628570.5A CN113394228B (en) | 2021-06-07 | 2021-06-07 | Three-dimensional memory and preparation method thereof |
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| CN105723511A (en) * | 2013-12-24 | 2016-06-29 | 英特尔公司 | Memory strucutre with self-aligned floating and control gates and associated methods |
| US20180374863A1 (en) * | 2017-06-26 | 2018-12-27 | Applied Materials, Inc. | 3d flash memory cells which discourage cross-cell electrical tunneling |
| CN111987106A (en) * | 2020-08-24 | 2020-11-24 | 维沃移动通信有限公司 | Memory and manufacturing method thereof |
| US20210066346A1 (en) * | 2019-09-03 | 2021-03-04 | Samsung Electronics Co., Ltd. | Semiconductor devices including separate charge storage layers |
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| US8946807B2 (en) * | 2013-01-24 | 2015-02-03 | Micron Technology, Inc. | 3D memory |
| US10680009B2 (en) * | 2017-08-23 | 2020-06-09 | Yangtze Memory Technologies Co., Ltd. | Method for forming gate structure of three-dimensional memory device |
| WO2022099463A1 (en) * | 2020-11-10 | 2022-05-19 | Yangtze Memory Technologies Co., Ltd. | Channel structures having protruding portions in three-dimensional memory device and method for forming the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105723511A (en) * | 2013-12-24 | 2016-06-29 | 英特尔公司 | Memory strucutre with self-aligned floating and control gates and associated methods |
| US20180374863A1 (en) * | 2017-06-26 | 2018-12-27 | Applied Materials, Inc. | 3d flash memory cells which discourage cross-cell electrical tunneling |
| US20210066346A1 (en) * | 2019-09-03 | 2021-03-04 | Samsung Electronics Co., Ltd. | Semiconductor devices including separate charge storage layers |
| CN111987106A (en) * | 2020-08-24 | 2020-11-24 | 维沃移动通信有限公司 | Memory and manufacturing method thereof |
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