CN111987106A - Memory and manufacturing method thereof - Google Patents
Memory and manufacturing method thereof Download PDFInfo
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- CN111987106A CN111987106A CN202010859679.5A CN202010859679A CN111987106A CN 111987106 A CN111987106 A CN 111987106A CN 202010859679 A CN202010859679 A CN 202010859679A CN 111987106 A CN111987106 A CN 111987106A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Abstract
The application discloses a memory and a manufacturing method thereof, and belongs to the technical field of semiconductor manufacturing. The memory device comprises a substrate, a stack layer and a channel, wherein the stack layer is arranged on the substrate and comprises isolation layers and first storage gate layers which are alternately stacked along a first direction; the channel is arranged on the substrate and penetrates through the stacking layer, a second storage grid layer, a barrier layer, an electron capture layer, an electron tunneling layer and a conductive channel layer are sequentially stacked on a first portion of the channel along a second direction, the channel comprises first functional layers, a first distance exists between every two first functional layers along the first direction, and each first functional layer comprises a second storage grid layer, a barrier layer and an electron capture layer; wherein the first memory gate layer of the stack layer corresponds to the second memory gate layer of the channel. The memory can effectively reduce the electron escape phenomenon between the adjacent second storage gate layers, thereby effectively improving the reliability of the data stored by the memory.
Description
Technical Field
The application belongs to the technical field of semiconductor manufacturing, and particularly relates to a memory and a manufacturing method thereof.
Background
In recent years, with the rapid development of flash memories, the structure of three-dimensional (3D) flash memories has been rapidly developed, wherein the memories are increasingly widely used in semiconductor devices. The memory is a flash memory device with a three-dimensional stack structure, the memory device is a device which stacks multiple planes of memory cells to realize larger storage capacity and lower cost per bit, the highest 32 layers can be stacked, the storage space of the highest 32GB can be increased on a single MLC flash memory chip, and the storage space of the single TLC flash memory chip can be increased by 48 GB. At present, the manufacturing process of the memory is mainly divided into a replacement gate process and a non-replacement gate process. For the replacement gate process, the inventors found that at least the following problems exist in the prior art: because all the structures in the functional layer are formed in the channel holes, and the electron capture layer in the functional layer is an integral structure spanning all the storage units, electrons captured in one storage unit can easily escape to the adjacent storage unit through the electron capture layer, and data storage errors occur.
Disclosure of Invention
An object of the embodiments of the present application is to provide a memory and a method for manufacturing the same, so as to solve the technical problem in the prior art that electrons are easy to escape from the memory.
In order to solve the technical problem, the present application is implemented as follows:
in a first aspect, an embodiment of the present application provides a memory, which includes:
a substrate;
a stack layer disposed on the substrate, the stack layer including an isolation layer and a first memory gate layer alternately stacked in a first direction;
a channel disposed on the substrate and penetrating through the stack layer, wherein a second storage gate layer, a blocking layer, an electron trapping layer, an electron tunneling layer, and a conductive channel layer are sequentially stacked on a first portion of the channel along a second direction, the channel includes first functional layers, a first distance exists between every two first functional layers along the first direction, and the first functional layers include the second storage gate layer, the blocking layer, and the electron trapping layer;
wherein the first memory gate layer of the stack layer corresponds to the second memory gate layer of the channel.
In a second aspect, an embodiment of the present application provides a method for manufacturing a memory, which includes the following steps:
providing a substrate; forming a preset stacking layer on the substrate, wherein the preset stacking layer comprises isolation layers and sacrificial layers which are alternately arranged; etching a channel hole through the preset stack layer along a first direction and exposing the substrate; replacing a sacrificial layer in the preset stacking layer with a first storage gate layer, wherein the isolation layer and the first storage gate layer form a stacking layer; etching and removing a part of each first storage grid layer close to the channel hole on two sides of the channel hole to form a notch part; and filling and forming a barrier layer and an electron capture layer in each gap part along the second direction, and filling and forming an electron tunneling layer and a conductive channel layer in the channel hole.
The technical scheme adopted by the application can achieve the following beneficial effects:
in the memory provided by the embodiment of the application, the first functional layers including the second storage gate layers, the barrier layers and the electron capture layers are not arranged to penetrate through the stack layers, but a first distance is arranged between every two adjacent first functional layers along the first direction, that is, the first functional layers are in a discrete structure, that is, an independent barrier layer and an electron capture layer are formed corresponding to each second storage gate layer, and the electron capture layers between different second storage gate layers are separated, so that the electron escape phenomenon between the adjacent second storage gate layers can be effectively reduced, and the reliability of data stored by the memory is effectively improved.
Drawings
FIG. 1 is a first schematic diagram illustrating a manufacturing process of a memory according to an embodiment of the present disclosure;
FIG. 2 is a second schematic diagram illustrating a manufacturing process of a memory according to an embodiment of the present disclosure;
FIG. 3 is a third schematic diagram illustrating a manufacturing process of a memory according to an embodiment of the present disclosure;
FIG. 4 is a fourth schematic view illustrating a manufacturing process of a memory according to an embodiment of the present disclosure;
FIG. 5 is a fifth schematic diagram illustrating a manufacturing process of a memory according to an embodiment of the present disclosure;
fig. 6 is a sixth schematic view illustrating a manufacturing process of a memory according to an embodiment of the present application;
FIG. 7 is a schematic structural diagram of a memory according to an embodiment of the present application;
fig. 8 is a schematic partial structure diagram of a memory according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms first, second and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application are capable of operation in sequences other than those illustrated or described herein. In addition, "and/or" in the specification and claims means at least one of connected objects, a character "/" generally means that a preceding and succeeding related objects are in an "or" relationship.
The memory provided by the embodiment of the present application is described in detail by specific embodiments and application scenarios thereof with reference to the accompanying drawings.
The embodiment of the present application provides a memory, which, referring to fig. 1 to 8, includes a substrate 101, a stack layer disposed on the substrate 101, and a channel, where the stack layer includes an isolation layer 102 and a first memory gate layer 103 that are alternately stacked along a first direction; the channel is disposed on the substrate 101 and penetrates through the stacked layers, a second storage gate layer 115, a blocking layer 107, an electron trapping layer 108, an electron tunneling layer 111, and a conductive channel layer 112 are sequentially stacked on a first portion of the channel along a second direction, the channel includes first functional layers, a first distance exists between every two first functional layers along the first direction, and the first functional layers include the second storage gate layer 115, the blocking layer 107, and the electron trapping layer 108; wherein the first storage gate layer 103 of the stacked layer corresponds to the second storage gate layer 115 of the channel. In the memory provided by the embodiment of the present application, the first functional layers including the second storage gate layers 115, the blocking layer 107 and the electron trapping layer 108 are not disposed through the stacked layers, but a first distance is formed between every two adjacent first functional layers along the first direction, that is, the first functional layers are discretely disposed, that is, an independent blocking layer 107 and an electron trapping layer 108 are formed corresponding to each second storage gate layer 115, and the electron trapping layers 108 between different second storage gate layers 115 are separated, so that an electron escape phenomenon between the adjacent second storage gate layers 115 can be effectively reduced, and thus, the reliability of data stored in the memory can be effectively improved.
It is understood that the second storage gate layer 115 corresponds to the first storage gate layer 103; wherein the first memory gate layer 103 is a memory gate layer formed on the stack layer before the formation of the channel, and the second memory gate layer 115 is a memory gate layer formed after the formation of the channel, a portion of the first memory gate layer 103 is replaced by the blocking layer 107 and the electron trapping layer 108, and the remaining portion of the first memory gate layer 103 is the second memory gate layer 115, i.e. the first memory gate layer 103 and the second memory gate layer 115 are continuous in the second direction.
In one embodiment, the channel further comprises a second portion, and the second portion and the first portion are symmetrically arranged with a central axis of the channel as a symmetry axis; wherein the second portion has a conductive channel layer (112), an electron tunneling layer (111), an electron trapping layer (108), a blocking layer (107), and a second storage gate layer (115) stacked in sequence along the second direction. Specifically, the whole channel is in a form of symmetrical arrangement, and the second storage gate layer 115, the blocking layer 107, the electron trapping layer 108, the electron tunneling layer 111 and the conductive channel layer 112 are symmetrically arranged in two groups; also, in general, there may be a gap position between the two conductive channel layers 112, and the gap position is filled with the filling layer 113, and specifically, alternatively, the material of the filling layer 113 may be silicon oxide.
In one embodiment, the first direction is perpendicular to the second direction.
Specifically, referring to fig. 1 to 8, the first direction is a vertical direction pointing from top to bottom in the drawing, and the second direction is a horizontal direction pointing from left to right in the drawing, and the two directions are perpendicular to each other.
In one embodiment, the memory further comprises a common source 109, the common source 109 being disposed on the substrate 101 and extending through the stacked layers. It will be appreciated that the direction through which the common source 109 extends is parallel to the first direction.
Further, in one embodiment, the common source 109 is provided in plurality, the common sources 109 are spaced apart from each other in the second direction in the stacked layer, and a second distance exists between two adjacent common sources 109.
Generally, the number of the common source electrodes 109 is more than one, and a plurality of the common source electrodes 109 are spaced apart along the second direction by the second distance and are disposed in the opposite stack.
The embodiment of the application also provides a manufacturing method of the memory, which comprises the following steps:
referring to fig. 1-7, a substrate 101 is provided; forming a preset stack layer on the substrate 101, wherein the preset stack layer comprises alternately arranged isolation layers 102 and sacrificial layers 110; etching a channel hole 104 through the preset stack layer along a first direction and exposing the substrate 101; replacing the sacrificial layer 110 in the preset stack layer with a first storage gate layer 103, wherein the isolation layer 102 and the first storage gate layer 103 form a stack layer; etching and removing a part of each first storage gate layer 103 close to the channel hole 104 on two sides of the channel hole 104 to form a notch 105; in each of the cut-outs 105, a barrier layer 107 and an electron trap layer 108 are formed by filling in the second direction, and an electron tunneling layer 111 and a conductive channel layer 112 are formed by filling in the channel hole 104.
In the manufacturing method of the memory provided by the embodiment of the application, through reasonable configuration of the process flow, the sacrificial layer 110 is completely removed in the preset stack layer, the first storage gate layer 103 is formed at the position originally belonging to the sacrificial layer 110, then the first storage gate layer 103 is subjected to reverse etching, a part of the first storage gate layer 103 close to two sides of the channel hole 104 is etched and removed to form the notch portion 105, the remaining storage gate layer after the notch portion 105 is formed is the second storage gate layer 115, one notch portion 105 corresponds to one second storage gate layer 115, the notch portions 105 are arranged at intervals, and a first distance is arranged between two adjacent notch portions 105. Therefore, the barrier layers 107 and the electron trapping layers 108 formed in the openings 105 are also spaced apart, and one second storage gate layer 115 corresponds to one barrier layer 107 and one electron trapping layer 108, so that the electron trapping layers 108 between different second storage gate layers 115 are separated, and the electron escape phenomenon between adjacent second storage gate layers 115 is effectively reduced. Since the first storage gate layer 103 is made of a metal material and has a large difference in chemical properties from the isolation layer 102 of silicon oxide, when a portion of the first storage gate layer 103 is etched to form the gap 105, whether dry etching or wet etching is used, the first storage gate layer 103 can have an etching rate far greater than that of the isolation layer 102, so that the gap 105 can be formed easily.
Alternatively, the substrate 101 may be a Si substrate, a Ge substrate, a SiGe substrate, and the like, which is not particularly limited in this application. Optionally, the isolation layer 102 is a silicon oxide layer. The sacrificial layer 110 is a silicon nitride layer. Specifically, optionally, when the sacrificial layer 110 of the silicon nitride layer is removed, phosphoric acid may be selectively used to perform wet etching on the silicon nitride layer; after the silicon nitride layer is removed and the first memory gate layer 103 is formed, a silicon oxide layer is located between every two first memory gate layers 103 as an isolation layer 102 to perform an isolation insulation function.
In one embodiment, the method further comprises:
forming a common source groove 114 penetrating through the stacked layers by dry etching and exposing the substrate 101; and performing ion implantation on the exposed substrate 101 in the common source groove 114 to fill source metal to form a common source 109.
In this embodiment, the common source 109 is first formed and then the channel hole 104 is etched, so that the common source 109 can support the predetermined stack layer.
In one embodiment, the method for forming the common source 109 specifically includes:
forming a common source electrode groove 114 penetrating through the preset stacking layer by adopting dry etching and exposing the substrate 101; performing ion implantation on the exposed substrate 101 in the common source groove 114 to fill source metal to form a common source 109;
dry etching is a technique for performing thin film etching using plasma; the formation of the common source 109 is a well-established process, and the application is not particularly limited.
In one embodiment, the replacement of the sacrificial layer 110 in the preset stack layer with the first storage gate layer 103 is specifically:
removing the sacrificial layer 110 by wet etching to form a gap structure; a first storage gate layer 103 is formed within the void structure using chemical vapor deposition.
Wet etching is a technique of etching an etching material using an etching solution. The process of replacing the sacrificial layer 110 with the first memory gate layer 103 is a well-established process, and the present application is not particularly limited.
While the present embodiments have been described with reference to the accompanying drawings, it is to be understood that the invention is not limited to the precise embodiments described above, which are meant to be illustrative and not restrictive, and that various changes may be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A memory, comprising:
a substrate (101);
a stack layer disposed on the substrate (101), the stack layer including an isolation layer (102) and a first memory gate layer (103) alternately stacked in a first direction;
a channel disposed on the substrate (101) and penetrating through the stack, a first portion of the channel having a second storage gate layer (115), a blocking layer (107), an electron trapping layer (108), an electron tunneling layer (111), and a conductive channel layer (112) sequentially stacked along a second direction, the channel comprising first functional layers, a first distance existing between every two first functional layers along the first direction, the first functional layers comprising the second storage gate layer (115), the blocking layer (107), and the electron trapping layer (108);
wherein the first memory gate layer (103) of the stacked layers corresponds to the second memory gate layer (115) of the channel.
2. The memory according to claim 1, wherein the channel further comprises a second portion, and the second portion and the first portion are symmetrically arranged with a central axis of the channel as a symmetry axis;
wherein the second portion has a conductive channel layer (112), an electron tunneling layer (111), an electron trapping layer (108), a blocking layer (107), and a second storage gate layer (115) stacked in sequence along the second direction.
3. The memory of claim 1, wherein the first direction is perpendicular to the second direction.
4. The memory of claim 1, further comprising a common source (109), the common source (109) being disposed on the substrate (101) and throughout the stacked layers.
5. The memory according to claim 4, wherein the common source (109) is provided in plurality, the common sources (109) are spaced apart in the stacked layer along the second direction, and a second distance exists between two adjacent common sources (109).
6. A manufacturing method of a memory is characterized by comprising the following steps:
providing a substrate (101); forming a preset stack layer on the substrate (101), wherein the preset stack layer comprises isolation layers (102) and sacrificial layers (110) which are alternately arranged; etching a channel hole (104) through the predetermined stack layer along a first direction and exposing the substrate (101); replacing a sacrificial layer (110) in the preset stack layer with a first storage gate layer (103), wherein the isolation layer (102) and the first storage gate layer (103) form a stack layer; etching and removing a part of each first storage gate layer (103) close to the channel hole (104) on two sides of the channel hole (104) to form a notched part (105); a barrier layer (107) and an electron trap layer (108) are formed in each of the cutouts (105) along the second direction, and an electron tunneling layer (111) and a conductive channel layer (112) are formed in the channel hole (104).
7. The method of fabricating a memory of claim 6, further comprising:
forming a common source trench (114) penetrating through the stacked layers by dry etching and exposing the substrate (101); and carrying out ion implantation on the exposed substrate (101) in the common source groove (114) to fill source metal to form a common source (109).
8. The method for manufacturing the memory according to claim 6, wherein the replacing the sacrificial layer (110) in the preset stack layer with the first memory gate layer (103) is specifically:
removing the sacrificial layer (110) by wet etching to form a gap structure; a first storage gate layer (103) is formed within the void structure using chemical vapor deposition.
9. The method of claim 6, wherein the isolation layer (102) is a silicon oxide layer.
10. The method of claim 6, wherein the sacrificial layer (110) is a silicon nitride layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202010859679.5A CN111987106A (en) | 2020-08-24 | 2020-08-24 | Memory and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202010859679.5A CN111987106A (en) | 2020-08-24 | 2020-08-24 | Memory and manufacturing method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113053904A (en) * | 2021-03-15 | 2021-06-29 | 维沃移动通信有限公司 | Three-dimensional flash memory structure and electronic equipment |
| CN113394228A (en) * | 2021-06-07 | 2021-09-14 | 长江存储科技有限责任公司 | Three-dimensional memory and preparation method thereof |
-
2020
- 2020-08-24 CN CN202010859679.5A patent/CN111987106A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113053904A (en) * | 2021-03-15 | 2021-06-29 | 维沃移动通信有限公司 | Three-dimensional flash memory structure and electronic equipment |
| CN113394228A (en) * | 2021-06-07 | 2021-09-14 | 长江存储科技有限责任公司 | Three-dimensional memory and preparation method thereof |
| CN113394228B (en) * | 2021-06-07 | 2022-05-20 | 长江存储科技有限责任公司 | Three-dimensional memory and preparation method thereof |
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