CN113394174A - 用于器件封装的系统和方法 - Google Patents
用于器件封装的系统和方法 Download PDFInfo
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- CN113394174A CN113394174A CN202110265813.3A CN202110265813A CN113394174A CN 113394174 A CN113394174 A CN 113394174A CN 202110265813 A CN202110265813 A CN 202110265813A CN 113394174 A CN113394174 A CN 113394174A
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 6
- 239000000919 ceramic Substances 0.000 claims abstract description 169
- 229910010293 ceramic material Inorganic materials 0.000 claims description 34
- 229910000679 solder Inorganic materials 0.000 claims description 30
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 8
- 239000010931 gold Substances 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 claims description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 8
- 229910052721 tungsten Inorganic materials 0.000 claims description 8
- 239000010937 tungsten Substances 0.000 claims description 8
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 230000008878 coupling Effects 0.000 claims description 4
- 238000010168 coupling process Methods 0.000 claims description 4
- 238000005859 coupling reaction Methods 0.000 claims description 4
- 238000005476 soldering Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 description 26
- 230000008901 benefit Effects 0.000 description 11
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 230000035882 stress Effects 0.000 description 9
- 239000000463 material Substances 0.000 description 7
- 238000001465 metallisation Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 5
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- 230000008569 process Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 229910001092 metal group alloy Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 238000004381 surface treatment Methods 0.000 description 2
- ZEMPKEQAKRGZGQ-AAKVHIHISA-N 2,3-bis[[(z)-12-hydroxyoctadec-9-enoyl]oxy]propyl (z)-12-hydroxyoctadec-9-enoate Chemical compound CCCCCCC(O)C\C=C/CCCCCCCC(=O)OCC(OC(=O)CCCCCCC\C=C/CC(O)CCCCCC)COC(=O)CCCCCCC\C=C/CC(O)CCCCCC ZEMPKEQAKRGZGQ-AAKVHIHISA-N 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000005382 thermal cycling Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
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Abstract
本公开的各实施例涉及用于器件封装的系统和方法。一种封装功率器件,包括陶瓷封装主体,该陶瓷封装主体包括具有第一面积的顶部漏极焊盘、具有第二面积的顶部源极焊盘、以及具有第三面积的顶部栅极焊盘,第二面积小于第一面积,第三面积小于第二面积;功率器件,具有被附连到顶部漏极焊盘的底部表面、被耦合到顶部源极焊盘的管芯源极焊盘、以及被耦合到顶部栅极焊盘的管芯栅极焊盘;以及陶瓷盖,该陶瓷盖被附连到陶瓷封装主体以形成经封装的功率器件。
Description
技术领域
本发明总体涉及用于器件封装的系统和方法。
背景技术
表面安装器件(SMD)封装可以用于容纳半导体器件,并将其直接连接到印刷电路板(PCB)。由于表面安装器件可以提供的各种优点,大量的电子电路设计使用SMD封装。例如,在需要高可靠性的军事和空间应用(如高性能车辆、飞机、航天飞机和卫星)中,SMD封装可以在极端或恶劣环境中提供必要的鲁棒性,同时提供益处(诸如更小的尺寸、更轻的重量和优异的热性能等)。
然而,SMD封装的普及受到了在SMD封装外壳的不同部分中使用的不同材料之间以及SMD封装与PCB材料之间的热膨胀系数(CTE)不相容性的阻碍。例如,传统SMD封装可以包括金属合金侧壁和陶瓷基底。尽管金属合金和陶瓷材料在室温下可能具有基本匹配的CTE,但是它们的CTE会随着温度的升高而急剧发散。在制造过程和热循环期间,当侧壁和基底都膨胀和收缩时,热应力会在侧壁与基底之间积聚。此外,当传统SMD封装被安装到PCB上时,传统SMD封装与PCB之间的CTE不匹配可能向SMD封装引入安装应力。这些应力会导致SMD封装的疲劳和开裂,反而导致SMD封装的气密性损失,并损坏SMD封装内部的半导体器件和电路。
因此,需要通过提供半导体封装(诸如SMD封装)来克服这种缺点和不足,半导体封装能够显著减少由于热应力和安装应力而导致的半导体封装的疲劳和开裂。
发明内容
一种封装包括陶瓷封装主体,该陶瓷封装主体包括内部腔部分和外部部分;具有第一面积的顶部漏极焊盘、具有第二面积的顶部源极焊盘、以及具有第三面积的顶部栅极焊盘,其中第二面积不同于第一面积,第三面积不同于第二面积,顶部漏极焊盘、顶部源极焊盘和顶部栅极焊盘被布置在内部腔部分的底表面上,并且其中顶部漏极焊盘、顶部源极焊盘与顶部栅极焊盘通过陶瓷封装主体的陶瓷材料彼此隔离;以及具有第四面积的底部漏极焊盘、具有第五面积的底部源极焊盘、以及具有第六面积的底部栅极焊盘,并且其中第五面积不同于第四面积,第六面积不同于第五面积,底部漏极焊盘、底部源极焊盘和底栅极焊盘被布置在外部部分的主表面上,并且其中底部漏极焊盘、底部源极焊盘与底部栅极焊盘通过陶瓷封装主体的陶瓷材料彼此隔离,并且其中顶部漏极焊盘和底部漏极焊盘通过至少一个漏极焊盘过孔耦合在一起,顶部源极焊盘和底部源极焊盘通过至少一个源极焊盘过孔耦合在一起,顶部栅极焊盘和底部栅极焊盘通过至少一个栅极焊盘过孔耦合在一起。
附图说明
为了更全面地理解本发明及其优点,现在结合附图参考以下描述,其中:
图1示出了根据实施例的陶瓷封装主体的顶视图;
图2示出了图1的陶瓷封装主体的底部立体视图;
图3示出了图1的陶瓷封装主体的顶部立体视图,示出了进一步的内部细节,诸如顶部焊盘与底部焊盘之间的过孔;
图4示出了包括图1的陶瓷封装主体以及被附连到陶瓷封装主体的盖的经组装的封装的顶部立体视图;
图5示出了图4的经组装的封装的底部立体视图;
图6A、图6B、图6C、图6D和图6E示出了图4的经组装的封装的各种附加的视图;
图7A示出了根据实施例的包括半导体器件的陶瓷封装主体的横截面侧视图;
图7B示出了还包括被附接到半导体器件和封装的接合线的图7A的陶瓷封装主体的横截面侧视图;
图7C示出了还包括被附连到陶瓷封装主体以形成经组装的封装的盖的图7B的陶瓷封装主体的横截面侧视图;
图8示出了图7B的陶瓷封装主体和集成电路的顶部平面视图;
图9示出了图7C的经组装的封装和半导体器件的分解顶部立体视图;
图10示出了根据实施例的具有备选的城堡形图案的陶瓷封装主体的底部平面视图;
图11示出了图10的陶瓷封装主体的底部立体视图;
图12示出了根据实施例的具有另一种备选的城堡形图案的陶瓷封装主体的底部立体视图;
图13A示出了根据实施例的包括备选的顶部焊盘布局的陶瓷封装主体的顶部平面视图;
图13B示出了包括备选的底部焊盘布局的图13A的陶瓷封装的底部平面视图;
图14A示出了制造陶瓷封装主体的方法的流程图;以及
图14B示出了制造用于附接到图14A的陶瓷封装主体的陶瓷盖的方法的流程图。
具体实施方式
下文详细讨论目前优选实施例的制造和使用。然而,应该理解的是,本发明提供了许多可应用的发明概念,这些概念可以在各种具体的上下文中呈现。所讨论的具体实施例仅仅是说明制造和使用本发明的具体方式,而不限制本发明的范围。
本发明将根据具体的上下文中的优选实施例来描述,即用于功率器件(诸如功率晶体管或功率二极管)的表面安装封装。本发明的实施例还可以被应用于其它封装类型和/或被配置为容纳各种电子部件的封装。
根据实施例,功率封装包括同时出现的许多有利方面,包括小的经组装的封装尺寸、大功率处理能力、陶瓷封装主体与陶瓷盖之间的密封、高可靠性、以及表面安装能力。由于半导体技术正在不断改进并且功率器件正在变得更小,因此可以有利地获得小尺寸的功率封装;在实施例中,功率封装有利地适应该趋势。在一些实施例中,由于半导体技术的另外的改进,功率器件能够比先前的设计切换更多的功率,因此功率封装还容纳大的功耗。在实施例中,具有密封外壳的功率封装被有利地提供给许多军事和空间应用,使得湿气或其他环境因素不会侵蚀封装的功率器件。在实施例中,有利地提供高可靠性以承受各种恶劣的操作环境。例如,当被安装在基板(诸如PCB)上时,功率封装有利地经受从极端高温到极端低温的许多温度循环。根据实施例,功率封装有利地保持其完整性,并且将功率封装附连到PCB的焊点仍然将完好无损。在实施例中,焊点也容易可见,使得可以容易地确定焊点的完整性。最后,在一些实施例中,功率封装可以使用与同一PCB上的其他表面安装器件兼容的通常的表面安装工艺,直接表面安装在PCB或其他这种衬底上。下文进一步详细描述能够同时提供所有优点的功率封装的各种实施例。
在实施例中,功率封装包括氮化铝(AlN)陶瓷封装主体。选择氮化铝,由于它的导热系数高达285瓦每米开尔文(W/m*K),并且因为氮化铝是电绝缘体。在实施例中,功率封装包括氮化铝陶瓷盖,因此CTE不匹配被最小化。在实施例中,盖包括预成型焊料,并且预成型焊料被焊接密封到陶瓷封装主体上。除了氮化铝陶瓷以外的不同陶瓷材料可以用于陶瓷封装主体和盖。例如,可以使用氧化铝(也称为“三氧化二铝”)代替氮化铝。根据所使用的陶瓷材料,功率封装的导热性能会发生变化。为使功率封装中的应力最小化,陶瓷封装主体和陶瓷盖都采用相同的陶瓷材料。
在实施例中,陶瓷封装主体的焊盘布局包括不同的漏极焊盘、源极焊盘和栅极焊盘。在实施例中,漏极焊盘包括顶部漏极焊盘、顶部源极焊盘和顶部栅极焊盘。顶部焊盘与陶瓷封装主体的内部腔部分的底表面相关联,顶部漏极焊盘被设计用于接收二端或三端功率半导体器件。在实施例中,顶部漏极焊盘具有第一面积,该第一面积大于顶部源极焊盘的第二面积。顶部源极焊盘的第二面积进而大于顶部栅极焊盘的第三面积。顶部焊盘的不对称布局用于实现最大布局效率,使得获得最小的封装面积。在实施例中,漏极焊盘还包括底部漏极焊盘、底部源极焊盘和底部栅极焊盘。底部焊盘与陶瓷封装主体的外部部分相关联。底部焊盘也具有与顶部焊盘的不对称布局大致对应的类似的不对称布局。底部焊盘被设计为使用下文描述的城堡形图案被焊接到PCB上。在实施例中,顶部和底部焊盘可以由金或铝或其他导电材料或其合金形成。过孔用于将顶部焊盘和底部焊盘电耦合在一起,其中较大的焊盘(诸如漏极焊盘)可以包括多达12个或更多过孔,而较小的焊盘(诸如栅极焊盘)仅可以包括3个或更多过孔。在实施例中,过孔材料可以是钨、铜或其他导电材料或其合金。
根据实施例,功率封装因此获得了有利的小尺寸,具有覆盖区为0.220英寸乘0.150英寸,高度为0.060英寸。功率封装的尺寸可以根据需要更改为任何适当的尺寸。该功率封装被设计为容纳半导体器件或管芯,包括三端子或二端子半导体器件,诸如金属氧化物半导体场效应晶体管(MOSFET)、二极管,具有管芯附接面积小于顶部漏极焊盘面积。在实施例中,管芯附接面积(顶部漏极焊盘尺寸)约为0.095英寸乘0.085英寸。管芯连接面积的尺寸可以根据需要更改为任何适当的尺寸。在实施例中,管芯源极焊盘和管芯栅极焊盘使用金接合线或其他适当的导线耦合到陶瓷封装主体的顶部源极焊盘和顶部栅极焊盘。可以使用多条接合线将管芯源极焊盘耦合到顶部源极焊盘,使得封装电阻被最小化。
在实施例中,陶瓷封装主体包括由底部漏极焊盘、源极焊盘和栅极焊盘中的每个焊盘以及陶瓷封装主体外部的对应的侧壁中的一个或多个凹槽或槽形成的城堡形图案。凹槽是金属化的,并且包括与对应的底部漏极焊盘、源极焊盘或栅极焊盘相同的材料。金属化的凹槽有助于焊料粘附,从而形成焊接圆角以增加焊点的强度。城堡形图案可以包括多个不同的图案,如下文将进一步详细地说明和描述的。在实施例中,城堡形图案将使得对应的焊点在功率封装的侧视图中容易看到,并且在检查中容易确定焊点的完整性。城堡形图案还能够在PCB上直接安装功率封装。功率封装可以通过通常的表面安装技术(SMT)工艺直接安装在PCB上,而不需要附加的导线或载体。根据实施例的功率封装与最常见的PCB材料(诸如玻璃增强环氧数值层压材料和聚酰亚胺,以及其他常见的PCB材料)兼容。
下文进一步详细地说明和描述了功率封装的实施例的其他特征和优点。
图1示出了根据实施例的陶瓷封装主体100的顶视图。陶瓷封装主体100包括顶部漏极焊盘102、顶部源极焊盘104和顶部栅极焊盘106。顶部焊盘位于示例不对称布局中,其中顶部漏极焊盘102的第一面积大于顶部源极焊盘104的第二面积,并且顶部源极焊盘104的第二面积大于顶部栅极焊盘106的第三面积。顶部焊盘由陶瓷封装主体100的陶瓷材料134电隔离。陶瓷封装主体100还包括内部侧壁和外部侧壁,以及金属化顶表面108。在实施例中,金属化顶表面108包括分层金属结构,该分层金属结构包括钨层、镍层和金层。也可以使用其他金属化结构。陶瓷封装主体100还包括城堡形图案,该城堡形图案包括多个凹槽116A,这些凹槽116A参考随后的附图最容易看到和描述。
图2示出了图1的陶瓷封装主体100的底部立体视图。陶瓷封装主体100包括底部漏极焊盘110、底部源极焊盘112和底部栅极焊盘114。底部焊盘也由陶瓷封装主体100的陶瓷材料134电隔离。底部焊盘也具有如图1中所示的顶部焊盘的示例不对称布局,并且位于大致相同的横向位置。底部漏极焊盘110的第四面积大于底部源极焊盘112的第五面积,并且底部源极焊盘112的第五面积大于底部栅极焊盘114的第六面积。尽管顶部焊盘和底部焊盘通常处于相同的横向面积中,但是对应的顶部焊盘和底部焊盘的各个面积可能不相同,因为顶部焊盘受到陶瓷封装主体100的侧壁的限制。底部焊盘不受陶瓷封装主体100的侧壁的限制,并且可以延伸到陶瓷封装主体100的底部表面的边缘。陶瓷封装主体还包括由多个金属化的凹槽或槽116A建立的城堡形图案,其目的是接收焊料并在底部焊盘的底部表面与PCB(图2中未示出)的表面之间建立可见的焊点。例如,底部漏极焊盘110包括三个凹槽116A,底部源极焊盘包括两个凹槽116A,并且底部栅极焊盘还包括两个凹槽116A。凹槽116A从底部焊盘以及陶瓷封装主体100的外部侧壁移除材料。凹槽116A利用用于底部焊盘的相同的金属进行金属化。当封装通过表面安装工艺焊接在PCB上时,焊料将填充凹槽并形成焊接圆角以加强焊点。
图2中所示的城堡形图案非常适合将陶瓷封装主体100附接到PCB的表面,但这只是许多这种城堡形图案中的一个示例。附加的城堡形图案在随后的附图中示出,并在下文中进一步详细描述。
图3示出了图1的陶瓷封装主体100的顶部立体视图,示出了进一步的内部细节,诸如位于顶部焊盘与底部焊盘之间的多个过孔。例如,多个过孔118用于将顶部漏极焊盘102电连接到底部漏极焊盘110。多个过孔118延伸穿过陶瓷封装主体100底部的陶瓷材料134。尽管示出了十二个这种过孔118,但是本领域技术人员将理解,可以使用附加的或更少的过孔将顶部漏极焊盘102电连接到底部漏极焊盘110。尽管过孔显示为圆柱形结构,但也可以使用其他形状的结构。此外,甚至可以使用实心结构将顶部漏极焊盘102耦合到底部漏极焊盘110。多个过孔120用于将顶部源极焊盘104电连接到底部源极焊盘112。尽管示出了五个这种过孔,但是可以使用任何适当的数目。多个过孔122用于将顶部栅极焊盘106电连接到底部栅极焊盘114。尽管示出了三个这种过孔,但是可以使用任何适当的数目。
图4示出了经组装的封装200的顶部立体视图,封装200包括图1的陶瓷封装主体100和被附连到陶瓷封装主体100的盖124。盖124的底表面(图4中未示出)包括与陶瓷封装主体100的金属化的顶表面108类似的金属化的表面。盖124的金属化的表面可以包括分层结构,该分层结构包括钨层、镍层和金层。此外,盖124的金属化表面可以包括预成型焊料,使得盖124可以被附连到陶瓷封装主体100的金属化的顶表面108。盖124被放置在陶瓷封装主体100上并加热到足以熔化预成型焊料并在其之间形成密封的温度。
图5示出了图4的组装封装200的底部立体视图,示出了底部漏极焊盘110、底部源极焊盘112和底部栅极焊盘114以及陶瓷材料134提供的电隔离的进一步的细节。凹槽116A形成的城堡形图案和连接的盖124也如图5中所示。
图6A、图6B、图6C、图6D和图6E示出了图4的经组装的封装200的各种附加的视图。例如,图6A示出了图4的经组装的封装200的顶部平面视图,其中示出了盖124的上表面和陶瓷封装主体100的金属化顶表面108。图6B示出了图4的组装封装200的第一侧视图,其中示出了盖124、陶瓷封装主体的陶瓷材料134和凹槽116A。图6C示出了图4的组装封装200的底部平面视图,其中示出了通过陶瓷封装主体的陶瓷材料134彼此电隔离的底部漏极焊盘110、底部源极焊盘112和底部栅极焊盘114。图6C中还示出了用于形成城堡形图案的凹槽116A。图6D示出了图4的组装封装200的第二侧视图,其中示出了盖124、陶瓷封装主体的陶瓷材料134和凹槽116A。
图6E示出了图4的经组装的封装200的第一侧视图,其中示出了盖124、陶瓷封装主体的陶瓷材料134以及可见的焊点136A和136B。可见的焊点136A和136B填充先前在图6B中示出的凹槽116A。注意,焊点136A和136B将经组装的封装200牢固地附连到衬底138(诸如PCB或其他这种衬底)的上表面。
图7A示出了陶瓷封装主体100的侧视图,陶瓷封装主体100包括半导体器件或管芯126,该半导体器件或管芯126包括根据实施例的功率晶体管或功率二极管。在其它实施例中,半导体器件或管芯126可以包括包含附加部件的集成电路。半导体器件或管芯126被连接(焊接)到顶部漏极焊盘,这在图7A的侧视图中不可见。然而,图7A的横截面视图示出了半导体器件126相对于陶瓷封装主体100的陶瓷材料134的位置。
图7B示出了图7A的陶瓷封装主体的侧视图,该陶瓷封装主体还包括被附接到半导体器件126的接合线128。接合线用于将半导体器件126上的接合焊盘电耦合到陶瓷封装主体100中的接合焊盘。在图7B的横截面侧视图中既看不到半导体器件焊盘也看不到陶瓷封装焊盘,但是半导体器件焊盘和陶瓷封装焊盘可以最容易地在下文描述的图8的顶部平面视图中被看到。
图7C示出了图7B的陶瓷封装主体100的侧视图,陶瓷封装主体100还包括被附连到陶瓷封装主体100的盖124,以形成组装封装200。如前所述,使用预成型焊料将盖124附连到陶瓷封装主体100上。
图8示出了图7B的陶瓷封装主体100和半导体器件126的平面视图,包括金属化顶部表面108、顶部漏极焊盘102、顶部源极焊盘104和顶部栅极焊盘106。半导体器件或管芯126被附连到顶部漏极焊盘102,并且在实施例中包括功率晶体管。功率晶体管的漏极被电连接(焊接)到顶部漏极焊盘102,功率晶体管的管芯源极焊盘130通过第一组接合线128A和第二组接合线128B被电连接到顶部源极焊盘104,并且功率晶体管的管芯栅极焊盘132通过第三组接合线128C被电连接到顶部栅极焊盘106。如前所述,顶部漏极焊盘102、顶部源极焊盘104和顶部栅极焊盘106通过陶瓷封装主体100的陶瓷材料134彼此电隔离。尽管示出了两组接合线以将管芯源极焊盘130连接到顶部源极焊盘104,但是可以使用任意数目的接合线。尽管仅示出了一组接合线以将管芯栅极焊盘132连接到顶部栅极焊盘106,但是可以使用任意数目的接合线。由于与源极相关联的高电流,与栅极连接相比,源极连接通常使用更多的接合线。本领域技术人员将理解,对于双端功率器件(诸如功率二极管),管芯焊盘布局和接合线的数目将会改变。
图9示出了图7C的经组装的封装200和半导体器件126的分解顶部立体视图。因此,图9示出了陶瓷盖124和陶瓷封装主体100。如前所述,示出了陶瓷封装主体100包括金属化顶表面108和陶瓷材料134。如前所述,管芯源极焊盘130和顶部源极焊盘104通过接合线组128A和128B耦合在一起,并且管芯栅极焊盘132和顶部栅极焊盘106通过接合线组128C耦合在一起。
图10示出了根据实施例的陶瓷封装主体300的底部平面视图,该陶瓷封装主体300具有使用凹槽116B形成的备选的城堡形图案。还示出了底部漏极焊盘110、底部源极焊盘112和底部栅极焊盘114以及陶瓷材料134。尽管凹槽116B在位置和形状上与例如图2和图6B中所示的凹槽116A类似,但是该凹槽的长度比凹槽116A长。较长的凹槽长度可以传达一个优点,即可以使用附加的焊料以更强的焊点将封装主体300附接到PCB的顶表面。
图11示出了图10的陶瓷封装主体的底部立体视图,示出了底部漏极焊盘110、底部源极焊盘112、底部栅极焊盘114、陶瓷材料134和凹槽116B的附加的视图。
图12示出了示出了根据实施例的具有另一种备选的城堡形图案的陶瓷封装主体400的底部立体视图,该城堡形图案由L形凹槽116C形成。底部漏极焊盘110包括两个L形凹槽116C,底部源极焊盘112包括单个L形凹槽116C,并且底部栅极焊盘114包括单个L形凹槽116C。如前所述,底部焊盘通过陶瓷材料134彼此电隔离。
图13A示出了根据实施例的包括备选的顶部焊盘不对称布局的陶瓷封装主体500的顶部平面视图。尽管金属化顶表面108与先前说明和描述的相同,但是顶部焊盘可以不同。例如,顶部源极焊盘504的形状不规则,并且顶部栅极焊盘506与顶部源极焊盘504偏移。顶部漏极焊盘502类似于先前说明和描述的顶部漏极焊盘102。三个顶部焊盘通过陶瓷材料134的“Y形”部分彼此电隔离。顶部焊盘的相对尺寸如前所述,其中顶部漏极焊盘502具有最大面积,顶部源极焊盘504具有第二大面积,并且顶部栅极焊盘506具有三个焊盘中的最小面积。
图13B示出了还包括备选的底部焊盘不对称布局的图13A的陶瓷封装主体500的底部平面视图。底部焊盘不对称布局类似于备选的顶部焊盘不对称布局,并且底部焊盘通过过孔(图13A或图13B中未示出)耦合到顶部焊盘,如前所述。例如,底部源极焊盘512的形状不规则,并且底部栅极焊盘514与底部源极焊盘512偏移。底部漏极焊盘510类似于先前说明和描述的底部漏极焊盘110。三个底部焊盘通过陶瓷材料134的类似“Y形”部分彼此电隔离。顶部焊盘的相对尺寸如前所述,其中底部漏极焊盘510具有最大面积,底部源极焊盘512具有第二大面积,并且底部栅极焊盘514具有三个焊盘中的最小面积。陶瓷封装主体500还包括由多个凹槽116D形成的城堡形图案,如图13B中所示。底部漏极焊盘510包括三个凹槽116D,底部源极焊盘512包括四个凹槽116D,并且底部栅极焊盘514包括单个凹槽116D。凹槽116D的数目可以根据需要改变。
尽管图13A和图13B中示出了备选的顶部焊盘布局和底部焊盘布局,但是本领域技术人员将理解,许多其他这种不对称焊盘布局是可能的。尽管顶部焊盘布局和底部焊盘布局类似,但是它们不需要在平面视图中精确重叠。
图14A是用于制造陶瓷封装主体的流程图1400。陶瓷封装主体分几个步骤制造。首先,在步骤1402处,陶瓷封装主体由陶瓷材料(诸如氮化铝、氧化铝或其它陶瓷材料)形成。然后,在步骤1404处,通过从陶瓷封装主体移除一些陶瓷材料并用导电材料(诸如钨或其他金属或合金)填充移除的体积来形成过孔。在步骤1406处,还通过从陶瓷封装主体移除一些陶瓷材料来形成城堡形图案。在制造过程的这一点上,陶瓷封装主体已经具有所需的形状和尺寸。陶瓷封装主体的金属化过程随后在步骤1408处执行,其中将金属(诸如钨或其它金属)的薄层应用于顶部焊盘、底部焊盘和顶部金属化表面将要形成的面积,并且也施加到凹槽周围的表面上。最后,在步骤1410处,将耐腐蚀金属(诸如镍和金)应用于到所有金属化面积,作为最后的表面处理以保护金属化。
图14B是用于制造陶瓷盖的流程图1420。陶瓷盖也分几个步骤制造。首先,在步骤1422处,陶瓷盖由陶瓷材料(诸如氮化铝、氧化铝或其它陶瓷材料)形成。然后,在步骤1424处,用钨或其它金属或合金对陶瓷盖的底表面进行金属化。接着,在步骤1426处,将耐腐蚀金属(诸如镍和金)应用于金属化面积作为最后的表面处理以保护金属化。最后,在步骤1428处,将预成型焊料(金属或合金薄板,通常为Au80Sn20)附接到陶瓷盖的金属化的底表面,其中Au80Sn20在本领域中被称为金锡共晶焊料,按重量计含有80%的金和20%的锡。
这里总结了本发明的示例实施例。其他实施例也可以从本文提交的说明书和权利要求书的整体来理解。
示例1。根据实施例,一种封装包括陶瓷封装主体,包括内部腔部分和外部部分;具有第一面积的顶部漏极焊盘、具有第二面积的顶部源极焊盘、以及具有第三面积的顶部栅极焊盘,其中第二面积不同于第一面积,第三面积不同于第二面积,顶部漏极焊盘、顶部源极焊盘和顶部栅极焊盘被布置在内部腔部分的底表面上,并且其中顶部漏极焊盘、顶部源极焊盘与顶部栅极焊盘通过陶瓷封装主体的陶瓷材料彼此隔离;具有第四面积的底部漏极焊盘、具有第五面积的底部源极焊盘、以及具有第六面积的底部栅极焊盘,并且其中第五面积不同于第四面积,第六面积不同于第五面积,,其中底部漏极焊盘、底部源极焊盘和底部栅极焊盘被布置在外部部分的主表面上,并且其中底部漏极焊盘、底部源极焊盘与底部栅极焊盘通过陶瓷封装主体的陶瓷材料彼此隔离,其中顶部漏极焊盘和底部漏极焊盘通过至少一个漏极焊盘过孔耦合在一起,顶部源极焊盘和底部源极焊盘通过至少一个源极焊盘过孔耦合在一起,并且顶部栅极焊盘和底部栅极焊盘通过至少一个栅极焊盘过孔耦合在一起。
示例2。根据示例1的封装,还包括被附连到陶瓷封装主体的陶瓷盖。
示例3。根据前述示例中的任何示例的封装,其中陶瓷封装主体和陶瓷盖各自包括氮化铝。
示例4。根据前述示例中的任何示例的封装,其中封装具有约0.220英寸乘0.150英寸的覆盖区以及约0.060英寸的高度。
示例5。根据前述示例中的任何示例的封装,其中陶瓷封装主体包括金属化的顶表面,并且陶瓷盖包括金属化的底表面。
示例6。根据前述示例中的任何示例的封装,其中陶瓷封装主体的金属化的顶表面和陶瓷盖的金属化的底表面各自包括钨、镍和金。
示例7。根据前述示例中的任何示例的封装,其中陶瓷封装主体的外部部分包括城堡形图案。
示例8。根据前述示例中的任何示例的封装,其中城堡形图案包括多个金属化的凹槽,金属化的凹槽被配置为使得被附连到金属化的凹槽上的焊点在封装的侧视图中可见。
示例9。根据前述示例中的任何示例的封装,其中城堡形图案包括在底部漏极焊盘中的三个凹槽、在底部源极焊盘中的两个凹槽、以及在底部栅极焊盘中的两个凹槽。
示例10。根据前述示例中的任何示例的封装,其中城堡形图案包括在底部漏极焊盘中的两个L形凹槽、在底部源极焊盘中的单个L形凹槽、以及在底部栅极焊盘中的单个L形凹槽。
示例11。根据实施例,一种封装功率器件的方法包括将功率器件的底表面附连到陶瓷封装主体的具有第一面积的顶部漏极焊盘;将功率器件的管芯源极焊盘耦合到陶瓷封装主体的顶部源极焊盘,顶部源极焊盘具有小于第一面积的第二面积;以及将功率器件的管芯栅极焊盘耦合到陶瓷封装主体的顶部栅极焊盘,顶部栅极焊盘具有小于第二面积的第三面积。
示例12。根据示例11的方法,还包括将陶瓷盖附接到陶瓷封装主体以形成封装功率器件。
示例13。根据前述示例中的任何示例的方法,其中陶瓷封装主体和陶瓷盖都包括氮化铝。
示例14。根据前述示例中的任何示例的方法,还包括在陶瓷封装主体中形成城堡形图案。
示例15。根据前述示例中的任何示例的方法,还包括将陶瓷封装主体的城堡形图案中的金属化的凹槽焊接到衬底,使得金属化的凹槽中的焊点在陶瓷封装主体的侧视图中可见。
示例16。根据实施例,一种经封装的功率器件包括陶瓷封装主体,包括具有第一面积的顶部漏极焊盘、具有第二面积的顶部源极焊盘、以及具有第三面积的顶部栅极焊盘,第二面积不同于第一面积,第三面积不同于第二面积;功率器件,具有被附连到顶部漏极焊盘的底表面、被耦合到顶部源焊盘的管芯源极焊盘、以及被耦合到顶部栅极焊盘的管芯栅极焊盘;以及陶瓷盖,被附连到陶瓷封装主体以形成经封装的功率器件。
示例17。根据示例16的经封装的功率器件,其中经封装的功率器件具有约0.220英寸乘0.150英寸的覆盖区以及约0.060英寸的高度。
示例18。根据前述示例中的任何示例的经封装的功率器件,其中陶瓷封装主体和陶瓷盖都包括氮化铝。
示例19。根据前述示例中的任何示例的经封装的功率器件,还包括在陶瓷封装主体中形成城堡形图案。
示例20。根据前述示例中的任何示例的经封装的功率器件,其中城堡形图案包括在陶瓷封装主体的侧视图中可见的金属化的凹槽。
由于陶瓷封装主体和陶瓷盖由相同的陶瓷材料制成,因此根据实施例的微型功率封装呈现出低应力的优点。因此,CTE不匹配被最小化,并且陶瓷中的应力非常低。陶瓷封装主体与陶瓷盖之间的应力低,陶瓷封装主体内部和陶瓷盖内部的应力也低。此外,在一些实施例中不使用金属底座或密封圈,因此在陶瓷封装主体或组装功率封装内基本上不存在CTE不匹配。
根据实施例的微型功率封装呈现出低无模封装电阻(DFPR)的优点。例如,本文所描述的大源极焊盘允许多个接合线和多个过孔,以用于源极连接,因此对应地,DFPR低。
根据实施例的微型功率封装呈现出低热阻的优点。陶瓷封装主体和陶瓷盖中使用的陶瓷材料AlN具有低热阻,因此微型功率封装也具有低热阻。
根据实施例的微型功率封装具有可以用于恶劣环境应用的优点。例如,本文所述的功率封装在恶劣环境(诸如低温和高温环境、冲击和振动环境、高湿度环境以及高海拔和空间环境)中工作。
根据实施例的微型功率封装具有可以封装大功耗的功率晶体管和功率二极管,并且可以用于封装其他类型的半导体器件的优点。
尽管本发明已经参考说明性实施例进行了描述,但本说明书不旨在以限制意义进行解释。通过参考说明书,本发明的说明性实施例以及其他实施例的各种修改和组合将对本领域技术人员显而易见。因此,所附权利要求旨在包含任何此类修改或实施例。
Claims (20)
1.一种封装,包括:
陶瓷封装主体,包括内部腔部分和外部部分;
具有第一面积的顶部漏极焊盘、具有第二面积的顶部源极焊盘、以及具有第三面积的顶部栅极焊盘,其中所述第二面积不同于所述第一面积,所述第三面积不同于所述第二面积,所述顶部漏极焊盘、所述顶部源极焊盘和所述顶部栅极焊盘被布置在所述内部腔部分的底表面上,并且其中所述顶部漏极焊盘、所述顶部源极焊盘与所述顶部栅极焊盘通过所述陶瓷封装主体的陶瓷材料彼此隔离;
具有第四面积的底部漏极焊盘、具有第五面积的底部源极焊盘、以及具有第六面积的底部栅极焊盘,其中所述第五面积不同于所述第四面积,所述第六面积不同于所述第五面积,其中所述底部漏极焊盘、所述底部源极焊盘和所述底部栅极焊盘被布置在所述外部部分的主表面上,并且其中所述底部漏极焊盘、所述底部源极焊盘与所述底部栅极焊盘通过所述陶瓷封装主体的陶瓷材料彼此隔离,
其中所述顶部漏极焊盘和所述底部漏极焊盘通过至少一个漏极焊盘过孔耦合在一起,所述顶部源极焊盘和所述底部源极焊盘通过至少一个源极焊盘过孔耦合在一起,并且所述顶部栅极焊盘和所述底部栅极焊盘通过至少一个栅极焊盘过孔耦合在一起。
2.根据权利要求1所述的封装,还包括被附连到所述陶瓷封装主体的陶瓷盖。
3.根据权利要求2所述的封装,其中所述陶瓷封装主体和所述陶瓷盖各自包括氮化铝。
4.根据权利要求2所述的封装,其中所述封装具有约0.220英寸乘0.150英寸的覆盖区以及约0.060英寸的高度。
5.根据权利要求2所述的封装,其中所述陶瓷封装主体包括金属化的顶表面,并且所述陶瓷盖包括金属化的底表面。
6.根据权利要求5所述的封装,其中所述陶瓷封装主体的金属化的顶表面和所述陶瓷盖的金属化的底表面各自包括钨、镍和金。
7.根据权利要求2所述的封装,其中所述陶瓷封装主体的所述外部部分包括城堡形图案。
8.根据权利要求7所述的封装,其中所述城堡形图案包括多个金属化的凹槽,所述金属化的凹槽被配置为使得被附连到所述金属化的凹槽上的焊点在所述封装的侧视图中可见。
9.根据权利要求7所述的封装,其中所述城堡形图案包括在所述底部漏极焊盘中的三个凹槽、在所述底部源极焊盘中的两个凹槽、以及在所述底部栅极焊盘中的两个凹槽。
10.根据权利要求7所述的封装,其中所述城堡形图案包括在所述底部漏极焊盘中的两个L形凹槽、在所述底部源极焊盘中的单个L形凹槽、以及在所述底部栅极焊盘中的单个L形凹槽。
11.一种封装功率器件的方法,所述方法包括:
将所述功率器件的底表面附连到陶瓷封装主体的具有第一面积的顶部漏极焊盘;
将所述功率器件的管芯源极焊盘耦合到所述陶瓷封装主体的顶部源极焊盘,所述顶部源极焊盘具有小于所述第一面积的第二面积;以及
将所述功率器件的管芯栅极焊盘耦合到所述陶瓷封装主体的顶部栅极焊盘,所述顶部栅极焊盘具有小于所述第二面积的第三面积。
12.根据权利要求11所述的方法,还包括将陶瓷盖附连到所述陶瓷封装主体以形成封装功率器件。
13.根据权利要求12所述的方法,其中所述陶瓷封装主体和所述陶瓷盖都包括氮化铝。
14.根据权利要求11所述的方法,还包括在所述陶瓷封装主体中形成城堡形图案。
15.根据权利要求14所述的方法,还包括将所述陶瓷封装主体的所述城堡形图案中的金属化的凹槽焊接到衬底,使得所述金属化的凹槽中的焊点在所述陶瓷封装主体的侧视图中可见。
16.一种经封装的功率器件,包括:
陶瓷封装主体,包括具有第一面积的顶部漏极焊盘、具有第二面积的顶部源极焊盘、以及具有第三面积的顶部栅极焊盘,所述第二面积不同于所述第一面积,所述第三面积不同于所述第二面积;
功率器件,具有被附连到所述顶部漏极焊盘的底表面、被耦合到所述顶部源焊盘的管芯源极焊盘、以及被耦合到所述顶部栅极焊盘的管芯栅极焊盘;以及
陶瓷盖,被附连到所述陶瓷封装主体以形成所述经封装的功率器件。
17.根据权利要求16所述的经封装的功率器件,其中所述经封装的功率器件具有约0.220英寸乘0.150英寸的覆盖区以及约0.060英寸的高度。
18.根据权利要求16所述的经封装的功率器件,其中所述陶瓷封装主体和所述陶瓷盖都包括氮化铝。
19.根据权利要求16所述的经封装的功率器件,还包括在所述陶瓷封装主体中形成城堡形图案。
20.根据权利要求19所述的经封装的功率器件,其中所述城堡形图案包括在所述陶瓷封装主体的侧视图中可见的金属化的凹槽。
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