CN113394094B - Method for forming semiconductor device - Google Patents
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- CN113394094B CN113394094B CN202010176880.3A CN202010176880A CN113394094B CN 113394094 B CN113394094 B CN 113394094B CN 202010176880 A CN202010176880 A CN 202010176880A CN 113394094 B CN113394094 B CN 113394094B
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- 238000000034 method Methods 0.000 title claims abstract description 41
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000000137 annealing Methods 0.000 claims abstract description 66
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 48
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 33
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 33
- 239000001301 oxygen Substances 0.000 claims abstract description 33
- 239000010408 film Substances 0.000 claims abstract description 26
- 229920005591 polysilicon Polymers 0.000 claims abstract description 23
- 239000010409 thin film Substances 0.000 claims abstract description 17
- 238000006243 chemical reaction Methods 0.000 claims abstract description 16
- 230000008569 process Effects 0.000 claims abstract description 15
- 238000005468 ion implantation Methods 0.000 claims description 23
- 150000002500 ions Chemical class 0.000 claims description 21
- 239000007789 gas Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 6
- 230000007547 defect Effects 0.000 abstract description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 3
- 230000003647 oxidation Effects 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 5
- 239000012212 insulator Substances 0.000 description 4
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 3
- -1 boron ions Chemical class 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 229910001882 dioxygen Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000004321 preservation Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical group [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- NWLLPIVESIULPG-UHFFFAOYSA-N dysprosium indium Chemical compound [In].[Dy] NWLLPIVESIULPG-UHFFFAOYSA-N 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
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Abstract
The embodiment of the invention provides a method for forming a semiconductor device. In the embodiment of the invention, the effect of controlling the concentration of oxygen in the reaction cavity of the vertical annealing furnace to be more uniform is achieved by introducing a small amount of oxygen into the upper end of the reaction cavity of the vertical annealing furnace. The oxygen at the bottom of the reaction chamber caused by the residual oxygen in the air near the workpiece inlet in the loading process and the oxygen at the top of the reaction chamber are avoided, so that the oxygen concentration in the reaction chamber is inconsistent and the thickness of an oxidation layer caused by different loading time of each front-end device is not uniform. So that the surfaces of the polysilicon films of the front-end devices form more consistent oxide layers. The defect that the consistency of the resistance value of the polycrystalline silicon film is poor due to ion overflow in the annealing process is avoided. Therefore, the uniformity of the resistance values of the polycrystalline silicon thin films can be improved, and the performance of the semiconductor device can be improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a forming method of a semiconductor device.
Background
With the continuous development of semiconductor manufacturing processes, the integration level of semiconductor devices is higher and higher, and the feature size of semiconductor devices is also gradually reduced. However, the performance of semiconductor devices is also in need of improvement.
Disclosure of Invention
Embodiments of the present invention provide a method for forming a semiconductor device to improve performance of the semiconductor device.
The embodiment of the invention provides a method for forming a semiconductor device, which comprises the following steps:
providing a plurality of front-end devices;
forming a polysilicon film on the front-end device;
performing ion implantation on the polycrystalline silicon film to adjust the resistance value of the polycrystalline silicon film; and
annealing treatment to activate the implanted ions;
and the annealing treatment is to put the front-end device subjected to ion implantation and sequentially superposed into a vertical annealing furnace with an oxygen atmosphere for heat preservation for a preset time.
Further, the oxygen atmosphere is specifically:
oxygen gas with the gas flow range of 100sccm-1000sccm is introduced into the upper end of the vertical annealing furnace.
Further, the oxygen atmosphere is specifically:
oxygen gas is introduced into the upper end of the vertical annealing furnace in the gas flow range of 300sccm to 600 sccm.
Further, gaps are reserved among the plurality of front-end devices which are sequentially stacked after ion implantation.
Further, the annealing treatment specifically comprises:
and sequentially placing the sequentially overlapped front-end devices after ion implantation from the bottom of the vertical annealing furnace.
Further, the temperature of the annealing treatment is 600-800 ℃.
Furthermore, the material of the polycrystalline silicon thin film is polycrystalline silicon.
Further, the semiconductor device is a micro control unit.
In the embodiment of the invention, the effect of controlling the concentration of oxygen in the reaction cavity of the vertical annealing furnace to be more uniform is achieved by introducing oxygen into the upper end of the reaction cavity of the vertical annealing furnace. And forming an oxide layer with uniform thickness on the surface of the polysilicon film of each front-end device. The defect of poor consistency of resistance of the polycrystalline silicon film caused by ion overflow in the annealing process is avoided. Therefore, the uniformity of the resistance values of the polycrystalline silicon thin films can be improved, and the performance of the semiconductor device can be improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 is a schematic view of the structure of a vertical annealing furnace of a method of forming a semiconductor device of a comparative example;
fig. 2 is a flow chart of a method of forming a semiconductor device of an embodiment of the present invention;
fig. 3-6 are schematic views of structures formed at various steps of a method of forming a semiconductor device according to an embodiment of the present invention.
Detailed Description
The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.
Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.
Unless the context clearly requires otherwise, throughout this specification the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to".
In the description herein, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.
In the description herein, it is to be understood that the term "layer" is used in its broadest sense to include a film, a cap layer, or the like, and a layer may include a plurality of sub-layers.
Semiconductor devices are electronic devices that have electrical conductivity between a good electrical conductor and an insulator, and that use the special electrical properties of semiconductor materials to perform specific functions, and can be used to generate, control, receive, convert, amplify signals, and convert energy. Commonly used semiconductor devices include resistive devices. Among them, polysilicon resistors have been frequently used in conventional Integrated Circuit (IC) design, and have a high resistance value, and are generally used as high-resistance resistor devices.
The method of forming the semiconductor device of the comparative example includes the steps of:
and S1, providing a front-end device.
And S2, depositing a polycrystalline silicon film on the front-end device.
And S3, performing ion implantation on the polycrystalline silicon film.
And S4, annealing treatment.
Referring to fig. 1, the ion-implanted front-end device is annealed in a vertical annealing furnace. During the annealing process, the vertical annealing furnace is first evacuated and then a protective gas such as Ar or N2 is introduced to prevent oxidation. Then the vertical annealing furnace is preheated, and the purpose of preheating is to make the temperature of each position in the furnace uniform. And finally, placing the front-end device subjected to ion implantation into a preheated vertical annealing. Since residual oxygen is present in the air near the piece inlet at the bottom of the vertical annealing furnace, when the front-end device is placed in the reaction chamber c of the vertical annealing furnace, a part of the oxygen remains on the surface of the front-end device, and a plurality of ion-implanted front-end devices are placed in the annealing furnace on a jig in a stacked state. Therefore, when a plurality of front ends are loaded into the vertical annealing furnace from the bottom of the vertical annealing furnace, the front end device located at the upper end of the jig enters the vertical annealing furnace first, and therefore, the front end device located at the upper end of the jig is exposed to a high temperature for a longer time than the front end device located at the lower end of the jig. This results in the polysilicon film of the front-end device at the upper end of the chuck being oxidized at a higher temperature for a longer time than the front-end device at the lower end of the chuck. This results in a thinner oxide layer formed on the annealed surface of the ion-implanted front-end device located at the bottom b of the vertical annealing furnace, and a thicker oxide layer formed on the annealed surface of the ion-implanted front-end device located at the top a of the vertical annealing furnace. Meanwhile, since the heat generating device of the vertical annealing furnace is located at the side wall of the vertical annealing furnace, the edge of the front end device is close to the side wall with respect to the center position, and thus the temperature of the edge of the front end device may be higher than that of the center position. The higher the temperature, the faster the oxidation reaction, resulting in a greater thickness of the oxide layer at the edges of the front-end device than at the center. In the annealing process, the oxide layer can prevent the injected ions from overflowing at high temperature, so that the thicknesses of the oxide layers on the surfaces of the front-end devices after ion injection are different, and the ion doping concentrations of the polycrystalline silicon thin films of the front-end devices after ion injection are different. The region with the thicker oxide layer has high ion doping concentration because ions cannot overflow, and the resistance of the corresponding polycrystalline silicon film in the region is smaller.
In view of this, the performance of the semiconductor device is improved. The embodiment of the invention provides a method for forming a semiconductor device. In the embodiment of the present invention, a polysilicon thin film in a Microcontroller Unit (MCU) is formed as an example. Furthermore, the method of the embodiment of the invention can be used for forming other Semiconductor devices such as a Complementary Metal Oxide Semiconductor (CMOS), a NAND Flash Memory (NAND Flash Memory), a Static Random Access Memory (SRAM), and the like.
Fig. 2 is a flowchart of a method of forming a semiconductor device of an embodiment of the present invention. As shown in fig. 2, the method for forming a semiconductor device according to the embodiment of the present invention includes the steps of:
and step S100, providing a plurality of front-end devices.
And S200, forming a polycrystalline silicon film on the front-end device.
And step S300, carrying out ion implantation on the polycrystalline silicon film. So as to adjust the resistance of the polysilicon film.
And step S400, annealing treatment is carried out to activate the implanted ions. And the annealing treatment is to put a plurality of front-end devices which are sequentially overlapped and subjected to ion implantation into a vertical annealing furnace which is introduced with oxygen atmosphere for heat preservation for preset time.
Referring to fig. 3, in step S100, the front-end device 10 is provided.
Specifically, the front-end device 10 provided in step S100 may include a silicon single crystal substrate, a germanium single crystal substrate, or a silicon germanium single crystal substrate. Alternatively, the front-end device 10 may also include a silicon-on-insulator (SOI) substrate, a silicon-on-insulator (SSOI), a silicon-on-insulator-silicon-germanium (S-SiGeOI), a silicon-on-insulator-silicon-germanium (SiGeOI), a germanium-on-insulator (GeOI), a substrate of an epitaxial layer-on-silicon structure, a compound substrate, or an alloy substrate. The compound substrate includes silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, or indium dysprosium, the alloy substrate includes SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP, gaInAsP, or combinations thereof, the SOI substrate includes a semiconductor layer (e.g., a silicon layer, a silicon germanium layer, a silicon carbon layer, or a germanium layer) disposed on an insulating material layer having active and passive devices therein, the insulating material layer protecting the active and passive devices disposed on the semiconductor layer. And a plurality of epitaxial interface layers or strain layers and other structures can be formed on the surface of the front-end device so as to improve the electrical performance of the semiconductor device.
Referring to fig. 4, in step S200, a polysilicon thin film 20 is formed on the front-end device 10.
Specifically, the material of the polysilicon thin film 20 is polysilicon. The polysilicon film 20 is used to form a polysilicon resistor.
In an alternative implementation, a polysilicon thin film material layer is formed on the front-end device 10 by an optional Chemical Vapor Deposition (CVD) method to serve as the polysilicon thin film 20. For example, low Temperature Chemical Vapor Deposition (LTCVD), plasma Chemical Vapor Deposition (PCVD), low Pressure Chemical Vapor Deposition (LPCVD), rapid Thermal Chemical Vapor Deposition (RTCVD), plasma Enhanced Chemical Vapor Deposition (PECVD), and Fluid Chemical Vapor Deposition (FCVD).
In another alternative implementation, a patterned polysilicon film 20 may also be formed on the front-end device 10. Specifically, a polysilicon material layer may be formed by a chemical vapor deposition process, and then patterned by a photolithography process.
Referring to fig. 5, in step S300, ion implantation is performed on the polysilicon thin film 20. To adjust the resistance of the polysilicon thin film 20.
Impurities are doped in the polycrystalline silicon thin film 20 through an ion implantation process, and the resistance value of the polycrystalline silicon thin film 20 can reach the expected resistance value. The ion implanted front end device 30 is formed.
The implanted ions may be carbon atoms, boron ions, arsenic ions, phosphorus ions, and the like. The implantation energy of the ion implantation may be 5KeV to 180KeV. The dose of the ion implantation may be 1x10 4 /cm 3 -1x10 16 /cm 3 。
In an alternative implementation, the implanted ions are arsenic atoms, and the implanted dose can be 1 × 10 8 /cm 3 。
Compared with the comparative example, the dosage of the ion implantation of the embodiment of the invention can be adaptively adjusted because the oxide layer is formed on the polysilicon thin film in the subsequent process.
Referring to fig. 6, in step S400, an annealing process is performed to activate the implanted ions. The annealing treatment is to put the front-end device 30 after the multiple ion implantations, which are sequentially stacked, into a vertical annealing furnace with an oxygen atmosphere introduced therein and to keep the temperature for a predetermined time.
First, the vertical annealing furnace is evacuated and then a protective gas such as Ar or N is introduced into the furnace 2 To prevent oxidation. Then, the vertical annealing furnace is preheated for the purpose of making the temperature in each position in the furnace uniform. Finally, the ion-implanted front end device 30 is placed in a preheated vertical anneal.
Specifically, the plurality of front-end devices 30 after the ion implantation, which are stacked in sequence, have gaps therebetween. Each of the plurality of post-ion implantation front end devices 30 is placed on a jig or fixture such that a gap is provided in the middle of each of the plurality of post-ion implantation front end devices 30. Gaps are formed between the front-end devices 30 after ion implantation, so that the front-end devices can be heated uniformly.
Specifically, the front-end devices after the ion implantation, which are stacked in order, are sequentially placed from the bottom B of the vertical annealing furnace.
In the present embodiment, a high temperature annealing process is used to activate the dopant ions in the polysilicon thin film 20. Further, the annealing temperature is 600 ℃ to 800 ℃. The holding time can be 5min-30min.
Specifically, the oxygen atmosphere is: oxygen O with the gas flow range of 100sccm-1000sccm is introduced into the upper end of the vertical annealing furnace 2 . And under the condition that the top of the vertical annealing furnace is provided with an air inlet, introducing oxygen through the air inlet at the top of the vertical annealing furnace. Under the condition that the top of the vertical annealing furnace is not provided with the air inlet, the air inlet pipe can be arranged at the top A of the reaction chamber C, and oxygen is introduced into the reaction chamber C of the vertical annealing furnace through the air inlet pipe. Preferably, oxygen O with the gas flow range of 300sccm-600sccm is introduced into the upper end of the vertical annealing furnace 2 . In this embodiment, oxygen gas was introduced into the vertical annealing furnace at the upper end thereof in a flow rate range of 400 sccm. In other alternative implementations, the amount of oxygen introduced may be adaptively adjusted.
A small amount of oxygen is introduced into the upper end of the reaction chamber of the vertical annealing furnace. The nonuniform thickness of the oxide layer caused by the inconsistent concentration of oxygen entering the reaction chamber in the loading process and different loading time of each front-end device is avoided. The oxygen concentration of the atmosphere in the vertical annealing furnace in this example was uniform. And forming oxide layers with consistent thickness on the surfaces of the polysilicon films of the front-end devices. And ion overflow in the annealing process is avoided. The condition that the thickness of an oxide layer formed in a front-end device of the comparison example is uneven, ions overflow when the oxide layer in some areas is thin under a high-temperature condition, and ions do not overflow when the oxide layer in some areas is thick is avoided, so that the ion concentration in the polycrystalline silicon film is uneven. Therefore, the defect that the resistance value of each polycrystalline silicon film is poor in consistency due to uneven ion concentration in the polycrystalline silicon film can be avoided.
In the embodiment of the invention, the effect of controlling the concentration of oxygen in the reaction cavity of the vertical annealing furnace to be uniform is achieved by introducing oxygen into the upper end of the reaction cavity of the vertical annealing furnace. And forming an oxide layer with similar thickness on the surface of the polysilicon film of each front-end device. The defect of poor consistency of resistance of the polycrystalline silicon film caused by ion overflow in the annealing process is avoided. Therefore, the uniformity of the resistance values of the polycrystalline silicon thin films can be improved, and the performance of the semiconductor device can be improved.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A method of forming a semiconductor device, the method comprising:
providing a plurality of front-end devices;
forming a polysilicon film on the front-end device;
performing ion implantation on the polycrystalline silicon film to adjust the resistance value of the polycrystalline silicon film; and
annealing treatment to activate the implanted ions;
and the annealing treatment is to place the front-end device subjected to ion implantation and sequentially superposed into a vertical annealing furnace with an oxygen atmosphere, and annealing, wherein oxygen is introduced through the upper end of a reaction cavity of the vertical annealing furnace so that the oxygen concentration in the reaction cavity is consistent in the loading process.
2. The method for forming a semiconductor device according to claim 1, wherein the atmosphere into which oxygen is introduced is specifically:
oxygen with the gas flow range of 100sccm-1000sccm is introduced into the upper end of the vertical annealing furnace.
3. The method for forming a semiconductor device according to claim 1, wherein the atmosphere into which oxygen is introduced is specifically:
oxygen with the gas flow range of 300sccm-600sccm is introduced into the upper end of the vertical annealing furnace.
4. The method of claim 1, wherein the plurality of front-end devices stacked in sequence after ion implantation have a gap therebetween.
5. The method for forming a semiconductor device according to claim 1, wherein the annealing treatment specifically comprises:
and sequentially placing the sequentially overlapped front-end devices subjected to ion implantation from the bottom of the vertical annealing furnace.
6. The method of forming a semiconductor device according to claim 1,
the temperature of the annealing treatment is 600-800 ℃.
7. The method for forming a semiconductor device according to claim 1, wherein a material of the polycrystalline silicon thin film is polycrystalline silicon.
8. The method of claim 1, wherein the semiconductor device is a micro control unit.
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| CN103515224A (en) * | 2012-06-29 | 2014-01-15 | 无锡华润上华科技有限公司 | Rapid annealing method for polysilicon after ion implantation |
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| CN105826192A (en) * | 2015-01-07 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Method for improving resistance uniformity of annealing process of polycrystalline silicon |
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| CN103515224A (en) * | 2012-06-29 | 2014-01-15 | 无锡华润上华科技有限公司 | Rapid annealing method for polysilicon after ion implantation |
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