JP6351079B2 - Integrated circuit hydrogen passivation - Google Patents

Description

  The present application relates to the field of integrated circuits, and more particularly to hydrogen passivation of integrated circuits.

6 is a flowchart of processing steps for forming an integrated circuit according to one embodiment.

Fig. 4 illustrates steps in an integrated circuit process flow according to another embodiment. Fig. 4 illustrates steps in an integrated circuit process flow according to another embodiment. Fig. 4 illustrates steps in an integrated circuit process flow according to another embodiment. Fig. 4 illustrates steps in an integrated circuit process flow according to another embodiment. Fig. 4 illustrates steps in an integrated circuit process flow according to another embodiment.

Fig. 4 illustrates an integrated circuit according to another embodiment. Fig. 4 illustrates an integrated circuit according to another embodiment.

Fig. 4 illustrates an integrated circuit according to an alternative embodiment. Fig. 4 illustrates an integrated circuit according to an alternative embodiment. Fig. 4 illustrates an integrated circuit according to an alternative embodiment.

FIG. 5 compares the transistor threshold voltage (Vt) of a transistor formed according to one exemplary embodiment with the Vt of a transistor not formed according to the exemplary embodiment.

  Exemplary embodiments are described with reference to the accompanying drawings, wherein like or similar elements are designated with the same reference numerals throughout the several views. These drawings are not drawn to scale and are provided merely to illustrate exemplary embodiments.

  For purposes of illustration, some aspects will be described with reference to some example applications. Please understand that. Numerous specific details, relationships, and methods are described to provide a thorough understanding of the example embodiments. However, one of ordinary skill in the art will readily recognize that the exemplary embodiments may be practiced without one or more specific details or in other ways. In other instances, well-known structures or operations have not been shown in detail in order to avoid obscuring these embodiments. The illustrated embodiments are not limited by the illustrated order or event, the illustrated embodiments are not limited to the illustrated acts or sequence of events, and some actions may be performed in different orders and / or other actions. / It may be done at the same time as the event. Also, not all illustrated acts or events need to implement techniques in accordance with these illustrative examples.

  The threshold voltage (Vt) of a transistor is generally defined as the gate voltage at which an inversion layer is formed at the interface between the substrate (body) and the gate dielectric. However, an interface state located between the substrate and the gate dielectric can generate an interface charge (Qit) that contributes to the transistor threshold voltage. Therefore, variations in Qit can vary Vt. One method for passivating this interface charge is annealing at a temperature of about 400 ° C. in a hydrogen atmosphere, which is usually one of the final steps in the integrated circuit process flow.

  An earlier step in the integrated circuit process flow is the formation of the gate dielectric of the CMOS transistor. This process typically begins with the oxidation of the single crystal silicon surface of the substrate. As the oxide is grown on the silicon surface, the silicon atoms are removed from the single crystal silicon surface to form an amorphous layer of silicon dioxide. When oxidation stops, some ionic silicon and any incomplete silicon bonds remain in the interface region, thereby forming a sheet of positive charge called interface trap charge or Qit. A gate dielectric (which can be composed of pure silicon dioxide, nitrided silicon dioxide, or high-k dielectric) is deposited on the thin silicon dioxide layer.

  Other processes in the integrated circuit manufacturing flow (such as plasma deposition and plasma etching) can cause weak bond breaks at the interface, thereby forming additional Qit. This charge can vary across the substrate and can be unstable. Since this charge can contribute to the Vt of the transistor, any variability in Qit across the substrate can also cause Vt variability, leading to transistor instability.

  The integrated circuit manufacturing process can also cause crystal defects near the substrate surface. Crystal defects in the depletion region of the PN junction of the transistor can increase diode leakage.

  One way to reduce interface charge magnitude and instability (and to passivate crystal defects) is to perform a forming gas (H2 + N2) anneal at about 400 ° C. later in the manufacturing flow. is there. Hydrogen can react with silicon ions and incomplete silicon bonds to form Si-H bonds, thus reducing and stabilizing the interface charge. The Vt distribution spread of the transistor typically becomes tight with the passivation of the interface state, and the stability of the Vt distribution over time can be significantly increased. Also, diode leakage and integrated circuit standby current can be reduced when hydrogen reacts with imperfect silicon bonds along crystal defects to form silicon hydrogen bonds.

  Hydrogen passivation of integrated circuits is becoming increasingly difficult with new technologies. For example, materials such as TaN used to form the interconnect layer may prevent hydrogen from diffusing into the interface. The increasing number of interconnect layers also lengthens the diffusion path, thereby requiring a longer diffusion time to allow hydrogen to reach the interface. Also, some integrated circuit process flows (eg, for ferroelectric memories) are involved in forming a hydrogen barrier film (eg, to prevent hydrogen from degrading the electrical properties of the ferroelectric capacitor) To do. However, these hydrogen barrier films also prevent the hydrogen used in the forming gas anneal from reaching the interface.

  Also, some materials used in advanced process flows (such as metal gates and ultra-low k dielectric materials) can be degraded by hydrogen annealing at 400 ° C. for one hour or longer. If the forming gas anneal is omitted, some digital integrated circuits may be able to function with increasing transistor variants, but omit the anneal from the analog process flow (this is a closely controlled transistor and configuration). May not require element matching).

  The term “passivation” refers to the reduction of Qit and the diode leakage that can occur during annealing involving hydrogen or deuterium. Incomplete silicon bonding of hydrogen or deuterium and chemical reaction with silicon ions can occur at the interface between the single crystal silicon substrate and the amorphous silicon dioxide, and can also be silicon hydrogen (Si-H) or silicon deuterium. It also occurs in crystal defects near the substrate surface forming (Si-D) bonds, thereby reducing and stabilizing the interface charge. Prior to forming gas annealing, the Qit density can be as low as 1011 cm-2 eV-1. After the forming gas anneal, the Qit density can be reduced to as low as the 1010 cm-2 eV-1 range. Instead of hydrogen, deuterium isotopes of hydrogen can be used for passivation to form Si-D bonds (which can be more stable than Si-H bonds).

  FIG. 1 is a flowchart of processing steps for forming an integrated circuit according to one embodiment. After 1000 transistors are formed on the substrate, the integrated circuit is passivated 1002 with an anneal and a passivation trapping layer is deposited 1004. This trapping layer generally prevents hydrogen or deuterium passivation from diffusing away from the transistor and interface regions during subsequent thermal processing steps. An optional capping layer may be deposited 1006 on top of the passivation trapping layer. In one exemplary embodiment, a silicon nitride passivation trapping layer (formed of NH3) is deposited on top of the substrate (including transistors). Thereafter, an oxide cap layer is deposited on top of the silicon nitride passivation trapping layer. The silicon nitride passivation trapping layer and the oxide cap layer can prevent NH3 from damaging the photoresist used in subsequent photoresist patterning steps (such as etching the premetal dielectric layer overlying the transistor). . In addition, processing such as forming contacts to the transistors and back-end processes to form metal interconnect layers is performed to complete the integrated circuit.

  A passivation step 1002 may be performed after silicidation of the transistor gate, source, and drain, but before any back-end (post contact formation) processing step that may be adversely affected by hydrogen. For example, if a ferroelectric capacitor (FeCap) is to be manufactured after contact formation, a passivation process and a passivation trapping layer can be formed after contact formation and before FeCap formation. If the FeCap is to be formed after formation of the first interconnect layer, a passivation step and a passivation trapping layer can be formed on top of the first interconnect layer prior to FeCap formation. An example embodiment passivation step 1002 may be a hydrogen or deuterium anneal performed in a high density plasma comprising hydrogen or deuterium at 350 ° C. or higher, or the passivation step 1002 may be hydrogen or deuterium release. It can be achieved by depositing a film. The hydrogen releasing film can be, for example, a silicon nitride film with a high concentration of silicon hydrogen bonds. The passivation trapping layer formed in step 1004 can be a film such as AlOx, AlONx, SiNx, SiNxHy, A1N, or BN. In addition, the passivation trapping layer formed in step 1004 can be a silicon nitride film with a low concentration of Si—H bonds. Also, the silicon nitride passivation trapping layer can contain a significant concentration of N—H bonds.

  2A-2E illustrate the main processing steps of another embodiment. Although hydrogen passivation is used to illustrate this embodiment, deuterium passivation may be used instead.

FIG. 2A shows an integrated circuit 2000 that is partially processed but does not include contact photoresist patterning. The integrated circuit is formed on a substrate 2002 and includes a shallow trench isolation region 2004, a transistor 2010 (having a transistor gate dielectric 2006 and a transistor gate 2008), and a premetal dielectric (PMD) 2012. A hydrogen release layer 2014 is also deposited on the integrated circuit for the passivation process of the illustrated embodiment. In this exemplary embodiment, the hydrogen releasing film is a high concentration Si-H formed using a high density plasma (HDP) process (although such a film can also be formed using a low density plasma). SiNxHy film with bonding. SiNxHy films typically contain hydrogen in the form of Si-H and N-H bonds. Si—H bonds have a lower bond energy (eg, about 3.34 eV) than N—H bonds (eg, about 4.05 eV). Hydrogen in high Si-H bonds, including SiNxHy films, can dissociate during the back-end (eg post contact formation) heat treatment step (such as copper anneal) and then becomes available for passivation. An exemplary 8 inch HDP process for forming a SiNxHy hydrogen releasing film is shown in Table 1 below. One skilled in the art can prepare an equivalent hydrogen release film using different processes such as PECVD.

As illustrated in FIG. 2B, a hydrogen diffusion barrier layer 2116 is formed on top of the hydrogen release layer 2014 of the integrated circuit 2100 to function as a passivation trapping layer. More specifically, the hydrogen diffusion barrier layer 2116 generally prevents hydrogen from diffusing away from the interface and silicon crystal defects during subsequent thermal processing (degassing). The hydrogen diffusion barrier layer 2116 helps maintain a high hydrogen concentration in close proximity to the transistor 2010, which can passivate interface states and crystal defects. The hydrogen barrier layer may be formed of one or more dielectric thin films such as AlOx, AlONx, SiNx, SiNxHy, A1N, or BN. In the illustrated embodiment, the hydrogen barrier layer is a SiNxHy film with most of the hydrogen in the form of NH bonds. An exemplary process for forming such a SiNxHy hydrogen barrier film using an 8-inch plasma enhanced chemical vapor deposition (PECVD) process is shown in Table 2 below. The SiNxHy hydrogen barrier film may alternatively be prepared by one skilled in the art using other processes such as HDP.

  An optional capping layer of oxide film 2218 is formed on integrated circuit 2200 as shown in FIG. 2C. A contact photoresist pattern 2217 is then formed on top of the oxide film 2218. In this example, oxide film 2218 may prevent reverse reaction (eg, resist contamination) between residual NH 3 that may be present in PECVD SiNxHy hydrogen barrier film 2116 and contact photoresist pattern 2217. The reverse reaction can interfere with photoresist patterning and growth and can also interfere with the photoresist removal process.

  FIG. 2D shows integrated circuit 2300 after contact 2320 has been formed using conventional processing. Note that the contact etch may be modified to etch hydrogen release 2014 and hydrogen barrier 2116 SiNxHy films.

  As shown in FIG. 2E, additional backend processing may be performed to add the first level interconnect 2424. The first intermetal dielectric layer (IMD-1) 2422 electrically insulates the first level interconnect (metal-1) 2424. The IMD-12422 can be any suitable dielectric, such as PECVD oxide or low-k dielectric. First level interconnect 2424 may be a metal such as copper or an aluminum copper alloy. Additional processing steps can be performed to add additional levels of dielectric and interconnects to complete the integrated circuit. In this exemplary embodiment, the back-end passivation anneal currently commonly used as one of the final processing steps in the CMOS process flow may be omitted.

  Transistors are shown in FIGS. 2A-2E to illustrate the embodiment, but other components such as memory cells (SRAM, DRAM, FLASH, FRAM, etc.), resistors, capacitors, analog components, and high voltage components Note that can also benefit from using this embodiment. Also, although the substrate 2002 in the illustrated embodiment is a bulk silicon substrate, other substrates such as silicon on insulator may alternatively be used.

  The exemplary embodiment described above with reference to FIGS. 2A-2E uses a hydrogen releasing film 2014. In yet another embodiment, the hydrogen releasing film is omitted, but hydrogen or deuterium annealing, or forming gas annealing containing hydrogen or deuterium, is used to passivate the integrated circuit prior to the deposition of the passivation trapping layer 2116. . If this embodiment is used, the passivation annealing that is currently generally used as one of the final processing steps in the CMOS process flow may be omitted.

  In the above example, a hydrogen releasing film is deposited on the planarized PMD dielectric layer after transistor formation and before contact photoresist patterning. However, deposition of the hydrogen barrier film over the passivation step and optionally may occur at other points in the process flow, as illustrated in FIGS. 3A and 3B. In FIG. 3A, a hydrogen releasing film 3014 and a hydrogen barrier film 3016 (and an oxide film (not shown), if used) are deposited on the integrated circuit 3000 after the contact 3020 is formed. In this example, the (passivation process) hydrogen release film 3014 and the (passivation trapping) hydrogen barrier film 3016 can also serve as an etch stop layer for metal-1 3024. Further, the metal-1 dielectric material 3022 is TiN or TaN, such as a hydrogen barrier material TiN or TaN. Even when etched through the hydrogen barrier layer 3016 through the opening for the metal-1 interconnect 3024, the metal-1 3024 can make the desired electrical connection with the contact 3020, and metal- The combination of one dielectric material 3022 and hydrogen barrier layer 3016 may still function as a substantially continuous hydrogen barrier on the integrated circuit 3000.

  In FIG. 3B, a hydrogen release layer 3114 is deposited over integrated circuit 3100 after formation of source and drain 3111 and transistor gate 3108 and after optional silicidation 3113 of source and drain 3111. The hydrogen release layer 3114 is an integrated circuit 3100 that can be passivated. The hydrogen release layer 3114 can also function as a contact etch stop layer in this embodiment. After deposition and planarization of PMD layer 3112, a hydrogen diffusion barrier layer 3116 is deposited (along with an optional oxide cap layer (not shown) if used). A passivation trapping layer that functions as a hydrogen diffusion barrier layer 3116. Next, contact 3120 is formed and a first level of interconnect, metal-1 3124, is formed over contact 3120. Alternatively, in the embodiment shown in FIG. 3B, a hydrogen diffusion barrier layer 3116 can be deposited directly on top of the hydrogen release layer 3114, or after contact 3120 formation, and then used as an etch stop for the metal-1 3124 etch. Can be.

  It is also within the scope of the present invention that hydrogen release film 3114 and hydrogen barrier film 3116 may be deposited at other points in the integrated circuit manufacturing flow. Some of these other embodiments are illustrated in FIGS. 4A, 4B, and 4C. In these examples, 4000, 4100, and 4200 are when the hydrogen release layer is omitted. Thus, in the embodiment shown in FIGS. 4A, 4B, and 4C, the integrated circuit may or may not be passivated prior to the deposition of the passivation trapping layer 4016. In embodiments where the integrated circuit is passivated prior to the deposition of the passivation trapping layer 4016, the integrated circuit may be exposed to a high density plasma (HDP) containing hydrogen or deuterium, or alternatively hydrogen at 350 ° C. or higher. It can be passivated through deuterium annealing. An HDP plasma containing hydrogen or deuterium is typically used in the best mode of the exemplary embodiment to generate reactive H and D radicals, which are particularly effective in the process of passivating interface states and crystal defects. It is done.

  In FIG. 4A, HDP passivation is performed after formation of source and drain silicide 4013 and gate silicide 4015 but before deposition of passivation trapping layer 4016. In this embodiment, a passivation trapping layer 4016 is deposited before the contact 4020 patterning step. If the passivation trapping layer 4016 is SiNxHy, an optional oxide cap layer (not shown) is formed on top of the passivation trapping layer 4016 prior to contact patterning (to avoid photoresist contamination due to residual NH3 in SiNxHy). Can be deposited. In this illustrative example, FeCap 4016 and second contact 4038 are formed on passivation trapping layer 4016.

  In FIG. 4B, after the formation of source and drain silicides 4013 and gate silicides 4015, a passivation step is also performed before the passivation trapping layer 4116 is deposited. In this example, a passivation trapping layer is deposited after the formation of contacts 4020 but before the formation of metal-1 interconnect 4124.

  In FIG. 4C, a passivation process is also performed before and after the passivation blocking layer 4216 is deposited. However, in this embodiment, a passivation trapping layer is deposited before the PMD dielectric 4212 is deposited. In this embodiment, the passivation trapping layer can also function as an etch stop layer for the contact 4020 etching process.

  In the embodiment shown and described in FIGS. 4A-4C, after a hydrogen or deuterium from 350 ° C. (higher) anneal or from an HDP plasma passivates the interface and crystal defects, the passivation trapping layer is integrated circuit. Deposited on top of. A passivation barrier film is deposited to prevent hydrogen or deuterium from diffusing away from the transistor interface during subsequent thermal processing steps.

  FIG. 5 shows a spread threshold voltage (Vt), eg, an N-channel 3.3 volt transistor 5002 processed without hydrogen passivation anneal, an N-channel 3.3 volt treated with a conventional end-of-process 400 ° C. hydrogen passivation anneal. 1 illustrates a transistor 5004 and an N channel 3.3 volt transistor 5006 treated with a hydrogen releasing film and a passivation trapping layer (HDP deposited prior to contact patterning). As shown in FIG. 5, the Vt of transistor 5002 formed without passivation annealing is about 0.75 volts compared to the Vt of transistor 5006 formed with a hydrogen release film of about 0.68 volts and a passivation trapping layer. is there. Thus, the process of forming a transistor with a hydrogen releasing film and a passivation trapping layer can passivate a significant portion of the interface change (Qit), thereby causing a decrease in Vt.

  The electrical data shown in FIG. 5 shows that the Vt spread for the transistor formed without the passivation anneal 5002 is from the Vt spread for the transistor formed with the hydrogen releasing film and the passivation trapping layer 5006 (ie, .about.0.03 volts). It is further shown to be large (ie, ~ .12 volts). Thus, the uniformity of the transistor Vt is significantly improved over the hydrogen releasing film formed by the transistor and the passivation trapping layer. Also, the Vt (~ .68 volts) and Vt spread (.03 volts) of the transistor formed by the hydrogen releasing film and the passivation trapping layer 5006 at Vt (~ .69 volts) and Vt spread (.05 volts). Compared to the baseline sinter process of a transistor processed with a conventional end-of-process 400 ° C. hydrogen passivation anneal 5004, the transistor formed with a hydrogen releasing film and a passivation trapping layer 5006 can be improved over the baseline sinter process 5004 It shows that.

  As mentioned above, deuterium can also be used in place of hydrogen for the passivation process of the disclosed embodiments. For example, SiD4 can be used instead of SiH4 in the formation of a hydrogen releasing film. Alternatively, deuterium containing gas may be added to the HDP during the formation of the hydrogen releasing film. Deuterium usually forms bonds with silicon that are more stable than hydrogen, and therefore deuterium can improve Vt stability (eg, Vt distribution) over time. The use of deuterium instead of hydrogen in the disclosed embodiments can provide a more cost effective passivation method than conventional furnace deuterium annealing. This is because the chamber size is much smaller, the reaction pressure is much lower, the deuterium concentration is much lower, and the process time is much shorter in a single wafer plasma process (compared to a batch furnace deuterium anneal process). Because.

  Exemplary process deposition conditions are given for an 8 inch deposition apparatus. One skilled in the art can use these 8-inch techniques for a 12-inch (or larger diameter) tool as a guide for developing an equivalent process.

While various embodiments have been described above, it should be understood that these embodiments are merely illustrative and not limiting. It will be appreciated that modifications can be made to the disclosed embodiments and that other embodiments can be implemented within the scope of the claims without departing from the scope of the claims. .

Claims (5)

A process for forming an integrated circuit comprising:
Providing a partially processed integrated circuit including a transistor;
Passivating the partially processed integrated circuit;
Depositing a passivation trapping layer on the transistor after the passivating step;
Forming a pre-metal dielectric (PMD) layer on the passivation trapping layer;
Etching at least one contact opening through the PMD layer and the passivation trapping layer in contact with the transistor after the forming step;
Including
The at least one contact opening is laterally adjacent to the gate of the transistor;
The process wherein the passivating step is an HDP process comprising at least one of hydrogen and deuterium. A process for forming an integrated circuit comprising:
Providing a partially processed integrated circuit including a transistor;
Passivating the partially processed integrated circuit;
Depositing a passivation trapping layer on the transistor after the passivating step;
Forming a pre-metal dielectric (PMD) layer on the passivation trapping layer;
Etching at least one contact opening through the PMD layer and the passivation trapping layer in contact with the transistor after the forming step;
Including
The at least one contact opening is laterally adjacent to the gate of the transistor;
The passivating step is depositing at least one of a hydrogen releasing layer and a deuterium releasing layer;
The hydrogen release layer Ri HDP SiNxHy film der with more Si-H bonds than N-H bond, Ru HDP SiNxDy film der of the deuterium discharge layer comprises more Si-D bonds than N-D bond, the process . A process for forming an integrated circuit comprising:
Providing a partially processed integrated circuit including a transistor;
Passivating the partially processed integrated circuit;
Depositing a passivation trapping layer on the transistor after the passivating step;
Forming a pre-metal dielectric (PMD) layer on the passivation trapping layer;
Etching at least one contact opening through the PMD layer and the passivation trapping layer in contact with the transistor after the forming step;
Including
The at least one contact opening is laterally adjacent to the gate of the transistor;
The passivating step is depositing at least one of a hydrogen releasing layer and a deuterium releasing layer;
A process wherein the hydrogen release layer is a HDP SiNxHy film with more Si-H bonds than N-H bonds and the deuterium release layer is an HDP SiNxDy film with more Si-D bonds than ND bonds. A process for forming an integrated circuit comprising:
Providing a partially processed integrated circuit including a transistor;
Passivating the partially processed integrated circuit;
Depositing a passivation trapping layer on the transistor after the passivating step;
Forming a pre-metal dielectric (PMD) layer on the passivation trapping layer;
Etching at least one contact opening through the PMD layer and the passivation trapping layer in contact with the transistor after the forming step;
Including
The at least one contact opening is laterally adjacent to the gate of the transistor;
The process, wherein the passivating step is a step of annealing the integrated circuit in at least one of an atmosphere containing hydrogen and an atmosphere containing deuterium. A process according to any one of claims 1 to 4,
The process, wherein the passivation trapping layer is a film selected from the group consisting of AlO, AlON, SiNx, and SiNxHy.