CN116564799A - Method for forming polycrystalline silicon film and method for controlling polycrystalline silicon film resistance - Google Patents
Method for forming polycrystalline silicon film and method for controlling polycrystalline silicon film resistance Download PDFInfo
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- CN116564799A CN116564799A CN202310626305.2A CN202310626305A CN116564799A CN 116564799 A CN116564799 A CN 116564799A CN 202310626305 A CN202310626305 A CN 202310626305A CN 116564799 A CN116564799 A CN 116564799A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 157
- 238000000034 method Methods 0.000 title claims abstract description 81
- 229920005591 polysilicon Polymers 0.000 claims abstract description 140
- 239000010410 layer Substances 0.000 claims abstract description 73
- 239000011241 protective layer Substances 0.000 claims abstract description 51
- 239000004065 semiconductor Substances 0.000 claims abstract description 43
- 238000000137 annealing Methods 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 41
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 28
- 150000002500 ions Chemical class 0.000 claims abstract description 20
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 14
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 13
- 239000010408 film Substances 0.000 claims description 69
- 239000010409 thin film Substances 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 9
- -1 phosphorus ions Chemical class 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- 239000002019 doping agent Substances 0.000 claims 1
- 239000012212 insulator Substances 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- AXQKVSDUCKWEKE-UHFFFAOYSA-N [C].[Ge].[Si] Chemical compound [C].[Ge].[Si] AXQKVSDUCKWEKE-UHFFFAOYSA-N 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02595—Microstructure polycrystalline
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a method for forming a polycrystalline silicon film and a method for controlling the resistance of the polycrystalline silicon film. Specifically, a doped polysilicon layer is deposited on a semiconductor substrate, then a protective layer is covered on the surface of the doped polysilicon layer, and then annealing treatment is carried out on the doped polysilicon layer to form a polysilicon film with the resistance meeting the design requirement. In the embodiment of the invention, before the doped polysilicon layer is annealed, a layer of protective layer which can be made of silicon dioxide is formed on the surface of the doped polysilicon layer, and then no matter how long the doped polysilicon layer is placed and then annealed, doped ions in the doped polysilicon layer are blocked by the protective layer with strong compactness and moderate thickness, and the phenomenon of escaping doped ions does not occur, namely, the resistance RS of the formed polysilicon film does not change along with the change of the interval time (placement time) between the doped polysilicon layer and the annealing treatment step of the doped polysilicon layer in the forming process.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a method for forming a polycrystalline silicon film and a method for controlling the resistance of the polycrystalline silicon film.
Background
Polysilicon (polycrystalline silicon) has semiconductor properties and is a very important good semiconductor material. The polysilicon needs ion heavy doping to reduce the resistivity, and at present, the existing polysilicon film forming method with a certain resistance value comprises the following steps: a doped polysilicon layer is formed and then directly annealed.
However, due to the process requirements of the semiconductor process, the difference of the standing time before the annealing treatment of the doped polysilicon layer can directly affect the resistance RS of the formed polysilicon film, that is, the longer the standing time, the smaller the resistance RS of the finally formed polysilicon film.
Therefore, how to solve the problem that the resistance RS of the polysilicon film changes with the change of the interval time (placement time) between the doped polysilicon and the annealing process in the forming process, so that the resistance RS of the finally formed polysilicon film is unstable or cannot meet the design requirement is a technical problem to be solved rapidly in the field.
Disclosure of Invention
The invention aims to provide a method for forming a polycrystalline silicon film and a method for controlling the resistance of the polycrystalline silicon film, which are used for solving the problem that the resistance RS of the finally formed polycrystalline silicon film is unstable or cannot meet the design requirement due to the fact that the resistance RS of the polycrystalline silicon film changes along with the change of the interval time (placement time) between doped polycrystalline silicon and annealing treatment steps in the forming process of the polycrystalline silicon film.
In order to solve the above technical problems, the present invention provides a method for forming a polysilicon film, which specifically includes the following steps:
providing a semiconductor substrate, and depositing a doped polysilicon layer on the semiconductor substrate;
forming a protective layer, wherein the protective layer covers the surface of the doped polysilicon layer;
and annealing the semiconductor substrate containing the protective layer to form the polysilicon film with the resistance meeting the design requirement.
Further, the material of the protective layer may include an oxide, and the oxide may be silicon dioxide.
Further, the thickness of the protective layer may be in the range of
Further, the annealing treatment performed on the semiconductor substrate including the protective layer may specifically include spike annealing treatment.
Further, the step of depositing a doped polysilicon layer on the semiconductor substrate may specifically include:
and placing the semiconductor substrate on a bearing table in a reaction cavity, and providing at least silicon source gas and doping source gas in the reaction cavity to form the doped polysilicon layer, wherein the doping source gas provides doping ions.
Further, the doping ions may include phosphorus ions, boron ions, or arsenic ions.
Further, the process of forming the protective layer may specifically include a thermal oxidation process, a physical vapor deposition process, or a chemical vapor deposition process, and of course, may also include other processes for forming an oxide layer.
Further, after annealing the semiconductor substrate including the protective layer, the method for forming the polysilicon film provided in the embodiment of the invention may further include: and measuring the resistance of the polysilicon film.
In a second aspect, based on the same inventive concept as the method for forming the polysilicon thin film, the embodiment of the invention further provides a method for controlling the polysilicon thin film resistor, which specifically may include:
and in the forming process of the polysilicon film, the resistance value of the polysilicon film is controlled by preventing the escape of doped ions doped in the doped polysilicon layer.
Further, the step of forming the polysilicon film may specifically be a method of forming a polysilicon film as described above, which will not be described in detail herein.
Further, the means for preventing the escape of the doped ions in the doped polysilicon layer may specifically include: and covering a protective layer on the surface of the doped polysilicon layer, wherein the material of the protective layer comprises oxide, and the oxide is silicon dioxide.
Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:
in the method for forming the polysilicon film or the method for controlling the polysilicon film resistor, a doped polysilicon layer is deposited on a semiconductor substrate, then a protective layer is covered on the surface of the doped polysilicon layer, and then annealing treatment is carried out on the surface of the doped polysilicon layer to form the polysilicon film with the resistance meeting the design requirement. In the embodiment of the invention, before the doped polysilicon layer is annealed, a layer of protective layer which can be made of silicon dioxide is formed on the surface of the doped polysilicon layer, so that doped ions in the doped polysilicon layer covered with the protective layer are blocked by the protective layer with strong compactness and moderate thickness in the annealing process, and the phenomenon of escape of the doped ions cannot occur, namely, the resistance RS of the formed polysilicon film cannot be changed along with the change of the interval time (placement time) between the doped polysilicon layer and the annealing process of the doped polysilicon layer in the forming process.
Drawings
FIG. 1 is a graph showing the comparison of the resistance RS of a doped polysilicon layer without a protective layer on the surface thereof before annealing treatment and the resistance RS after annealing treatment;
FIG. 2 is a flow chart illustrating a method for forming a polysilicon film according to an embodiment of the present invention;
fig. 3 is a graph showing a variation of a resistance value RS of a polysilicon film formed by the method for forming a polysilicon film shown in fig. 2 and a time interval (a set time) between an annealing process of a doped polysilicon layer and the annealing process of the doped polysilicon layer according to an embodiment of the present invention.
Detailed Description
As described in the background art, at present, the difference of the time of placing the doped polysilicon layer before the annealing treatment directly affects the resistance RS of the finally formed polysilicon film (i.e. the doped polysilicon after the annealing treatment), i.e. the longer the time of placing, the smaller the resistance RS of the finally formed polysilicon film.
Referring to fig. 1, fig. 1 is a graph comparing a resistance value RS of a doped polysilicon layer, the surface of which is not covered with a protective layer, before annealing treatment with a resistance value RS after annealing treatment; in fig. 1, a curve RS before splike anneal in the range of resistance RS from 1500Ω to 1700 Ω is a graph of the change in resistance RS of the doped polysilicon layer with the time interval (days) of placement before the annealing treatment, and a curve RS after splike anneal in the range of resistance RS from 300Ω to 700Ω is a graph of the change in resistance RS of the doped polysilicon layer with the time interval (days) of placement after the annealing treatment. Obviously, the longer the standing time, the smaller the resistance RS of the finally formed polysilicon thin film.
Therefore, the invention provides a method for forming a polysilicon film and a method for controlling the resistance of the polysilicon film, which are used for solving the problem that the resistance RS of the finally formed polysilicon film is unstable or cannot meet the design requirement due to the fact that the resistance RS of the polysilicon film is changed along with the change of the interval time (placement time) between doped polysilicon and annealing treatment steps in the forming process.
The method for forming the polysilicon thin film and the method for controlling the polysilicon thin film resistance according to the present invention are described in further detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than as described herein, and therefore the present invention is not limited to the specific embodiments disclosed below.
As used in this application and in the claims, the terms "a," "an," "the," and/or "the" are not specific to the singular, but may include the plural, unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that the steps and elements are explicitly identified, and they do not constitute an exclusive list, as other steps or elements may be included in a method or apparatus. In describing embodiments of the present invention in detail, the cross-sectional view of the device structure is not partially exaggerated to a general scale for convenience of explanation, and the schematic drawings are only examples and should not limit the scope of the present invention herein. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
Referring to fig. 2, fig. 2 is a flow chart illustrating a method for forming a polysilicon film according to an embodiment of the invention; as shown in fig. 2, the method for forming a polysilicon film provided by the present invention at least includes the following steps:
step S100, providing a semiconductor substrate, and depositing a doped polysilicon layer on the semiconductor substrate;
step S200, forming a protective layer, wherein the protective layer covers the surface of the doped polysilicon layer;
and step S300, annealing the semiconductor substrate containing the protective layer to form the polysilicon film with the resistance meeting the design requirement.
In the above step S100, a semiconductor substrate may be provided first, wherein the semiconductor substrate may specifically be any suitable substrate material known in the art, for example, may be at least one of the following mentioned materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III/V compound semiconductors, and also include multilayer structures made of these semiconductors, or are silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or may be Double polished silicon wafers (Double SidePolishedWafers, DSP), ceramic substrates such as aluminum oxide, quartz, or glass substrates, or the like. The semiconductor substrate in this embodiment is, for example, a silicon wafer.
The semiconductor substrate may be a substrate in a front end of line (FEOL) of integrated circuit fabrication, or may be a substrate entering a back end of line (BEOL) of integrated circuit fabrication, and various structures (not shown) may be defined in or on the surface of the semiconductor substrate, for example, an isolation structure may be formed in the semiconductor substrate, and the isolation structure may be a Shallow Trench Isolation (STI) structure or a local silicon oxide (LOCOS) isolation structure, and an active region of the semiconductor substrate may be defined by the isolation structure.
In addition, in the method for forming a polysilicon film according to the embodiment of the present invention, the polysilicon film may be formed as a single film layer, for example, a polysilicon resistor, or may be a part of a film layer in a semiconductor structure, which is not particularly limited.
Next, a doped polysilicon layer may be formed on the surface of the semiconductor substrate by using a deposition process, and in particular, a specific implementation manner of forming the doped polysilicon layer is provided in the embodiments of the present invention as follows:
step S101, placing the semiconductor substrate on a carrier in a reaction chamber, and providing at least a silicon source gas and a doping source gas into the reaction chamber to form the doped polysilicon layer, where the doping source gas provides doping ions, and the doping ions may include phosphorus ions or boron ions, for example, and then performing step S200.
In the step S200, a film forming process such as a thermal oxidation process, a chemical vapor deposition process, a physical vapor deposition process, an ALD atomic layer deposition process, etc. may be used to cover a protective layer with a certain thickness on the surface of the doped polysilicon layer, which is a preferred example, and in the embodiment of the present invention, the material of the protective layer is an oxide, that is, specifically, silicon dioxide, and then, in step S300, the range of the thickness of the formed protective layer (silicon dioxide) may beThat is, it may be specifically +> And a range of any two of the above values and values within the range.
In the step S300, after forming the protective layer made of silicon dioxide, the semiconductor substrate containing the protective layer may be annealed to form a polysilicon film with a resistance meeting the design requirements.
As a preferred example, in the embodiment of the present invention, the annealing treatment performed on the semiconductor substrate including the protective layer may specifically be a spike annealing treatment, and the temperature of the spike annealing treatment may be, for example, 1000 ℃ to 1100 ℃.
Further, after the annealing treatment is performed on the semiconductor substrate in the step S300 to form the polysilicon film, the method may further include the following steps:
step S400, measuring the resistance RS of the polysilicon film.
Referring to fig. 3, a graph of the variation of the resistance RS of a polysilicon film formed by the method according to an embodiment of the present invention and the interval time (standing time) between the doped polysilicon layer and the annealing process is shown in an embodiment of the present invention. In FIG. 3, the ordinate is the resistance RS of the polysilicon film and the abscissa is the thickness of the CAP filmThe correspondence between the silicon dioxide protective layers (OX and active OX) is plotted when the intervals (0 days, 45 days) between the doped polysilicon layer during the formation and the annealing step are different.
Obviously, the resistance RS of the polysilicon thin film formed varies little regardless of the interval time. In the embodiment of the invention, before the doped polysilicon layer is annealed, a layer of protective layer which can be made of silicon dioxide is formed on the surface of the doped polysilicon layer, and then no matter how long the doped polysilicon layer is placed and then annealed, doped ions in the doped polysilicon layer cannot escape due to the blocking of the protective layer with strong compactness and moderate thickness in the annealing process, namely, the aim that the resistance RS of the formed polysilicon film cannot change along with the change of the interval time (placement time) between the doped polysilicon layer and the annealing process is realized.
Based on the same inventive concept as the method for forming the polysilicon film shown in fig. 2, the embodiment of the invention also provides a method for controlling the polysilicon film resistor, which specifically includes the following steps:
and in the forming process of the polysilicon film, the resistance value of the polysilicon film is controlled by preventing the escape of doped ions doped in the doped polysilicon layer.
Specifically, the step of forming the polysilicon thin film may include the steps of:
providing a semiconductor substrate, and depositing a doped polysilicon layer on the semiconductor substrate;
forming a protective layer, wherein the protective layer covers the surface of the doped polysilicon layer;
and annealing the semiconductor substrate containing the protective layer to form the polysilicon film with the resistance meeting the design requirement.
Further, the means for preventing escape of doped ions doped in the doped polysilicon layer includes: covering a protective layer on the surface of the doped polysilicon layer, wherein the material of the protective layer comprises oxide, the oxide is silicon dioxide, and the thickness of the protective layer can be in the range of The annealing treatment performed on the semiconductor substrate including the protective layer includes spike annealing treatment.
In summary, in the method for forming a polysilicon film or the method for controlling a polysilicon film resistor provided in the embodiments of the present invention, a doped polysilicon layer is deposited on a semiconductor substrate, then a protective layer is covered on the surface of the doped polysilicon layer, and then annealing treatment is performed to form a polysilicon film with a resistance value meeting design requirements. In the embodiment of the invention, before the doped polysilicon layer is annealed, a layer of protective layer which can be made of silicon dioxide is formed on the surface of the doped polysilicon layer, and then no matter how long the doped polysilicon layer is placed and then annealed, doped ions in the doped polysilicon layer are blocked by the protective layer with strong compactness and moderate thickness, and the phenomenon of escaping doped ions cannot occur, namely, the resistance RS of the formed polysilicon film cannot be changed along with the change of the interval time (placement time) between the doped polysilicon layer and the annealing treatment step of the doped polysilicon layer in the forming process.
It should be noted that although the present invention has been disclosed in the preferred embodiments, the above embodiments are not intended to limit the present invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.
It should be further understood that the terms "first," "second," "third," and the like in this specification are used merely for distinguishing between various components, elements, steps, etc. in the specification and not for indicating a logical or sequential relationship between the various components, elements, steps, etc., unless otherwise indicated. The meaning of "and/or" herein is either or both.
It should also be understood that the terminology described herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses, and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood as having the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates the contrary. Furthermore, implementation of the methods and/or apparatus in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.
Claims (11)
1. A method for forming a polysilicon film, comprising:
providing a semiconductor substrate, and depositing a doped polysilicon layer on the semiconductor substrate;
forming a protective layer, wherein the protective layer covers the surface of the doped polysilicon layer;
and annealing the semiconductor substrate containing the protective layer to form the polysilicon film with the resistance meeting the design requirement.
2. The method of forming a polysilicon film according to claim 1, wherein the material of the protective layer comprises an oxide, and the oxide is silicon dioxide.
3. The method for forming a polysilicon film according to claim 1 or 2, wherein the protective layer has a thickness ranging from
4. The method of forming a polysilicon film according to claim 1, wherein the annealing treatment performed on the semiconductor substrate including the protective layer includes spike annealing treatment.
5. The method of forming a polysilicon film according to claim 1, wherein the step of depositing a doped polysilicon layer on the semiconductor substrate comprises:
and placing the semiconductor substrate on a bearing table in a reaction cavity, and providing at least silicon source gas and doping source gas in the reaction cavity to form the doped polysilicon layer, wherein the doping source gas provides doping ions.
6. The method of claim 5, wherein the dopant ions comprise phosphorus ions, boron ions, or arsenic ions.
7. The method of forming a polysilicon film according to claim 2, wherein the process of forming the protective layer comprises a thermal oxidation process, a physical vapor deposition process, or a chemical vapor deposition process.
8. The method for forming a polycrystalline silicon thin film according to claim 1, wherein after annealing the semiconductor substrate including the protective layer, the method further comprises: and measuring the resistance value of the polycrystalline silicon film.
9. The control method of the polysilicon thin film resistor is characterized by comprising the following steps:
and in the forming process of the polysilicon film, the resistance value of the polysilicon film is controlled by preventing the escape of doped ions doped in the doped polysilicon layer.
10. The method of controlling a polysilicon thin film resistor according to claim 9, wherein the step of forming the polysilicon thin film includes the method of forming a polysilicon thin film according to any one of claims 1 to 8.
11. The method of claim 10, wherein the preventing the escape of the doped ions within the doped polysilicon layer comprises: and covering a protective layer on the surface of the doped polysilicon layer, wherein the material of the protective layer comprises oxide, and the oxide is silicon dioxide.
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| CN202310626305.2A CN116564799A (en) | 2023-05-31 | 2023-05-31 | Method for forming polycrystalline silicon film and method for controlling polycrystalline silicon film resistance |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310626305.2A CN116564799A (en) | 2023-05-31 | 2023-05-31 | Method for forming polycrystalline silicon film and method for controlling polycrystalline silicon film resistance |
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| CN202310626305.2A Pending CN116564799A (en) | 2023-05-31 | 2023-05-31 | Method for forming polycrystalline silicon film and method for controlling polycrystalline silicon film resistance |
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