CN113378499B - Fuse trimming circuit and equipment applied to integrated circuit - Google Patents
Fuse trimming circuit and equipment applied to integrated circuit Download PDFInfo
- Publication number
- CN113378499B CN113378499B CN202110698982.6A CN202110698982A CN113378499B CN 113378499 B CN113378499 B CN 113378499B CN 202110698982 A CN202110698982 A CN 202110698982A CN 113378499 B CN113378499 B CN 113378499B
- Authority
- CN
- China
- Prior art keywords
- fuse
- circuit
- sets
- fuses
- page
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/3312—Timing analysis
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
Abstract
The invention provides a fuse trimming circuit and equipment applied to an integrated circuit, wherein the fuse trimming circuit comprises m fuse sets and m output lines corresponding to the m fuse sets, any one fuse set in the m fuse sets at least comprises a fuse, and each fuse in any one fuse set in the m fuse sets is connected with a corresponding one of the m output lines; the maximum number of fuses in each of the m fuse sets is n; the fuse bank is also provided with n page selection registers corresponding to the maximum value n, and the fuses in each fuse bank in the m fuse banks are connected with different one page selection register; each output line of m output lines in the fuse circuit is connected with one bit selection unit; each bit selection unit is connected with a bias structure; each page select register in the fuse circuit is connected to one word select unit. The invention does not need to add extra complex process version, effectively reduces the area requirement and directly reads the trimming parameter value.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a fuse trimming circuit and device applied to an integrated circuit.
Background
Fuses in integrated circuits are a common way to modify voltage, current, and fix code. The technology of secondary development after the integrated circuit is manufactured occupies an important position in the integrated circuit trimming due to the characteristics of simple implementation mode, high visualization and the like. However, as the integrated circuit manufacturing line scale is reduced, the whole area of the chip is reduced, and the disadvantage of the fuse trimming occupied area gradually appears, especially in some PAD Limited (the core area of the chip is too small, and the pins required by the chip are too many, so that a chip with small function uses a very large silicon area, which is more than what is expected by planning, called PAD Limited), the problem is particularly prominent. Of course, as manufacturing processes are advanced, new processes provide more fuse trimming schemes, such as EEROM bit cell trimming, EFUSE programming, and the like. The methods increase the process version or increase the chip area, are not visualized during burning, and increase the complexity of design.
Disclosure of Invention
The invention provides a fuse trimming circuit and a fuse trimming device applied to an integrated circuit, which can effectively reduce the area requirement without increasing additional complex process version and can directly read the trimming parameter value.
A fuse trimming circuit applied to an integrated circuit comprises m fuse sets and m output lines corresponding to the m fuse sets, wherein any one of the m fuse sets at least comprises one fuse, and each fuse in any one of the m fuse sets is connected with a corresponding one of the m output lines;
the maximum number of fuses in each of the m fuse sets is n;
the fuse trimming circuit is also provided with n page selection registers corresponding to the maximum value n, and the fuses in each fuse set in the m fuse sets are connected with different one page selection register;
each output line of m output lines in the fuse circuit is connected with a bit selection unit;
each bit selection unit is connected with a bias structure;
each page selection register in the fuse trimming circuit is connected with a word selection unit;
m is an integer greater than 1, and n is an integer not less than 1.
Preferably, the fuses in each of the m fuse sets have numbers sequentially from small to large, and the maximum number value of the m fuse sets including the maximum number of fuses is n;
the n page selection registers are n page selection registers which are numbered sequentially from small to large; and
fuses having the same number in each of the m fuse banks are connected to a corresponding one of the page select registers having the same number.
Preferably, the fuses in each of the m fuse sets are numbered from small to large in sequence starting from 1.
Preferably, any one of the m fuse sets has the same number of fuses.
A device comprising a fuse repair circuit as described above.
The invention realizes the multiplexing of the fuse main body structure by adding a certain sequential logic control, and can read the trimming parameter values in a time division multiplexing mode. The invention does not need to add extra complex process version, effectively reduces the area requirement, provides an intuitive solution for trimming parameters of the integrated circuit, and particularly has obvious effect on non-continuous parameters such as fixed codes or voltage.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic circuit diagram according to an embodiment;
FIG. 2 is a schematic diagram of a programming timing sequence according to an embodiment;
FIG. 3 is a diagram illustrating an embodiment of a readout timing sequence.
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention.
With reference to fig. 1, the present embodiment provides a fuse circuit applied in an integrated circuit, where the fuse circuit includes m fuse banks and m output lines corresponding to the m fuse banks, where any one of the m fuse banks includes at least one fuse, each fuse in any one of the m fuse banks is connected to a corresponding one of the m output lines, and m is an integer greater than 1.
By applying programming capacitive energy to the output lines and fuses, the fuses can be linked or disconnected, and specifically, by sequential logic control of the programming, multiplexing of the fuse body structure can be achieved.
In another implementation manner of this embodiment, the maximum number of fuses in each of the m fuse sets is n;
the fuse circuit further has n page selection registers corresponding to the maximum value n;
fuses in each of the m fuse banks are connected to a different one of the page select registers;
and n is an integer not less than 1.
In another implementation manner of this embodiment, in order to better correspond the fuses to the page selection register, the fuses in each of the m fuse sets have numbers sequentially from small to large, and a maximum number value of the m fuse sets, which includes the maximum number of fuses, is n;
the n page selection registers are n page selection registers which are numbered sequentially from small to large; and
fuses having the same number in each of the m fuse banks are connected to a corresponding one of the page select registers having the same number.
Wherein the fuses in each of the m fuse sets may be numbered sequentially from small to large starting with 1.
As can be understood from the above, the circuit can be more conveniently controlled by adopting sequential logic by adopting a coding mode. Of course, the encoding method adopted by the embodiment is not unique, and other implementation methods may also be adopted, the embodiment is not further described, and the embodiment is not limited to be a single one, but rather, those skilled in the art may deeply understand the embodiment.
In addition, it is understood that any one of the m fuse sets may have the same number of fuses. The method controls the linking or the disconnection of the fuse, and is more convenient and faster in programming and time sequence control due to the same quantity.
The embodiment also provides a fuse trimming circuit, which comprises the fuse circuit as described above.
In this embodiment, one bit selection unit is connected to each of the m output lines in the fuse circuit.
In this embodiment, each of the bit selection units is connected to a bias structure.
In this embodiment, each page selection register in the fuse circuit is connected to one word selection unit.
The present embodiment also provides a device comprising a fuse circuit as described above, or a device comprising a fuse repair circuit as described above.
As shown in fig. 1, which illustrates an optimal circuit schematic, m fuse sets each having n fuses fuse1.
The m output lines are sequentially out [1]... eta.. out [ m ].
An output line out [1] connects the fuses fuse1..... fusen in the first fuse set, and so on, and an output line out [ m ] connects the fuses fuse1..... fusen in the mth fuse set.
Page [ n ] sel is n Page select registers.
Fuse1 in each fuse set is connected to Page [1] sel, and so on, and the fusen in the first fuse set is connected to Page [ n ] sel.
Page [1]. Page [ n ] is a word selection unit, Page [1] and Page [1] sel, and so on, Page [ n ] is connected with Page [ n ] sel. Wherein, word selection unit is grounded respectively.
bit [1] to bit [ m ] are bit selection cells, bit [1] is connected with out [1] through a resistor, and so on, bit [ m ] is connected with out [ m ] through a resistor.
bias structure, m bias structures are connected with m bit selection units respectively.
Referring to fig. 2, in the embodiment, during programming, the programming is completed in the middle test process after the wafer production is completed, and during the programming, the page [ y ] sel and the negative electrode of the programming capacitor are grounded, the programming capacitor is charged to 5V, and the programming is completed by discharging the out [ x ]. And when the programming is finished, the resistance of the outx and the page y sel is positively measured by adding the outx, when the resistance is more than 500K, the programming is proved to be successful, otherwise, the previous actions are repeated. The content of programming can be fixed coding, given by a circuit design scheme, determining the link or disconnection of fuse [ x, y ], and other out [ ext (x) ] and page [ ext (y) ] sel have no power supply connection, form floating, and have the same level and form equipotential. Wherein x and y are positive integers and are less than or equal to m.
Further, as shown in FIG. 3, when the fuse value is read out, the chip select page [ y ] and the bit select bit [ x ] are asserted, and out [ x, y ] can be read out. That is, when the combined timing comes when the page [ y ] signal is high and the bit [ x ] signal is low, the out [ x, y ] is read out and used as a set of parameters of the circuit to realize a certain function of the circuit.
According to the content of the embodiment, compared with the fuse structure of the EEROM, the fuse structure of the EEROM has the advantages that special process steps and devices are not needed, and the process version number is reduced;
compared with the programming EFUSE structure, the structure reduces the control complexity, increases the intuition of trimming and debugging and saves the area at the same time;
it is verified that the present embodiment can omit nearly (m/n × m)% of the area compared to the conventional fuse structure. Compared with the conventional fuse structure, the present embodiment can save about (m/n × m)% of power consumption. Compared with the conventional fuse structure, the present embodiment can improve the characteristics of (n × m/m)% PAD limited.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (5)
1. A fuse trimming circuit applied to an integrated circuit is characterized in that:
the fuse trimming circuit comprises m fuse sets and m output lines corresponding to the m fuse sets, wherein any one of the m fuse sets at least comprises one fuse, and each fuse in any one of the m fuse sets is connected with a corresponding one of the m output lines;
the maximum number of fuses in each of the m fuse sets is n;
the fuse trimming circuit is also provided with n page selection registers corresponding to the maximum value n, and the fuses in each fuse set in the m fuse sets are connected with different one page selection register;
each output line of m output lines in the fuse trimming circuit is connected with a bit selection unit;
each bit selection unit is connected with a bias structure;
each page selection register in the fuse circuit is connected with a word selection unit;
m is an integer greater than 1, and n is an integer not less than 1.
2. The fuse trimming circuit of claim 1, wherein:
the fuses in each fuse set in the m fuse sets are sequentially numbered from small to large, and the maximum number value of the m fuse sets including the maximum fuse number is n;
the n page selection registers are n page selection registers which are numbered sequentially from small to large; and
fuses having the same number in each of the m fuse banks are connected to a corresponding one of the page select registers having the same number.
3. The fuse trimming circuit of claim 2, wherein:
the fuses in each of the m fuse sets are numbered from small to large in sequence starting with 1.
4. A fuse circuit for use in an integrated circuit according to any of claims 1 to 3, wherein:
any one of the m fuse sets has the same number of fuses.
5. An apparatus comprising the fuse trimming circuit of any one of claims 1 to 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110698982.6A CN113378499B (en) | 2021-06-23 | 2021-06-23 | Fuse trimming circuit and equipment applied to integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110698982.6A CN113378499B (en) | 2021-06-23 | 2021-06-23 | Fuse trimming circuit and equipment applied to integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113378499A CN113378499A (en) | 2021-09-10 |
| CN113378499B true CN113378499B (en) | 2022-04-19 |
Family
ID=77578732
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110698982.6A Active CN113378499B (en) | 2021-06-23 | 2021-06-23 | Fuse trimming circuit and equipment applied to integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113378499B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1226991A (en) * | 1997-05-21 | 1999-08-25 | 爱特梅尔股份有限公司 | Semiconductor memory for secure data storage |
| KR20150063759A (en) * | 2013-12-02 | 2015-06-10 | 에스케이하이닉스 주식회사 | Semiconductor device |
| CN107528576A (en) * | 2016-06-22 | 2017-12-29 | 许亚夫 | A kind of high performance switch power supply chip trims circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6462985B2 (en) * | 1999-12-10 | 2002-10-08 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory for storing initially-setting data |
-
2021
- 2021-06-23 CN CN202110698982.6A patent/CN113378499B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1226991A (en) * | 1997-05-21 | 1999-08-25 | 爱特梅尔股份有限公司 | Semiconductor memory for secure data storage |
| KR20150063759A (en) * | 2013-12-02 | 2015-06-10 | 에스케이하이닉스 주식회사 | Semiconductor device |
| CN107528576A (en) * | 2016-06-22 | 2017-12-29 | 许亚夫 | A kind of high performance switch power supply chip trims circuit |
Non-Patent Citations (2)
| Title |
|---|
| Fuse-monitoring system for multiple fuse circuits;G. R. Lezan;《 Electrical Engineering ( Volume: 77, Issue: 2, Feb. 1958)》;19580228;第154-157页 * |
| SOC的可测性设计策略;徐智伟 等;《计算机测量与控制》;20080825;第1095-1098页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113378499A (en) | 2021-09-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9865359B2 (en) | Semiconductor device including fuse circuit | |
| US7373573B2 (en) | Apparatus and method for using a single bank of eFuses to successively store testing data from multiple stages of testing | |
| US8289770B2 (en) | Semiconductor memory device and system including the same | |
| CN112420116A (en) | Apparatus and method for fuse error detection | |
| US8391091B2 (en) | Anti-fuse circuit and method for anti-fuse programming and test thereof | |
| CN115985380B (en) | FeFET array data verification method based on digital circuit control | |
| TWI655637B (en) | Memory device | |
| US9627059B2 (en) | Resistive memory and data writing method for memory cell thereof | |
| CN100368818C (en) | Test module and test method in use for electrical erasable memory built in chip | |
| WO1982002793A1 (en) | Semiconductor memory redundant element identification circuit | |
| TW200400513A (en) | Semiconductor memory device with built-in self-diagnostic function and semiconductor device having the semiconductor memory device | |
| CN113378499B (en) | Fuse trimming circuit and equipment applied to integrated circuit | |
| EP1724788A1 (en) | Improved built-in self-test method and system | |
| CN116631486A (en) | Low-complexity internal memory built-in self-test circuit | |
| US6601204B1 (en) | Pattern generating method, pattern generator using the method, and memory tester using the pattern generator | |
| CN110350910B (en) | Circuit for FT trimming based on EPROM and Pin multiplexing | |
| CN110827878B (en) | Memory device | |
| CN114067899A (en) | Memory built-in self-test system and method for realizing rapid test | |
| CN205911022U (en) | A device for calibrating analog integrated circuit | |
| CN114743585B (en) | Programming method and device for testing flash memory and flash memory | |
| JP2011034642A (en) | Memory test circuit, semiconductor integrated circuit, and memory test method | |
| CN101984492B (en) | A kind of structure and method thereof reducing standby power consumption of flash memory | |
| TWI730767B (en) | Memory device | |
| JPH10112198A (en) | Semiconductor memory | |
| CN115148270B (en) | ID coding fuse array fusing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |