CN113363340A - Heterojunction battery and preparation method thereof - Google Patents
Heterojunction battery and preparation method thereof Download PDFInfo
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- 238000000034 method Methods 0.000 claims abstract description 53
- 230000008569 process Effects 0.000 claims abstract description 33
- 229910021419 crystalline silicon Inorganic materials 0.000 claims abstract description 31
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- 238000004519 manufacturing process Methods 0.000 claims description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 238000005137 deposition process Methods 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 6
- 238000007650 screen-printing Methods 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 26
- 238000000151 deposition Methods 0.000 abstract description 13
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- 230000000694 effects Effects 0.000 description 7
- 238000005240 physical vapour deposition Methods 0.000 description 7
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Abstract
The embodiment of the application provides a heterojunction cell and a preparation method thereof, belonging to the technical field of solar cells2The intrinsic amorphous silicon layer with a three-layer structure is formed by doping the amorphous silicon layer, and the specific operation process flow is as follows: providing a crystalline silicon substrate; cleaning and texturing; preparing a first layer on at least one of the P-side and N-side of the substrate by CVD deposition, the first layer being CO2Doping the amorphous silicon layer; preparing a second layer and a third layer on the second layer on the P surface and the N surface of the substrate obtained in the previous step by adopting a CVD (chemical vapor deposition) process, wherein the second layer is a non-H-doped intrinsic layerAnd the third layer is an H-doped intrinsic amorphous silicon layer. Through the processing scheme, the interface passivation quality is improved, the photo-generated current and the open-circuit voltage are both increased, and the battery conversion efficiency is improved.
Description
Technical Field
The application relates to the technical field of solar cells, in particular to a heterojunction cell and a preparation method thereof.
Background
As an alternative to traditional energy power generation technology, "photovoltaic" is considered one of the most promising new energy industries. In recent years, photovoltaic industry mainly using solar cells has been developed in a large scale, and one of them is a Heterojunction with Intrinsic thin film (HJT) cell.
The process flow of the traditional heterojunction battery is as follows: cleaning and texturing → CVD (Chemical Vapor Deposition) Deposition of amorphous silicon thin film → PVD (Physical Vapor Deposition) Deposition of Transparent Conductive Oxide thin film → screen printing. The amorphous silicon film comprises an intrinsic amorphous silicon layer and an impurity-doped amorphous silicon layer, the intrinsic amorphous silicon layer is introduced to inhibit epitaxial growth of substrate crystalline silicon, and the interface quality is improved, so that the photoelectric conversion efficiency of the cell is improved.
The intrinsic amorphous silicon film layer generally has a two-layer structure, the first layer is an intrinsic amorphous silicon layer, and the second layer is an intrinsic amorphous silicon layer. The problems of unsatisfactory passivation effect of an intrinsic amorphous silicon layer and difficult optimization of thickness exist in the prior art. It is generally believed that increasing the thickness of the first intrinsic amorphous silicon layer is effective in improving the quality of interface passivation, but the increase in thickness results in an increase in cell series resistance and a decrease in light that can be absorbed and converted by the substrate crystalline silicon, so that the cell current decreases and the photoelectric conversion efficiency decreases. The intrinsic amorphous silicon film layer is too thin, the passivation effect is not ideal, and the open-circuit voltage of the battery can be reduced.
Disclosure of Invention
In view of the above, embodiments of the present disclosure provide a method for manufacturing a heterojunction cell and a heterojunction cell, which are used to improve the passivation effect of the heterojunction cell, and at least partially solve the problems in the prior art.
In a first aspect, the present application provides a method of fabricating a heterojunction battery, the method comprising:
providing a crystalline silicon substrate, wherein one side of the substrate is a P surface, and the other side of the substrate is an N surface;
cleaning and texturing the substrate;
preparing a first layer on at least one of the P-side and N-side of the substrate, the first layer being CO2Doping the amorphous silicon layer;
and preparing a second layer and a third layer on the second layer on the P surface and the N surface of the substrate after the first layer is prepared, wherein the second layer is an H-free doped intrinsic amorphous silicon layer, and the third layer is an H-doped intrinsic amorphous silicon layer.
According to a specific implementation manner of the embodiment of the application, the thickness of the first layer is in a range of 0.5-3nm, the thickness of the second layer is in a range of 3-5nm, and the thickness of the third layer is in a range of 4-6 nm.
According to a specific implementation manner of the embodiment of the present application, a manufacturing process of the first layer is as follows: the process temperature range is 180-4The gas flow range is 200-2The gas flow range is 200-400sccm, the gas pressure range is 50-100Pa, and the electrode spacing range is 23-30 mm.
According to a specific implementation manner of the embodiment of the present application, a manufacturing process of the first layer is as follows: the process temperature range is 180-4The gas flow range is 200-2The gas flow range is 200-400sccm, the gas pressure range is 50-100Pa, and the electrode spacing range is 23-30 mm.
According to a specific implementation manner of the embodiment of the present application, a manufacturing process of the second layer is as follows: the process temperature range is 180-4The gas flow range is 600-1500sccm, the gas pressure range is 50-100Pa, and the electrode spacing range is 23-30 mm.
According to a specific implementation manner of the embodiment of the present application, a specific manufacturing process of the third layer is as follows: the process temperature range is 180-4The gas flow range is 1000-2The gas flow range is 1000-5000sccm, the gas pressure range is 50-100Pa, and the electrode spacing range is 23-30 mm.
According to a specific implementation manner of the embodiment of the present application, after the step of preparing the second layer and the third layer on the second layer on both the P-side and the N-side of the substrate after the first layer is prepared, the method further includes the steps of:
preparing a P-type doped layer on the third layer of the P surface of the substrate, and preparing an N-type doped layer on the third layer of the N surface of the substrate;
respectively preparing transparent conducting layers on the p-type doping layer and the n-type doping layer;
and respectively carrying out screen printing on the P-surface transparent conductive layer of the substrate and the N-surface transparent conductive layer of the substrate.
According to a specific implementation manner of the embodiment of the application, the crystalline silicon is an n-type silicon wafer, and the thickness range of the n-type silicon wafer is 100-160 um.
According to a specific implementation manner of the embodiment of the application, the first layer, the second layer and the third layer are prepared by adopting a PECVD (plasma enhanced chemical vapor deposition) deposition process, and the transparent conducting layer is prepared by adopting a PVD (physical vapor deposition) deposition process.
In a second aspect, the present application provides a heterojunction cell comprising a crystalline silicon substrate and an intrinsic amorphous silicon layer of a double-layer structure located on both sides of the crystalline silicon substrate, and a layer of CO is disposed between the crystalline silicon substrate and the intrinsic amorphous silicon layer of the double-layer structure on at least one side2The doped amorphous silicon layer forms an intrinsic amorphous silicon layer with a three-layer structure, and the heterojunction cell further comprises a p-type doped layer, an n-type doped layer and a transparent conducting layer which are positioned on the intrinsic amorphous silicon layer.
Advantageous effects
According to the preparation method of the heterojunction cell provided by the embodiment of the application, on the basis of the existing process, a layer of doped CO is added between crystalline silicon and an intrinsic amorphous silicon layer2The amorphous silicon layer improves the interface passivation quality, does not need to greatly change the traditional intrinsic amorphous silicon layer, does not need to increase other equipment, increases both the photoproduction current and the open-circuit voltage, and improves the conversion efficiency of the cell.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a structural diagram of a heterojunction battery of example 1 of the present application;
fig. 2 is a structural view of a heterojunction battery of example 2 of the present application;
fig. 3 is a further structural view of a heterojunction battery of example 2 of the present application;
fig. 4 is a structural view of a heterojunction battery of a comparative example of the present application;
fig. 5 is a graph showing the test results of a heterojunction cell of example 3 of the present application.
In the drawings, wherein:
1-crystalline silicon; 2-a first layer; 3-a second layer; 4-a third layer; 5-P side; 6-N side.
Detailed Description
The embodiments of the present application will be described in detail below with reference to the accompanying drawings.
The following description of the embodiments of the present application is provided by way of specific examples, and other advantages and effects of the present application will be readily apparent to those skilled in the art from the disclosure herein. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. The present application is capable of other and different embodiments and its several details are capable of modifications and/or changes in various respects, all without departing from the spirit of the present application. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It is noted that various aspects of the embodiments are described below within the scope of the appended claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present application, one skilled in the art should appreciate that one aspect described herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. Additionally, such an apparatus may be implemented and/or such a method may be practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present application, and the drawings only show the components related to the present application rather than the number, shape and size of the components in actual implementation, and the type, amount and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.
In a first aspect, embodiments of the present application provide a method for fabricating a heterojunction cell, including adding a layer of CO between crystalline silicon and a double-layer intrinsic amorphous silicon layer structure2The doped amorphous silicon layer forms an intrinsic amorphous silicon layer having a three-layered structure including an intrinsic amorphous silicon layer without H-doping and an intrinsic amorphous silicon layer with H-doping. The present invention will be further described with reference to the following detailed description.
Example 1
The embodiment of the application provides a preparation method of a heterojunction cell, which comprises the step of adding a layer of CO between the P surface side of crystalline silicon and a traditional double-layer intrinsic amorphous silicon layer structure2The doped amorphous silicon layer forms an intrinsic amorphous silicon layer having a three-layer structure, considering that in the conventional preparation of the intrinsic amorphous silicon layer, the intrinsic amorphous silicon layer having a high deposition rate, the film quality, and the intrinsic amorphous silicon layer having a high deposition rate have different effects on the film qualityThe amount is not so good that the film quality of the intrinsic amorphous silicon layer of low deposition rate is good, and thus different deposition rates can be used for the preparation of the first layer.
The specific operation process flow comprises the following steps:
and S1, selecting the crystalline silicon 1 as a substrate, wherein one side surface of the substrate is a P surface 5, and the other side surface is an N surface 6. In the embodiment of the present application, the crystalline silicon 1 is an n-type silicon wafer, and the n-type silicon wafer is relatively insensitive to metal impurities and many non-metal defects, in other words, the n-type silicon has a good tolerance, and minority carriers thereof have a long and stable diffusion length, so that the crystalline silicon has the advantages of a long minority carrier lifetime, low light attenuation, excellent low-light characteristics, and easy preparation of a double-sided battery. Preferably, the thickness of the n-type silicon wafer is 130 um.
S2, cleaning and texturing the substrate, wherein the cleaning and texturing process mainly comprises the steps of pre-cleaning the crystalline silicon 1, removing a damaged layer on the surface of the silicon, texturing, cleaning the silicon wafer, drying, blanking and taking the pressure rod, and the texturing stage is a light trapping structure and is beneficial to light absorption.
S3, preparing a first layer 2 on the P surface 5 of the substrate by adopting a CVD (chemical vapor deposition) deposition process, wherein the first layer 2 is CO2The specific manufacturing process of the doped amorphous silicon layer comprises the following steps: the process temperature is 200 ℃, the preheating time is 10min, the power is 300W, and SiH4Gas flow 300sccm, CO2A gas flow of 300sccm, a gas pressure of 75Pa, a pole pitch of 26mm, and a thickness of the first layer 2 of 1.5 nm.
S4, preparing a second layer 3 and a third layer 4 on the second layer 3 on a P-side 5 of the substrate obtained in the previous step by using a CVD deposition process, and preparing the second layer 3 and the third layer 4 on the second layer 3 on an N-side 6, wherein the second layer 3 is an H-free intrinsic amorphous silicon layer, and the specific manufacturing process is as follows: the process temperature is 200 ℃, the preheating time is 10min, the power is 450W, and SiH4The gas flow is 1050sccm, the gas pressure is 75Pa, the inter-polar distance is 26mm, and the thickness of the second layer 3 is 4 nm;
the third layer 4 is an H-doped intrinsic amorphous silicon layer, and the specific manufacturing process is as follows: process temperaturePreheating at 200 deg.C for 10min with power of 450W and SiH4Gas flow rate 3000sccm, H2The gas flow rate is 3000sccm, the gas pressure is 75Pa, the inter-polar distance is 26mm, and the thickness of the third layer 4 is 5 nm.
And S5, preparing a P-type doped layer on the third layer 4 of the P surface 5 by adopting a CVD (chemical vapor deposition) deposition process, and preparing an N-type doped layer on the third layer 4 of the N surface 6.
And S6, preparing transparent conducting layers on the p-type doping layer and the n-type doping layer respectively by adopting PVD equipment.
And S7, screen printing is respectively carried out on the transparent conductive layer on the P surface 5 of the substrate and the transparent conductive layer on the N surface 6 of the substrate.
In this example, low rate CO deposition is used2The method of doping an amorphous silicon layer produces a heterojunction cell having a structure as shown in fig. 1, and for convenience, only a schematic cross-sectional view of a portion of the heterojunction cell is shown in fig. 1. The solar cell comprises a first layer 2, a second layer 3 and a third layer 4 of a crystalline silicon 1 and a P surface 5, and a second layer 3 and a third layer 4 of an N surface 6, wherein the first layer 2 is CO2The second layer 3 is an H-free doped intrinsic amorphous silicon layer, and the third layer 4 is an H-doped intrinsic amorphous silicon layer.
Example 2
The present embodiment provides a method for manufacturing a heterojunction cell, which is different from embodiment 1 mainly in that a CVD process is used to deposit CO2The amorphous silicon layer is doped by high-speed deposition, and the specific operation process flow comprises the following steps:
s1, selecting crystalline silicon 1 as a substrate, wherein in the embodiment of the application, the crystalline silicon 1 is an n-type silicon wafer, and the thickness of the n-type silicon wafer is 100 um.
S2, cleaning and texturing, wherein the cleaning and texturing process mainly comprises the steps of pre-cleaning the crystalline silicon 1, removing a damaged layer on the surface of the crystalline silicon, texturing, cleaning the silicon wafer, drying and blanking to obtain a pressure rod, and the texturing stage is a light trapping structure and is beneficial to light absorption.
S3, preparing a first layer 2 on the P surface 5 of the substrate by adopting a CVD deposition process, wherein the specific manufacturing process is as follows: the process temperature is 180 DEG CPreheating time 5min, power 1500W, SiH4Gas flow 200sccm, CO2The gas flow rate is 200sccm, the gas pressure is 50Pa, the inter-pole distance is 23mm, and the thickness of the first layer 2 is 3 nm.
S4, preparing a second layer 3 and a third layer 4 on the second layer 3 on a P-side 5 of the substrate obtained in the previous step by using a CVD deposition process, and preparing a second layer 3 and a third layer 4 on the second layer 3 on an N-side 6, wherein the second layer 3 and the second layer 3 are H-free doped intrinsic amorphous silicon layers, and the specific manufacturing process is as follows: the process temperature is 180 ℃, the preheating time is 5min, the power is 300W, and SiH4The gas flow is 600sccm, the gas pressure is 50Pa, the inter-polar distance is 23mm, and the thickness of the second layer 3 is 3 nm;
the third layer 4 and the third layer 4 are H-doped intrinsic amorphous silicon layers, and the specific manufacturing process comprises the following steps: the process temperature is 180 ℃, the preheating time is 5min, the power is 300W, and SiH4Gas flow 1000sccm, H2The gas flow is 1000sccm, the gas pressure is 50Pa, the inter-polar distance is 23mm, and the thickness of the third layer 4 is 4 nm.
And S5, preparing a P-type doped layer on the third layer 4 of the P surface 5 by adopting a CVD (chemical vapor deposition) deposition process, and preparing an N-type doped layer on the third layer 4 of the N surface 6.
And S6, preparing transparent conducting layers on the p-type doping layer and the n-type doping layer respectively by adopting PVD equipment.
And S7, screen printing is respectively carried out on the transparent conductive layer on the P surface 5 of the substrate and the transparent conductive layer on the N surface 6 of the substrate.
In this example, high rate CO deposition is used2The method of doping the amorphous silicon layer produced a heterojunction cell having the same structure as the heterojunction cell produced by the method of example 1, as shown in fig. 1.
In both example 1 and example 2, the first layer 2 is deposited on the P-side of the substrate to produce a heterojunction cell, but it should be understood that this is merely an example provided for the purpose of explaining the present application and is not to be construed as limiting the present application, and other forms of depositing the first layer 2 are within the scope of the present application.
For example, in this documentIn one embodiment of the application, the first layer 2 is deposited by a CVD process on the N-side 6 of the substrate only and is located between the substrate and the double intrinsic amorphous silicon layer, as shown in fig. 2, wherein the first layer 2 is CO deposited by a CVD process2And doping the amorphous silicon layer.
In another embodiment of the present application, the first layer 2 is deposited on the P-side 5 and the N-side 6 of the substrate by a CVD process, and the first layer 2 is located between the P-side 5 of the substrate and the double-layer intrinsic amorphous silicon layer and between the N-side 6 of the substrate and the double-layer intrinsic amorphous silicon layer, respectively, as shown in fig. 3, wherein the first layer 2 is CO deposited by a CVD process2And doping the amorphous silicon layer.
It can therefore be understood that the first layer 2 is produced on at least one of the P-side 5 and N-side 6 of the substrate by a CVD deposition process, said first layer 2 being CO2Doping an amorphous silicon layer, and preparing a second layer 3 and a third layer 4 on the second layer 3 on the P surface 5 and the N surface 6 of the substrate by adopting a CVD (chemical vapor deposition) deposition process, wherein the first layer 2, the second layer 3 and the third layer 4 form an intrinsic amorphous silicon layer with a three-layer structure, and the second layer 3 and the third layer 4 form an intrinsic amorphous silicon layer with a two-layer structure.
Comparative example
The present example provides a method for preparing a heterojunction battery, which is different from examples 1 and 2 mainly in that the heterojunction battery prepared in the present example does not include CO2Doping the amorphous silicon layer for the purpose of containing CO2The heterojunction cell doped with the amorphous silicon layer is used for performance comparison, and the specific operation process flow comprises the following steps:
s1, selecting crystalline silicon 1 as a substrate, wherein in the embodiment of the application, the crystalline silicon 1 is an n-type silicon wafer, and the thickness of the n-type silicon wafer is 160 um.
S2, cleaning and texturing, wherein the cleaning and texturing process mainly comprises the steps of pre-cleaning the crystalline silicon 1, removing a damaged layer on the surface of the crystalline silicon, texturing, cleaning the silicon wafer, drying and blanking to obtain a pressure rod, and the texturing stage is a light trapping structure and is beneficial to light absorption.
S3, preparing the second layer 3 on the P surface 5 and the N surface 6 of the substrate by adopting the CVD deposition processA third layer 4 on the second layer 3, wherein the second layer 3 is an intrinsic amorphous silicon layer without H doping, and the specific manufacturing process is as follows: the process temperature is 220 ℃, the preheating time is 15min, the power is 600W, and SiH4The gas flow is 1500sccm, the gas pressure is 100Pa, the inter-polar distance is 30mm, and the thickness of the second layer 3 is 5 nm;
the third layer 4 is an H-doped intrinsic amorphous silicon layer, and the specific manufacturing process is as follows: the process temperature is 220 ℃, the preheating time is 15min, the power is 600W, and SiH4Gas flow rate 5000sccm, H2The gas flow is 5000sccm, the gas pressure is 100Pa, the inter-polar distance is 30mm, and the thickness of the third layer 4 is 6 nm.
And S4, preparing a P-type doped layer on the third layer 4 of the P surface 5 by adopting a CVD (chemical vapor deposition) deposition process, and preparing an N-type doped layer on the third layer 4 of the N surface 6.
And S5, preparing transparent conducting layers on the p-type doping layer and the n-type doping layer respectively by adopting PVD equipment.
And S6, screen printing is respectively carried out on the transparent conductive layer on the P surface 5 of the substrate and the transparent conductive layer on the N surface 6 of the substrate.
The method of making the heterojunction cell in this example does not include CO2The fabrication of the doped amorphous silicon layer, i.e. without the first layer 2, produces a heterojunction cell structure as shown in figure 4. For convenience, a schematic cross-sectional view of only a portion of the heterojunction cell is shown in fig. 4.
Preferably, the adopted CVD Deposition process is a PECVD Deposition process (Plasma Enhanced Chemical Vapor Deposition), and the PECVD Deposition process has the advantages of low basic temperature, fast Deposition rate, good film forming quality, fewer pinholes and difficult cracking.
Example 3
In the examples of the present application, the photovoltaic performance of the heterojunction cells fabricated by the methods of manufacturing the heterojunction cells described in examples 1 and 2 and the comparative example was tested, and the results are shown in fig. 5, where CO is deposited at a low rate in example 12Doped amorphous silicon layer, corresponding to the experimental group "low speed i 0" in the figure, example 2 used high rate depositionCO2Doped amorphous silicon layer corresponding to the experimental group "high speed i 0" in the figure, no CO in the comparative example2The amorphous silicon layer was doped, corresponding to the experimental group "without i 0" in the figure. From the efficiency map, the efficiency of the experiment group of the low speed i0 is the highest and is about 22.9 percent, the efficiency of the experiment group of the high speed i0 is about 22.8 percent, which is lower than that of the experiment group of the low speed i0, and the efficiency of the experiment group of the non-i 0 is about 22.6 percent; from the current diagram, the current of the experimental group of "low speed i 0" is the highest and about 9.35A, the current of the experimental group of "high speed i 0" is about 9.3A, and the current of the experimental group without i0 "is about 9.32A; from the voltage diagram, it can be found that the voltage of the experimental group "low speed i 0" is the highest and about 0.739V, the voltage of the experimental group "high speed i 0" is about 0.736V, and the voltage of the experimental group "no i 0" is about 0.731V.
By comparison of the experimental results it is shown that the low rate deposited first layer 2 performs better than the heterojunction cell of the high rate deposited first layer 2, because the quality of the high rate deposited film layer is not as good as the low rate deposited film layer; and the heterojunction cell performance of the first layer 2 deposited at a low rate is significantly better than that of the CO-free2Heterojunction cell performance of doped amorphous silicon layer. The test result shows that the intrinsic amorphous silicon layer structure with 3 layers, namely the intrinsic amorphous silicon layer consisting of the first layer, the second layer and the third layer can improve the current of about 30mA, improve the open-circuit voltage of about 10mv and bring about 0.1 percent of absolute efficiency improvement.
According to the embodiment provided by the application, aiming at the problems that the intrinsic amorphous silicon layer is not ideal in passivation effect and difficult in thickness optimization, the heterojunction cell preparation method is invented, and a layer of CO is added between crystalline silicon and a traditional double-layer intrinsic amorphous silicon layer structure2The doped amorphous silicon layer forms an intrinsic amorphous silicon layer with a three-layer structure, so that the interface passivation quality is improved, the photo-generated current and the open-circuit voltage are both increased under the condition that the traditional intrinsic amorphous silicon layer is not required to be greatly changed and other equipment is not required to be added, and the photoelectric conversion efficiency of the cell is improved.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A method of fabricating a heterojunction battery, the method comprising:
providing a crystalline silicon substrate, wherein one side of the substrate is a P surface, and the other side of the substrate is an N surface;
cleaning and texturing the substrate;
preparing a first layer on at least one of the P-side and N-side of the substrate, the first layer being CO2Doping the amorphous silicon layer;
and respectively preparing a second layer and a third layer on the second layer on the P surface and the N surface of the substrate after the first layer is prepared, wherein the second layer is an H-free doped intrinsic amorphous silicon layer, and the third layer is an H-doped intrinsic amorphous silicon layer.
2. A method of fabricating a heterojunction cell according to claim 1, wherein the thickness of the first layer is in the range of 0.5-3nm, the thickness of the second layer is in the range of 3-5nm, and the thickness of the third layer is in the range of 4-6 nm.
3. The method of claim 1, wherein the first layer is formed by a process comprising: the process temperature range is 180-4The gas flow range is 200-2The gas flow range is 200-400sccm, the gas pressure range is 50-100Pa, and the electrode spacing range is 23-30 mm.
4. The method of claim 1, wherein the first layer is formed by a process comprising: the process temperature range is 180-4The gas flow range is 200-400sccm，CO2The gas flow range is 200-400sccm, the gas pressure range is 50-100Pa, and the electrode spacing range is 23-30 mm.
5. The method of claim 1, wherein the second layer is formed by a process comprising: the process temperature range is 180-4The gas flow range is 600-1500sccm, the gas pressure range is 50-100Pa, and the electrode spacing range is 23-30 mm.
6. The method of claim 1, wherein the third layer is formed by a process comprising: the process temperature range is 180-4The gas flow range is 1000-2The gas flow range is 1000-5000sccm, the gas pressure range is 50-100Pa, and the electrode spacing range is 23-30 mm.
7. The method of manufacturing a heterojunction cell according to claim 1, wherein after the step of manufacturing a second layer and a third layer on the second layer on both P-side and N-side of the substrate after the first layer is manufactured, further comprising the step of:
preparing a P-type doped layer on the third layer of the P surface of the substrate, and preparing an N-type doped layer on the third layer of the N surface of the substrate;
respectively preparing transparent conducting layers on the p-type doping layer and the n-type doping layer;
and respectively carrying out screen printing on the P-surface transparent conductive layer of the substrate and the N-surface transparent conductive layer of the substrate.
8. The method as claimed in any one of claims 1 to 7, wherein the crystalline silicon is an n-type silicon wafer, and the thickness of the n-type silicon wafer is in the range of 100-160 μm.
9. A method of fabricating a heterojunction cell according to any of claims 1 to 7 wherein the first, second and third layers are fabricated using a PECVD deposition process and the transparent conductive layer is fabricated using a PVD deposition process.
10. The heterojunction cell is characterized by comprising a crystalline silicon substrate and intrinsic amorphous silicon layers with double-layer structures positioned on two sides of the crystalline silicon substrate, wherein a layer of CO is arranged between the crystalline silicon substrate on at least one side and the intrinsic amorphous silicon layers with double-layer structures2The doped amorphous silicon layer forms an intrinsic amorphous silicon layer with a three-layer structure, and the heterojunction cell further comprises a p-type doped layer, an n-type doped layer and a transparent conducting layer which are positioned on the intrinsic amorphous silicon layer.
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