CN113363207A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN113363207A
CN113363207A CN202010153286.2A CN202010153286A CN113363207A CN 113363207 A CN113363207 A CN 113363207A CN 202010153286 A CN202010153286 A CN 202010153286A CN 113363207 A CN113363207 A CN 113363207A
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China
Prior art keywords
initial
side wall
sidewall
top surface
forming
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CN202010153286.2A
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Chinese (zh)
Inventor
杨鹏
张静
渠汇
刘佳磊
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202010153286.2A priority Critical patent/CN113363207A/en
Publication of CN113363207A publication Critical patent/CN113363207A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

Abstract

A forming method of a semiconductor structure comprises the following steps: providing a substrate, wherein the substrate comprises a first area; forming a first gate structure and an initial first sidewall structure on a top surface and a sidewall surface of the first gate structure over the first region, the initial first sidewall structure comprising: the method comprises the steps that a first side wall and a second side wall are initialized, and the material of the first side wall is different from that of the second side wall; forming a dielectric layer covering the surface of the side wall of the initial first side wall structure on the substrate, wherein the top surface of the dielectric layer is lower than that of the initial first side wall structure; removing the initial second side wall higher than the top surface of the dielectric layer by adopting a first etching process, exposing the top surface and the side wall surface of the initial first side wall, and enabling the initial second side wall to form a second side wall; and removing the initial first side wall higher than the top surface of the dielectric layer by adopting a second etching process to form the first side wall by the initial first side wall. The method is beneficial to improving the performance of the formed semiconductor structure.

Description

Method for forming semiconductor structure
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a forming method of a semiconductor structure.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. A fin field effect transistor is a common multi-gate device, and the structure of the fin field effect transistor includes: the barrier layer covers a part of the side wall of the fin part, and the surface of the barrier layer is lower than the top of the fin part; the grid electrode structure is positioned on the surface of the barrier layer, the top of the fin part and the surface of the side wall; and the source region and the drain region are positioned in the fin parts at two sides of the grid structure.
Since the dielectric layer process has a decisive role in the height of the gate structure, and the height of the gate structure has a great influence on the performance and yield of the semiconductor device, the dielectric layer process influences the performance of the semiconductor device.
However, the sidewall formed by the existing dielectric layer process has poor morphology and defects, which results in poor performance of the formed semiconductor.
Disclosure of Invention
The invention provides a method for forming a semiconductor structure, which aims to improve the performance of the formed semiconductor structure.
In order to solve the above technical problem, the present invention further provides a method for forming a semiconductor structure, including: providing a substrate comprising a first region; forming a first gate structure and an initial first sidewall structure on a top surface and a sidewall surface of the first gate structure over the first region, the initial first sidewall structure comprising: the gate structure comprises an initial first side wall and an initial second side wall, wherein the initial first side wall is positioned on the top surface and the surface of the side wall of the first gate structure, the initial second side wall is positioned on the surface of the initial first side wall, and the material of the initial first side wall is different from that of the initial second side wall; forming a dielectric layer on the substrate to cover the surface of the side wall of the initial first side wall structure, wherein the top surface of the dielectric layer is lower than that of the initial first side wall structure; removing the initial second side wall higher than the top surface of the dielectric layer by adopting a first etching process, exposing the top surface and the side wall surface of the initial first side wall, and enabling the initial second side wall to form a second side wall; and removing the initial first side wall higher than the top surface of the dielectric layer by adopting a second etching process to form the first side wall by the initial first side wall.
Optionally, the top surface of the first gate structure has a mask structure and an interface layer on the top surface of the mask structure, and the initial first sidewall structure is located on the sidewall surfaces of the first gate structure, the mask structure and the interface layer and on the top surface of the interface layer.
Optionally, the substrate further comprises: a second region adjacent to the first region; the method for forming the semiconductor structure further comprises the following steps: forming a second gate structure and an initial second sidewall structure on a top surface and a sidewall surface of the second gate structure on the second region; the dielectric layer is also positioned on the second area substrate, covers the surface of the side wall of the initial second side wall structure, and is lower than the surface of the top of the initial second side wall structure.
Optionally, the mask structure is further located on a top surface of the second gate structure; the initial second sidewall structure is located on the sidewall surfaces of the second gate structure and the mask structure, and on the top surface of the mask structure.
Optionally, the initial second sidewall structure includes: the gate structure comprises an initial third side wall positioned on the surface of the side wall of the second gate structure and an initial fourth side wall positioned on the surface of the side wall of the initial third side wall and the surface of the top of the second gate structure, wherein the material of the initial third side wall is different from that of the initial fourth side wall.
Optionally, the first etching process further removes the initial fourth sidewall higher than the top surface of the dielectric layer, and exposes the top surface and the sidewall surface of the initial third sidewall, so that the initial fourth sidewall forms a fourth sidewall; and the second etching process also removes the initial third side wall higher than the top surface of the dielectric layer, so that the initial third side wall forms a third side wall.
Optionally, the first etching process is an isotropic wet process; and the etching rates of the first etching process to the initial second side wall and the initial fourth side wall are greater than the etching rates to the initial first side wall and the initial third side wall.
Optionally, the initial second side wall is made of an insulating material; and the material of the initial fourth side wall is an insulating material.
Optionally, the insulating material includes: silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.
Optionally, the wet etching parameters include: the etching process is a diluted phosphoric acid solution, and the volume ratio of the phosphoric acid solution to water is 2: 5-4: 5.
Optionally, the second etching process is an isotropic wet process; and the etching rate of the second etching process to the initial first side wall and the initial third side wall is greater than the etching rate to the dielectric layer.
Optionally, the initial first side wall is made of a low-K dielectric material; the material of the initial third side wall is a low-K dielectric material.
Optionally, the low-K dielectric material contains silicon, oxygen, carbon and nitrogen elements.
Optionally, the parameters of the second etching process include: the adopted etching solution comprises an ozone water solution and a hydrofluoric acid solution, wherein the volume ratio of the ozone water solution to the hydrofluoric acid solution is 55: 45-75: 25.
optionally, the number of the second areas is several, and the first area is located between adjacent second areas.
Optionally, the top surface of the dielectric layer is lower than the bottom surface of the interface layer.
Optionally, the distance between the top surface of the dielectric layer and the top surface of the initial first sidewall structure ranges from 40 nm to 80 nm.
Optionally, the forming method of the dielectric layer includes: forming a film of an initial dielectric material on the substrate; flattening the initial dielectric material film to form a dielectric material film, wherein the dielectric material film is higher than or flush with the top surface of the initial first side wall structure; and etching back the dielectric material film to enable the top surface of the dielectric material film to be lower than the bottom of the interface layer, and forming the dielectric layer.
Optionally, the method further includes: and after the first side wall, the second side wall, the third side wall and the fourth side wall are formed, removing the mask structures on the top surfaces of the first gate structure and the second gate structure and the interface layer on the first region.
Optionally, the substrate comprises: the first grid structure crosses the fin part, and the first grid structure is located on part of the top surface and the surface of the side wall of the fin part.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
in the forming method of the semiconductor structure provided by the technical scheme of the invention, the initial second side wall higher than the top surface of the dielectric layer is removed by adopting a first etching process, so that the top surface of the formed second side wall is flush with the top surface of the dielectric layer, and the formed second side wall is ensured to have good appearance; and removing the initial first side wall higher than the top surface of the dielectric layer by adopting a second etching process, so that the top surface of the formed first side wall is flush with the top surface of the dielectric layer, and the formed first side wall is ensured to have a better appearance. In conclusion, the top surface of the first side wall structure formed by the first side wall and the second side wall is flush with the top surface of the dielectric layer, so that the formed first side wall structure has a better appearance, and the performance of the formed semiconductor structure is improved.
Further, the first etching process is an isotropic wet etching process. The wet etching process is isotropic, and is beneficial to completely removing the initial second side wall and the initial fourth side wall which are higher than the surface of the dielectric layer, so that the first gate structure is prevented from being left with the material of the initial second side wall, and the top surfaces of the formed second side wall and the fourth side wall are flush with the top surface of the dielectric layer. And the second side wall forms a first side wall structure, and the fourth side wall forms a second side wall structure, so that the first side wall structure of the first area and the second side wall structure of the second area can keep better consistency in appearance, and the stability of the performance of the formed semiconductor is improved.
Further, the second etching process is an isotropic wet etching process. The wet etching process is isotropic, and is beneficial to thoroughly removing the initial first side wall and the initial third side wall which are higher than the surface of the dielectric layer, so that the first gate structure is prevented from being left with the initial first side wall material, and the top surfaces of the formed first side wall and the formed third side wall are flush with the top surface of the dielectric layer. And the first side wall forms a first side wall structure, and the third side wall forms a second side wall structure, so that the first side wall structure of the first area and the second side wall structure of the second area can keep better consistency in appearance, and the stability of the performance of the formed semiconductor is improved.
Furthermore, the etching rate of the second etching process to the initial first side wall and the initial third side wall is greater than the etching rate to the dielectric layer, so that the etching loss to the surface of the dielectric layer is reduced while the first side wall formed on the first region and the third side wall formed on the second region are ensured to have better consistency, thereby ensuring that the height of the dielectric layer is less influenced, being beneficial to the control of the subsequent process, and being beneficial to improving the stability of the performance of the formed semiconductor.
Drawings
FIGS. 1-4 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure;
fig. 5 to 10 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
As described in the background, the performance of existing semiconductor structures is poor.
The reason for the poor performance of the semiconductor structure will be described in detail below with reference to the accompanying drawings, and fig. 1 to 4 are schematic structural diagrams of steps of a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 100 is provided, where the substrate 100 includes a first region I and a second region II, the first region I and the second region II have a fin 110 thereon, the first region I has a first gate structure 121 crossing the fin 110 thereon, the second region II has a second gate structure 122 crossing the fin 110 thereon, and the first gate structure 121 has an interface layer 125 thereon.
Referring to fig. 2, an initial first sidewall structure is formed on the surface of the first gate structure 121, and the initial first sidewall structure covers the interface layer 125, and the initial first sidewall structure includes: an initial first sidewall 131 on the top surface and the sidewall surface of the first gate structure 121, and an initial second sidewall 132 on the top surface and the sidewall surface of the initial first sidewall 131, where an initial second sidewall structure is formed on the surface of the second gate structure 122, and the initial second sidewall structure includes: an initial third sidewall 141 on the sidewall surface of the second gate structure 122, and an initial fourth sidewall 142 on the sidewall surface of the initial third sidewall and the top surface of the second gate structure 122, wherein the top surface of the initial first sidewall is higher than the top surface of the initial second sidewall.
Referring to fig. 3, a dielectric layer 150 is formed on the substrate 100 to cover the sidewall surfaces of the initial first sidewall structure 130 and the initial second sidewall structure 140, and the top surface of the dielectric layer 150 is lower than the bottom of the junction layer 125.
Referring to fig. 4, the initial first sidewall 131, the initial second sidewall 132, the initial third sidewall 141 and the initial fourth sidewall 142 that are higher than the top surface of the dielectric layer 150 are etched, so that the first sidewall 151 is formed by the initial first sidewall 131, the second sidewall 152 is formed by the initial second sidewall 132, the third sidewall 153 is formed by the initial third sidewall 141, and the fourth sidewall 154 is formed by the initial fourth sidewall 142.
In the above method, the first sidewall 151 and the second sidewall 152 are formed by etching the initial first sidewall 131 and the initial second sidewall 132, and the first sidewall 151 and the second sidewall 152 affect the height of the gate structure formed on the first region I by the gate-last process. Similarly, the third sidewall 153 and the fourth sidewall 154 influence the height of a gate structure formed on the second region II by a gate-last process.
The second region II is used for forming different types of devices, including: the first region I is an interface region between the adjacent N-type device and the adjacent P-type device. When an N-type device or a P-type device is formed on the second region II, the first region I is not exposed, so that the film layer on the first region I is not easily removed by etching, and the top surface of the first gate structure 121 on the first region I has the interface layer 125, and meanwhile, the top surface of the interface layer 125 also has the initial first sidewall 131, so that the top surface of the initial first sidewall structure on the first region I is higher than the top surface of the initial second sidewall structure on the second region II. Furthermore, in the subsequent etching process of the initial first sidewall 131, the initial second sidewall 132, the initial third sidewall 141, and the initial fourth sidewall 142, the initial first sidewall 131 and the initial second sidewall 132, which are higher than the top surface of the dielectric layer 150, in the first region I are not easily removed completely, so that the heights of the first sidewall 151 and the second sidewall 152 formed on the first region I are higher than the top surface of the dielectric layer 150. Meanwhile, the third side wall 153 and the fourth side wall 154 on the second region II can be better removed in the etching process, so as to be flush with the top surface of the dielectric layer 150, and therefore, the height of the first side wall structure on the first region I is higher than that of the second side wall structure on the second region II, which affects the subsequent process, so that the performance of the formed semiconductor structure is poor.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: removing the initial second side wall higher than the top surface of the dielectric layer by adopting a first etching process, exposing the top surface and the side wall surface of the initial first side wall, and enabling the initial second side wall to form a second side wall; and removing the initial first side wall higher than the top surface of the dielectric layer by adopting a second etching process to form the first side wall by the initial first side wall. And forming a first side wall through the first etching process, wherein the top surface of the first side wall is flush with the top surface of the dielectric layer, the second etching process forms a second side wall, and the top surface of the second side wall is flush with the top surface of the dielectric layer, so that the top surface of a first side wall structure formed by the first side wall and the second side wall is flush with the top surface of the dielectric layer, the formed first side wall structure has better appearance, and the improvement of the performance of the formed semiconductor structure is facilitated.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 5 to 10 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 5, a substrate is provided, the substrate including a first region I.
In this embodiment, the substrate further includes: a second zone II adjacent to the first zone I.
In this embodiment, the substrate includes: a substrate 201 and a fin 202 on a surface of the substrate 201. In other embodiments, the base may also be a planar substrate.
In this embodiment, the second region II is used to form an N-type device and a P-type device, and the first region I is a boundary between the N-type device and the P-type device.
In another embodiment, the number of the second regions is several, the first regions are located between adjacent second regions, and the second regions located at two sides of the first regions are respectively used for forming different types of devices.
The substrate is made of silicon; in other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide; in other embodiments, the base may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
In this embodiment, the method for forming the substrate includes: providing an initial substrate; and patterning the initial substrate to form the substrate 201 and the fin part 202 on the surface of the substrate 201.
Referring to fig. 6, a first gate structure 220 and an initial first sidewall structure (not labeled) on the top surface and sidewall surface of the first gate structure 220 are formed on the first region I, and the initial first sidewall structure includes: an initial first sidewall 251 located on a top surface and a sidewall surface of the first gate structure 220, and an initial second sidewall 252 located on a surface of the initial first sidewall 251, where a material of the initial first sidewall 251 is different from a material of the initial second sidewall 252.
In this embodiment, the method for forming a semiconductor structure further includes: forming a second gate structure 240 on the second region II, and an initial second sidewall structure (not labeled) on a top surface and a sidewall surface of the second gate structure 240, the initial second sidewall structure including: an initial third sidewall 261 located on a sidewall surface of the second gate structure 240, and an initial fourth sidewall 262 located on a sidewall surface of the initial third sidewall 261 and a top surface of the second gate structure 240, wherein a material of the initial third sidewall 261 is different from a material of the initial fourth sidewall 262.
The first gate structure 220 and the second gate structure 240 are formed in the same process.
The method for forming the first gate structure 220 and the second gate structure 240 includes: forming a gate dielectric material film (not shown) on the substrate 201, wherein the gate dielectric material film covers the top surface and the side wall surface of the fin 202; forming a gate electrode material film on the surface of the gate dielectric material film; forming a patterned layer on the surface of the gate electrode material film, the patterned layer covering a part of the surface of the gate electrode material film on the first region I and the second region II; and etching the gate electrode material film and the gate dielectric material film by taking the patterning layer as a mask until the top surface of the fin 202 and the surface of the substrate 201 are exposed, forming the first gate structure 220 on the first region I, and forming the second gate structure 240 on the second region II.
In this embodiment, the first gate structure 220 further has a mask structure (not shown).
In this embodiment, the mask structure is also located on the top surface of the second gate structure 240.
The mask structure includes: a first mask layer 221 and a second mask layer 222 on the surface of the first mask layer.
The first mask layer 221 protects the surface of the gate electrode material film, reduces etching damage to the surface of the gate electrode material film, and improves the appearance of the formed first gate structure 220 and the second gate structure 240.
The second mask layer 222 is used for protecting the first mask layer 221 on one hand, so that the first mask layer 221 is not thinned; on the other hand, the second mask layer 222 has a large physical strength, which is beneficial to improving the accuracy of pattern transfer.
In this embodiment, the material of the first mask layer 221 is silicon oxide.
In this embodiment, the second mask layer 222 is made of silicon nitride.
Note that, an interface layer 225 is further provided on the first gate structure 220.
In this embodiment, the material of the interface layer 225 is silicon oxide.
When an N-type device or a P-type device is formed by etching, the interface layer 225 on the second region II is removed by etching, and meanwhile, the first region I is not easily exposed when the N-type device is formed and not easily exposed when the P-type device is formed, so that the interface layer 225 on the first region I is remained.
Specifically, in the present embodiment, the interface layer 225 is located on the surface of the second mask layer 222 on the first gate structure 220 in the first region I.
It should be noted that, in this embodiment, the interface layer 225 is also located on the surface of the mask structure on the second gate structure 240, and the interface layer 225 located on the second gate structure 240 is to be removed in the subsequent process of etching the sidewall material film, and the interface layer 225 located on the first gate structure 220 is remained.
After the first gate structure 220 is formed, the initial first sidewall 251 is formed on the sidewall surface and the top surface of the first gate structure 220.
In this embodiment, the method further includes: an initial third sidewall 261 is formed on the sidewall surface of the second gate structure 240.
In this embodiment, the initial first sidewall 251 and the initial third sidewall 261 are formed in the same process.
The initial first sidewall 251 and the initial third sidewall 261 are formed by a method including: forming a sidewall material film (not shown) on the sidewall surface and the top surface of the first gate structure 220 and the second gate structure 240; and etching back the side wall material film until the surface of the substrate 201 is exposed, forming the initial first side wall 251 on the first region I, and forming the initial third side wall 261 on the second region II.
The material of the initial first sidewall 251 is a low-K dielectric material.
The material of the initial third sidewall 261 is a low K dielectric material.
The low-K dielectric material contains silicon, oxygen, carbon and nitrogen elements.
The initial first sidewall 251 and the initial third sidewall 261 are formed by etching a film of sidewall material, and the initial first sidewall 251 and the initial third sidewall 261 are identical.
It should be noted that, in this embodiment, because of the limitation of the existing photolithography limit, the first region I is a boundary between the adjacent N-type region and the adjacent P-type region, and is not easily etched, so that in the process of etching back the sidewall material film, the sidewall material film on the first region I and the interface layer 225 covered by the sidewall material film are not easily etched and opened, and the interface layer 225 on the first region I cannot be removed, and the formed initial first sidewall 251 is not only located on the sidewall surfaces of the first gate structure 220 and the mask structure, but also located on the sidewall surface and the top surface of the interface layer 225. Meanwhile, the top surface of the sidewall material film on the second region II can be etched open, so that the interface layer 225 covered by the sidewall material film can be etched and removed, and the initial third sidewall 261 formed on the second region II is located on the sidewall surfaces of the second gate structure 240 and the mask structure, exposing the top surface of the mask structure.
After the initial first side walls 251 are formed, the initial second side walls 252 are formed on the top surfaces and the side wall surfaces of the initial first side walls 251.
In an embodiment, further comprising: the initial fourth side wall 262 is formed on the top surface and the sidewall surface of the initial third side wall 261.
The initial second side walls 252 are used for forming second side walls in the following, and the initial fourth side walls 262 are used for forming fourth side walls in the following.
The material of the initial second side wall 252 is different from that of the initial first side wall 251.
The material of the initial fourth side wall 262 is different from that of the initial third side wall 261.
The material of the initial second sidewall 252 is an insulating material, and the insulating material includes: silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.
The material of the initial fourth sidewall 262 is an insulating material, and the insulating material includes: silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.
In this embodiment, the initial second sidewall 252 and the initial fourth sidewall 262 are made of the same material and are made of silicon nitride.
In this embodiment, after the initial first sidewall 251 and the initial third sidewall 261 are formed, and before the initial second sidewall 252 and the initial fourth sidewall 262 are formed, the method for forming the semiconductor structure further includes: source and drain doped regions (not shown) are formed in the fin 202 at two sides of the first gate structure 220 and the second gate structure 240.
Next, a dielectric layer covering the sidewall surface of the initial first sidewall structure is formed on the substrate, and the top surface of the dielectric layer is lower than the top surface of the initial first sidewall structure, please refer to fig. 7 and 8 in the specific process of forming the dielectric layer.
Referring to fig. 7, a dielectric material film 270 is formed on the substrate, and the dielectric material film 270 covers the surface of the initial first sidewall structure.
In this embodiment, the dielectric material film 270 also covers the initial second sidewall structure surface.
The dielectric material film 270 provides a material for the subsequent formation of a dielectric layer.
The forming method of the dielectric material film comprises the following steps: forming a film of initial dielectric material (not shown) on the substrate; planarizing the initial dielectric material film to form a dielectric material film 270, wherein the dielectric material film 270 is higher than or flush with the top surface of the initial first sidewall structure.
The material of the initial dielectric material film comprises: silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.
In this embodiment, the material of the initial dielectric material film is silicon oxide.
The forming process of the initial dielectric material film comprises the following steps: a fluid chemical vapor deposition process. The fluid chemical vapor deposition process is beneficial to forming an initial medium material film with good filling property, and on the other hand, the formed quality and compactness are good, thereby being beneficial to improving the performance of a subsequently formed medium layer.
In other embodiments, the forming process of the initial dielectric material film comprises: a physical vapor deposition process or an atomic layer deposition process.
In this embodiment, the top surface of the dielectric material film 270 is higher than the top surface of the initial first sidewall 251 structure.
Referring to fig. 8, the dielectric material film 270 is etched back such that the top surface of the dielectric material film 270 is lower than the bottom of the interface layer 225, thereby forming the dielectric layer 271.
The dielectric layer 271 is formed by etching back the dielectric material film 270, and the material of the dielectric layer 271 includes: silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride. In this embodiment, the material of the dielectric layer 271 is silicon oxide.
Specifically, in this embodiment, the distance between the top surface of the dielectric layer 271 and the top surface of the initial first sidewall structure ranges from 40 nm to 80 nm.
The significance of selecting the range is: if the distance is greater than 80 nanometers, the height of the dielectric layer 271 is lower, and the dielectric layer 271 with the lower height affects the height of a gate structure formed by a subsequent gate-last process, so that the gate structure with the higher height is not ensured; since the interfacial layer 225 has a certain height, typically 40 nm, if the distance is less than 40 nm, it is not guaranteed that the top surface of the dielectric layer 271 is lower than the bottom surface of the interfacial layer 225.
Referring to fig. 9, after the dielectric layer 271 is formed, a first etching process is performed to remove the initial second sidewall 252 higher than the top surface of the dielectric layer 271 and expose the top surface and the sidewall surface of the initial first sidewall 251, so that the initial second sidewall 252 forms a second sidewall 282.
In this embodiment, the first etching process further removes the initial fourth sidewall 262 higher than the top surface of the dielectric layer 271, so that the initial fourth sidewall 262 forms a fourth sidewall 284.
The first etching process is an isotropic wet process; the etching rate of the first etching process to the initial second sidewall 252 and the initial fourth sidewall 262 is greater than the etching rate to the initial first sidewall 251 and the initial third sidewall 261.
In this embodiment, the initial second sidewall 252 and the initial fourth sidewall 262 are made of the same material, and are both made of silicon nitride, the initial first sidewall 251 and the initial third sidewall 261 are made of the same low-K dielectric material containing silicon, oxygen, carbon, and nitrogen, and the wet etching parameters include: the etching process is a diluted phosphoric acid solution, and the volume ratio of the phosphoric acid solution to water is 2: 5-4: 5.
The first etching process is an isotropic wet etching process. The wet etching process is isotropic, which is beneficial to completely removing the initial second sidewall 252 and the initial fourth sidewall 262 higher than the surface of the dielectric layer 271, thereby avoiding the material of the initial second sidewall 252 remaining on the portion higher than the dielectric layer 271, and making the top surfaces of the formed second sidewall 282 and fourth sidewall 284 flush with the top surface of the dielectric layer 271. Moreover, the second sidewall 282 subsequently forms a first sidewall structure, and the fourth sidewall subsequently forms a second sidewall structure, which is beneficial to maintaining better consistency of the first sidewall structure of the first area I and the second sidewall structure of the second area, thereby improving the stability of the performance of the formed semiconductor.
Referring to fig. 10, a second etching process is performed to remove the initial first sidewall 251 higher than the top surface of the dielectric layer 271, so that a first sidewall 281 is formed on the initial first sidewall 251.
In this embodiment, the second etching process further removes the initial third sidewall 261 higher than the top surface of the dielectric layer 271, so that the initial third sidewall 261 forms a third sidewall 283.
The second etching process is an isotropic wet process; the etching rate of the second etching process to the initial first sidewall 251 and the initial third sidewall 261 is greater than the etching rate to the dielectric layer 271.
In this embodiment, the initial first sidewall 251 and the initial third sidewall 261 are the same and are made of a low-K dielectric material containing silicon, oxygen, carbon, and nitrogen, the dielectric layer 271 is made of silicon oxide, and the parameters of the second etching process include: the adopted etching solution comprises an ozone water solution and a hydrofluoric acid solution, wherein the volume ratio of the ozone water solution to the hydrofluoric acid solution is 55: 45-75: 25.
the second etching process is an isotropic wet etching process. The wet etching process is isotropic, which is beneficial to completely removing the initial first sidewall 251 and the initial third sidewall 261 which are higher than the surface of the dielectric layer 271, so as to avoid the residue of the initial first sidewall material on the first gate structure 220, and to make the top surfaces of the formed first sidewall 281 and the third sidewall 283 flush with the top surface of the dielectric layer 271. In addition, the first side wall 281 forms a first side wall structure, and the third side wall 281 forms a second side wall structure, which is beneficial to maintaining better consistency of the morphology of the first side wall structure of the first area I and the second side wall structure on the second area, thereby improving the stability of the performance of the formed semiconductor.
Further, the etching rate of the second etching process to the initial first sidewall 251 and the initial third sidewall 261 is greater than that to the dielectric layer 271, so that the first sidewall 281 formed on the first region I and the third sidewall 283 formed on the second region II are guaranteed to have better consistency in morphology, and meanwhile, the etching loss to the surface of the dielectric layer 271 is reduced, so that the height of the dielectric layer 271 is guaranteed to be less affected, the control of the subsequent process is facilitated, and the stability of the performance of the formed semiconductor is improved.
In this embodiment, the method for forming a semiconductor structure further includes: after the first and second sidewalls 281, 282, the third sidewall 283 and the fourth sidewall 284 are formed by the first and second etching processes, the mask structures on the top surfaces of the first and second gate structures 220 and 240 and the interface layer 225 on the first region I are removed.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a substrate comprising a first region;
forming a first gate structure and an initial first sidewall structure on a top surface and a sidewall surface of the first gate structure over the first region, the initial first sidewall structure comprising: the gate structure comprises an initial first side wall and an initial second side wall, wherein the initial first side wall is positioned on the top surface and the surface of the side wall of the first gate structure, the initial second side wall is positioned on the surface of the initial first side wall, and the material of the initial first side wall is different from that of the initial second side wall;
forming a dielectric layer on the substrate to cover the surface of the side wall of the initial first side wall structure, wherein the top surface of the dielectric layer is lower than that of the initial first side wall structure;
removing the initial second side wall higher than the top surface of the dielectric layer by adopting a first etching process, exposing the top surface and the side wall surface of the initial first side wall, and enabling the initial second side wall to form a second side wall;
and removing the initial first side wall higher than the top surface of the dielectric layer by adopting a second etching process to form the first side wall by the initial first side wall.
2. The method of claim 1, wherein the first gate structure has a mask structure on a top surface thereof and an interface layer on the mask structure top surface, and wherein the initial first sidewall structure is on sidewall surfaces of the first gate structure, the mask structure and the interface layer and on a top surface of the interface layer.
3. The method of forming a semiconductor structure of claim 1, wherein the substrate further comprises: a second region adjacent to the first region; the method for forming the semiconductor structure further comprises the following steps: forming a second gate structure and an initial second sidewall structure on a top surface and a sidewall surface of the second gate structure on the second region; the dielectric layer is also positioned on the second area substrate, covers the surface of the side wall of the initial second side wall structure, and is lower than the surface of the top of the initial second side wall structure.
4. The method of forming a semiconductor structure of claim 3, wherein the mask structure is further located on a top surface of the second gate structure; the initial second sidewall structure is located on the sidewall surfaces of the second gate structure and the mask structure, and on the top surface of the mask structure.
5. The method of forming a semiconductor structure of claim 3, wherein the initial second sidewall structure comprises: the gate structure comprises an initial third side wall positioned on the surface of the side wall of the second gate structure and an initial fourth side wall positioned on the surface of the side wall of the initial third side wall and the surface of the top of the second gate structure, wherein the material of the initial third side wall is different from that of the initial fourth side wall.
6. The method for forming a semiconductor structure according to claim 5, wherein the first etching process further removes the initial fourth sidewall higher than the top surface of the dielectric layer to expose the top surface and the sidewall surface of the initial third sidewall, so that the initial fourth sidewall forms a fourth sidewall; and the second etching process also removes the initial third side wall higher than the top surface of the dielectric layer, so that the initial third side wall forms a third side wall.
7. The method of forming a semiconductor structure of claim 6, wherein the first etching process is an isotropic wet process; and the etching rates of the first etching process to the initial second side wall and the initial fourth side wall are greater than the etching rates to the initial first side wall and the initial third side wall.
8. The method for forming a semiconductor structure according to claim 7, wherein the material of the initial second sidewall spacers is an insulating material; and the material of the initial fourth side wall is an insulating material.
9. The method of forming a semiconductor structure of claim 8, wherein the insulating material comprises: silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride.
10. The method for forming a semiconductor structure of claim 9, wherein the wet etch parameters comprise: the etching process is a diluted phosphoric acid solution, and the volume ratio of the phosphoric acid solution to water is 2: 5-4: 5.
11. The method of forming a semiconductor structure of claim 6, wherein the second etching process is an isotropic wet process; and the etching rate of the second etching process to the initial first side wall and the initial third side wall is greater than the etching rate to the dielectric layer.
12. The method for forming a semiconductor structure according to claim 11, wherein the initial first sidewall spacer is made of a low-K dielectric material; the material of the initial third side wall is a low-K dielectric material.
13. The method of forming a semiconductor structure of claim 12 wherein said low K dielectric material comprises silicon, oxygen, carbon and nitrogen elements.
14. The method of forming a semiconductor structure of claim 13, wherein the parameters of the second etch process comprise: the adopted etching solution comprises an ozone water solution and a hydrofluoric acid solution, wherein the volume ratio of the ozone water solution to the hydrofluoric acid solution is 55: 45-75: 25.
15. the method of claim 3, wherein the number of the second regions is several, and the first region is located between adjacent second regions.
16. The method of forming a semiconductor structure of claim 1, wherein a top surface of the dielectric layer is lower than a bottom surface of the interfacial layer.
17. The method of forming a semiconductor structure of claim 16, wherein a top surface of the dielectric layer is spaced apart from a top surface of the initial first sidewall structure by a distance in a range from 40 nm to 80 nm.
18. The method of forming a semiconductor structure of claim 16, wherein the method of forming the dielectric layer comprises: forming a film of an initial dielectric material on the substrate; flattening the initial dielectric material film to form a dielectric material film, wherein the dielectric material film is higher than or flush with the top surface of the initial first side wall structure; and etching back the dielectric material film to enable the top surface of the dielectric material film to be lower than the bottom of the interface layer, and forming the dielectric layer.
19. The method of forming a semiconductor structure of claim 6, further comprising: and after the first side wall, the second side wall, the third side wall and the fourth side wall are formed, removing the mask structures on the top surfaces of the first gate structure and the second gate structure and the interface layer on the first region.
20. The method of forming a semiconductor structure of claim 1, wherein the substrate comprises: the first grid structure crosses the fin part, and the first grid structure is located on part of the top surface and the surface of the side wall of the fin part.
CN202010153286.2A 2020-03-06 2020-03-06 Method for forming semiconductor structure Pending CN113363207A (en)

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