CN113362770B

CN113362770B - Display panel and display device

Info

Publication number: CN113362770B
Application number: CN202110612324.0A
Authority: CN
Inventors: 冯雪欢; 李永谦
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Priority date: 2021-06-02
Filing date: 2021-06-02
Publication date: 2022-10-28
Anticipated expiration: 2041-06-02
Also published as: CN113362770A

Abstract

The present disclosure provides a display panel and a display device. The display panel includes: a substrate base plate; a plurality of pixel units disposed on the substrate, each pixel unit including a sub-pixel including a light emitting element and a pixel driving circuit coupled to the light emitting element; the grid driving circuit comprises a plurality of cascaded shift registers and a plurality of grid lines, one shift register is coupled with the plurality of pixel driving circuits in one row of pixel units through the grid lines, and the shift registers are used for providing grid driving signals for the plurality of pixel driving circuits through the grid lines; the grid line comprises a first conductive part positioned between adjacent sub-pixels, the first conductive part comprises a first conductive sub-layer and a second conductive sub-layer, the first conductive sub-layer and the second conductive sub-layer are positioned on different layers, an insulating layer is arranged between the first conductive sub-layer and the second conductive sub-layer, and the first conductive sub-layer and the second conductive sub-layer are coupled through an insulating layer through hole.

Description

Display panel and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

The Organic Light Emitting Diode (OLED) Display technology is widely used, and becomes the most potential Display technology to replace Liquid Crystal Display (LCD). Compared with the LCD display technology, the OLED display technology has better experience in terms of image quality, response speed, light weight, and the like.

In the display field, especially in large-size OLED display, the gate driving circuit is usually disposed on both sides of the panel, which makes it difficult to achieve ultra-narrow frame or even frameless frame. With the trend of narrow-frame and even no-frame display devices, various types of display panels, such as full-screen and water-drop screen, appear.

Disclosure of Invention

In view of the above, embodiments of the present disclosure provide a display panel and a display device, which are used to meet the trend of narrow frame and even no frame of the display device.

In one aspect, an embodiment of the present disclosure provides a display panel, including: a substrate base plate; a plurality of pixel units disposed on the base substrate, the plurality of pixel units being arranged in an array in a row direction and a column direction on a display area of the base substrate, each pixel unit including at least one sub-pixel including a light emitting element and a pixel driving circuit coupled to the light emitting element; the grid driving circuit comprises a plurality of cascaded shift registers and a plurality of grid lines, one shift register is coupled with the plurality of pixel driving circuits in at least one row of pixel units through at least one grid line, and the shift register is used for providing grid driving signals for the plurality of pixel driving circuits through at least one grid line; the shift register comprises a plurality of first thin film transistors, the first thin film transistors are divided into a plurality of first thin film transistor groups, at least one first thin film transistor group is located in the display area and distributed among at least part of adjacent sub-pixels in the same row of sub-pixels, at least one grid line comprises a first conductive part located between the adjacent sub-pixels, the first conductive part comprises a first conductive sub-layer and a second conductive sub-layer, the first conductive sub-layer and the second conductive sub-layer are located on different layers, an insulating layer is arranged between the first conductive sub-layer and the second conductive sub-layer, and the first conductive sub-layer and the second conductive sub-layer are coupled through an insulating layer through hole.

In some embodiments, the display panel further comprises: and the power supply line is positioned on the substrate and is positioned between the adjacent sub-pixels and used for providing power supply signals for the sub-pixels.

In some embodiments, the plurality of gate lines extend in a first direction, the power line extends in a second direction, the first direction and the second direction are different, and the power line includes a second conductive portion, an orthographic projection of the second conductive portion on the substrate at least partially overlapping an orthographic projection of at least one of the plurality of gate lines on the substrate.

In some embodiments, an orthographic projection of the second conductive portion on the substrate base plate at least partially overlaps with an orthographic projection of the second conductive sub-layer on the substrate base plate, and the orthographic projection of the second conductive portion on the substrate base plate is isolated from the orthographic projection of the first conductive sub-layer on the substrate base plate.

In some embodiments, the power line further includes a third conductive portion, the third conductive portion and the second conductive portion being located at different layers.

In some embodiments, an orthographic projection of the third conductive part on the substrate base plate is isolated from an orthographic projection of the first conductive sub-layer on the substrate base plate, and an orthographic projection of the third conductive part on the substrate base plate is isolated from an orthographic projection of the second conductive sub-layer on the substrate base plate.

In some embodiments, the pixel driving circuit includes a thin film transistor; and the thin film transistor comprises a source electrode and a drain electrode, and the second conductive sublayer and the source electrode and the drain electrode are positioned in the same layer.

In some embodiments, the power line includes a second conductive portion and a third conductive portion; the thin film transistor includes a gate electrode; the display panel further includes: a light shielding pattern disposed on the substrate in a region corresponding to an active layer of a thin film transistor of the pixel driving circuit; the insulating layer includes: the buffer layer is arranged on one side of the shading pattern far away from the substrate base plate; and the interlayer dielectric layer is arranged on one side of the buffer layer far away from the substrate base plate.

In some embodiments, the second conductive portion is located on a layer where the shading pattern is located, and the second conductive portion is electrically connected to the third conductive portion through a first via hole and a second via hole, wherein the first via hole is disposed on the buffer layer, and the second via hole is disposed on the interlayer dielectric layer.

In some embodiments, an orthographic projection of the first via on the substrate base overlaps an orthographic projection of the second via on the substrate base.

In some embodiments, the second conductive sublayer is electrically connected to the first conductive sublayer through a third via disposed on the interlayer dielectric layer.

In some embodiments, the sub-pixel comprises a light emitting element comprising an anode; and the anode is coupled with the drain electrode of the thin film transistor of the pixel driving circuit.

In some embodiments, orthographic projections of the first and second conductive sublayers on the substrate base plate overlap each other and extend in the same direction.

In certain embodiments, the second conductive sublayer is disposed in at least one of: a layer where the light-shielding pattern is located, a layer where the source and drain electrodes are located, or a layer where the cathode electrode is located.

In some embodiments, the display panel further comprises: a light shielding pattern disposed on the substrate in a region corresponding to an active layer of a thin film transistor of the pixel driving circuit; and a storage capacitor electrode disposed on a side of the light shielding pattern away from the substrate; wherein, the orthographic projection of the shading pattern on the substrate base plate is at least partially overlapped with the orthographic projection of the storage capacitor electrode on the substrate base plate.

In some embodiments, light emitted by the light emitting element exits through the base substrate; the orthographic projection of the part of the gate drive circuit, which is positioned in the display area, on the substrate does not overlap with the orthographic projection of the light-emitting element and the pixel drive circuit on the substrate.

In some embodiments, in the sub-pixels of two adjacent rows, the light emitting elements located in different rows are adjacent, or the pixel driving circuits located in different rows are adjacent.

In some embodiments, the display panel further comprises: a data signal line coupled to the pixel driving circuit and configured to provide a data signal to the pixel driving circuit; the plurality of first thin film transistor groups at least comprise a first thin film transistor group which is used as an output transistor in the shift register; and a first interval between the first thin film transistor group as the output transistor and the power supply line is smaller than a second interval between the first thin film transistor group as the output transistor and the data signal line.

In another aspect, an embodiment of the present disclosure provides a display device. The display device includes: the display panel according to any of the above embodiments.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it should be understood that the drawings described below relate only to some embodiments of the present disclosure, and not to limit the present disclosure, wherein:

FIG. 1 is a structural diagram of a display panel;

fig. 2 is a structural diagram of a display panel provided in accordance with an embodiment of the present disclosure;

fig. 3 is a structural diagram of an equivalent circuit of a pixel driving circuit according to an embodiment of the disclosure;

FIG. 4 is a cascade connection diagram of a plurality of shift registers provided according to an embodiment of the present disclosure;

fig. 5 is an equivalent circuit structure diagram of a shift register provided according to some embodiments of the present disclosure;

FIG. 6 is a timing diagram corresponding to the shift register shown in FIG. 4 according to some embodiments of the present disclosure;

fig. 7 is a schematic structural diagram of a display panel provided according to an embodiment of the present disclosure;

FIG. 8 isbase:Sub>A schematic cross-sectional view of the display panel along the direction A-A' in FIG. 7;

FIG. 9 is another schematic cross-sectional view taken along the line A-A' of FIG. 7 according to an embodiment of the present disclosure;

fig. 10 is a schematic structural diagram of a display panel provided according to an embodiment of the present disclosure;

fig. 11 is a schematic structural diagram of a display panel according to another embodiment of the present disclosure;

FIG. 12 is a schematic cross-sectional view taken along the line B-B' in FIG. 11;

FIG. 13 is a schematic cross-sectional view taken along the line C-C of FIG. 11;

FIG. 14 is a schematic cross-sectional view taken along the direction D-D' in FIG. 11; and

fig. 15 is a block diagram of a display device provided in an embodiment of the present disclosure.

Detailed Description

To more clearly illustrate the objects, aspects and advantages of the present disclosure, embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It is to be understood that the following description of the embodiments is intended to illustrate and explain the general concepts of the disclosure and should not be taken as limiting the disclosure. In the specification and drawings, the same or similar reference numerals refer to the same or similar parts or components. The figures are not necessarily to scale and certain well-known components and structures may be omitted from the figures for clarity.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and the like in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", "top" or "bottom", etc. are used merely to indicate relative positional relationships, which may change accordingly when the absolute position of the object being described changes. When an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

Technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided in the present disclosure are within the scope of protection of the present disclosure.

Unless the context requires otherwise, throughout the description and the claims, the term "comprise" and its other forms, such as the third person's singular form "comprising" and the present participle form "comprising" are to be interpreted in an open, inclusive sense, i.e. as "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.

In describing some embodiments, expressions of "coupled" and "connected," along with their derivatives, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, some embodiments may be described using the term "coupled" to indicate that two or more elements are in direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

"at least one of A, B and C" has the same meaning as "at least one of A, B or C" and includes the following combination of A, B and C: a alone, B alone, C alone, a combination of a and B, a combination of a and C, a combination of B and C, and A, B and C.

"A and/or B" includes the following three combinations: a alone, B alone, and a combination of A and B.

As used herein, the term "if" is optionally interpreted to mean "when … …" or "at … …" or "in response to a determination" or "in response to a detection", depending on the context. Similarly, the phrase "if it is determined … …" or "if [ stated condition or event ] is detected" is optionally interpreted to mean "at determination … …" or "in response to determination … …" or "upon detection [ stated condition or event ] or" in response to detection [ stated condition or event ] ", depending on the context.

The use of "adapted to" or "configured to" herein means open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.

In addition, the use of "based on" means open and inclusive, as a process, step, calculation, or other action that is "based on" one or more conditions or values may in practice be based on additional conditions or values that are exceeded.

As used herein, "about" or "approximately" includes the stated value as well as the average value within a range of acceptable deviations for the particular value, as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

As used herein, the same reference numerals may denote both a signal line and a signal terminal and signals corresponding to the signal line and the signal terminal.

Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

Embodiments of the present disclosure provide a display device, which may be, for example, any one of an OLED display device and a QLED (Quantum Dot Light Emitting Diodes) display device.

The structure of the display device will be described below by taking the display device as an OLED display device as an example.

Fig. 1 is a structural view of a display panel.

As shown in fig. 1, the display panel 1 includes a display area 10 and a non-display area 11 located at the periphery of the display area 10, wherein a plurality of pixel units are arranged in an array in the display area 10, and each pixel unit may include one or more sub-pixels P. A pixel driving circuit 12 and a light emitting device D coupled to the pixel driving circuit 12 are disposed in each sub-pixel P. A gate driving circuit 13 is disposed in the non-display region 11, an output terminal of the gate driving circuit 13 is coupled to the gate line 1330, and the pixel driving circuits 12 in the same row are coupled to the same gate line 1330. In the display panel 1, since all the thin film transistors in the gate driving circuit 13 are located in the non-display region 11, a large area is occupied in the non-display region 11, and thus the area of the non-display region 11 is large, for example, the length and the width are both long, which is not favorable for realizing a narrow frame of the display panel 1.

Fig. 2 is a structural diagram of a display panel provided according to an embodiment of the present disclosure.

As shown in fig. 2, the display panel 1' has a display region 10 and a non-display region 11. The non-display area 11 is provided around the display area 10, for example.

The display panel 1' includes: a substrate, a plurality of pixel units and a gate driving circuit 13 disposed on the substrate. Each pixel unit may include one or more sub-pixels P. A plurality of pixel units are arranged in an array in a row direction and a column direction on the substrate, each pixel unit including at least one sub-pixel P, each sub-pixel P including a light emitting element D in a light emitting region and a pixel driving circuit 12 in a non-light emitting region.

The gate driving circuit 13 includes a plurality of cascaded shift registers and a plurality of gate lines, one shift register is coupled to the plurality of pixel driving circuits 12 in at least one row of pixel units through at least one gate line, and the shift register is configured to provide a gate driving signal to the plurality of pixel driving circuits 12 through at least one gate line.

The pixel driving circuit 12 may be, for example, a 2T1C type pixel driving circuit, a 3T1C type pixel driving circuit, or a 7T1C type pixel driving circuit, where T represents a Thin-film transistor (TFT), C represents a storage capacitor, and 2T1C type pixel driving circuit 12 includes 2 TFTs and 1 storage capacitor Cst, and so on. The structure and operation of the pixel driving circuit 12 will be described by taking the pixel driving circuit 12 of 3T1C type as an example.

Fig. 3 is a diagram of an equivalent circuit structure of a pixel driving circuit according to an embodiment of the disclosure.

As shown in fig. 3, 3 pixel drive circuits 12 are shown, each pixel drive circuit 12 including: a thin film transistor T1, a thin film transistor T2, a thin film transistor T3, and a storage capacitor Cst, wherein the thin film transistor T3 is a driving transistor. The gate of the thin film transistor T1 is coupled to a first gate signal terminal G1<1>, the first pole is coupled to the Data signal terminal Data, and the second pole is coupled to the node G. The gate of the thin film transistor T2 is coupled to the second gate signal terminal G2<1>, the first pole is coupled to the sensing signal terminal Sense, and the second pole is coupled to the node S. The gate of the thin film transistor T3 is coupled to the node G, the first pole is coupled to the power voltage signal terminal ELVDD, and the second pole is coupled to the node S. The anode of the light emitting device D is coupled to the node S, and the cathode is coupled to the power voltage signal terminal ELVSS. The storage capacitor Cst has one terminal coupled to the node G and the other terminal coupled to the node S. The first gate signal terminal G1<1> is configured to receive the first gate signal G1, the second gate signal terminal G2<1> is configured to receive the second gate signal G2, the Data signal terminal Data is configured to receive the Data signal Data including, for example, the detection Data signal Data1 and the display Data signal Data2, the power supply voltage signal terminal ELVDD is configured to receive the power supply voltage signal ELVDD ranging, for example, from-5V to 5V, and the power supply voltage signal terminal ELVSS is configured to receive the power supply voltage signal ELVSS being, for example, a fixed voltage signal, for example, a voltage signal less than or equal to 0V; the sensing signal terminal Sense is configured to provide a reset signal for resetting the anode of the light emitting element D or obtain a sensing signal Sense for calculating a threshold voltage of the thin film transistor T3.

When the pixel driving circuit 12 operates in the blanking period of one image Frame (1 Frame), referring to fig. 6, the operation of the pixel driving circuit 12 is, for example: under the control of a first gate signal G11 provided by a first gate signal end G1, the thin film transistor T1 is turned on, and a detection Data signal Data1 is transmitted to a node G through a Data signal end Data; under the control of a second gate signal G21 provided by the second gate signal terminal G2, the thin film transistor T2 is turned on, and a signal of the node S is transmitted to the sensing signal terminal Sense through the thin film transistor T2; when the Data signal Data1 and the power voltage signal ELVDD are detected to turn off the thin film transistor T3 controlled by the node G, the magnitude of the sensing signal Sense at the sensing signal terminal Sense is measured, and the threshold voltage Vth of the thin film transistor T3 can be calculated according to the difference between the Data signal Data1 and the sensing signal Sense.

In the above process, the sensing signal Sense is measured by controlling the sensing transistor (thin film transistor T2), so that the threshold voltage of the driving transistor (thin film transistor T3) is calculated, and the threshold voltage of the driving transistor is calculated and then compensated into the display Data signal Data2, thereby completing the external compensation of the pixel driving circuit 12. Referring to fig. 2, when performing external compensation, the pixel driving circuit 12 needs to receive the first gate signal G11 and the second gate signal G12 to turn on the thin film transistor T2 and the thin film transistor T1, and the sensing signal terminal Sense is in a floating state, which is equivalent to a capacitor; after the sensing Data signal Data1 controls the thin film transistor T3 to be turned on, the power voltage signal ELVDD is transmitted to the node S, the node S is charged until the potential of the node S does not change, at this time, the difference between the potential of the node G and the potential of the node S is equal to the threshold voltage of the thin film transistor T3, the thin film transistor T2 is also in an on state, the signal of the node S is transmitted to the sensing signal terminal Sense through the thin film transistor T2 and is the sensing signal Sense, and the magnitude of the sensing signal Sense is equal to the potential of the node S, so the threshold voltage of the thin film transistor T3 can be calculated by calculating the difference between the sensing Data signal Data1 and the sensing signal Sense.

When the pixel drive circuit 12 operates in the display period of one image frame, the operation process of the pixel drive circuit 12 includes, for example, a reset phase, a data write phase, and a light emission phase.

In the reset phase, the thin film transistor T2 is turned on under the control of the second gate signal G22 provided by the second gate signal terminal G2, and transmits a reset signal provided by the sensing signal terminal Sense to the node S to reset the anode of the light emitting element D.

In the Data writing phase, under the control of the first gate signal G12 provided by the first gate signal terminal G1, the thin film transistor T1 is turned on, transmits the display Data signal Data2 provided by the Data signal terminal Data to the node G, and charges the storage capacitor Cst.

In the light emitting stage, under the control of the node G, the thin film transistor T3 is turned on, and the storage capacitor Cst starts to discharge to the node G, so that the potential of the node G is maintained for a period of time, thereby ensuring the on-time of the thin film transistor T3. After the thin film transistor T3 is turned on, a driving signal, such as a driving current, is output to the light emitting element D under the control of the power supply voltage signal ELVDD provided from the power supply voltage signal terminal ELVDD and the gate voltage thereof, and the light emitting element D starts emitting light under the control of the driving signal.

During the operation of the pixel driving circuit 12 in an image frame, the gate signals received by the first gate signal terminal G1 and the second gate signal terminal G2 are both provided by the gate driving circuit.

The gate driving circuit includes N (N ≧ 2) cascaded shift registers and a plurality of control signal lines, one shift register is coupled to a plurality of pixel driving circuits 12 in at least one row of subpixels P, and at least a portion of the plurality of control signal lines is coupled, and the shift register 130 is configured to provide a gate driving signal to the plurality of pixel driving circuits 12 under control of each control signal line coupled to the shift register.

The gate line may include a first conductive portion, and the first conductive portion may include a second conductive sub-layer at a different layer from the gate electrode to reduce a resistance of the gate line. The control signal line may include conductive members at different layers to reduce the resistance of the control signal line. For example, the Gate lines with the second conductive sub-layer help to reduce the resistance of the Gate lines, improve the problem of insufficient Gate falling edge (which may cause insufficient charging rate) caused by too few output transistors in the Gate driving circuit, and improve the uniformity of the panel display effect.

Fig. 4 is a cascade connection diagram of a plurality of shift registers according to an embodiment of the disclosure.

As shown in fig. 4, the gate drive circuit 13 includes, for example, 6 cascaded shift registers 130 and 22 control signal lines 132. The 6 cascaded shift registers 130 are a first-stage shift register A1, a second-stage shift register A2, a third-stage shift register A3, a fourth-stage shift register A4, a fifth-stage shift register A5 and a sixth-stage shift register A6; each stage of shift register 130 includes an input signal terminal STU, a first output signal terminal OUT1, a second output signal terminal OUT2, and a reset signal terminal STD, and the odd stages of shift register 130 (i.e., the first stage of shift register A1, the third stage of shift register A3, and the fifth stage of shift register A5) further include a cascade output signal terminal CR. The input signal terminal STU is configured to receive an input signal STU. The first output signal terminal OUT1 is configured to output a first gate signal G1 to the first gate signal terminal G1 in the pixel driving circuit 12, the second output signal terminal OUT2 is configured to output a second gate signal G2 to the second gate signal terminal G2 in the pixel driving circuit 12, and the first gate signal G1 and the second gate signal G2 may be the same or different. The reset signal terminal STD is configured to receive a reset signal STD, the reset signals STD of the remaining shift registers 130 are provided by the cascade output signal terminal CR of the N +4 th or N +3 th stage shift register 130 except that the reset signal terminal STD of the last four stages of shift registers 130 is provided by the reset signal line STD, for example, the reset signal terminals STD of the first and second stages of shift registers A1 and A2 are coupled to the cascade output signal terminal CR of the fifth stage shift register A5; the cascade output signal terminal CR of the shift register 130 is further configured to provide the input signal STU to the input signal terminals STU of a part of the shift register 130, e.g. the input signal terminals STU of the third stage shift register A3 and the fourth stage shift register A4 are coupled to the cascade output signal terminal CR of the first stage shift register A1.

The 22 control signal lines 132 include an input signal line STU, a global reset signal line TRST, a reset signal line STD, a random signal line OE, a power line VDDA, a power line VDDB, a clock signal line CLKA, a clock signal line CLKD (including a clock signal line CLKD1, a clock signal line CLKD3, a clock signal line CLKD 5), a clock signal line CLKE (including a clock signal line CLKE1, a clock signal line CLKE2, a clock signal line CLKE3, a clock signal line CLKE4, a clock signal line CLKE5, a clock signal line CLKE 6), a clock signal line CLKF (including a clock signal line CLKF1, a clock signal line CLKF2, a clock signal line CLKF3, a clock signal line CLKF4, a clock signal line CLKF5, a clock signal line CLKF 6).

The input signal line STU is configured to supply the input signal STU to the input signal terminals STU of some shift registers 130, for example, the input signal line STU supplies the input signal to the input signal terminals STU of the first stage shift register A1 and the second stage shift register A2; the input signal terminals STU of the third shift register A3 and the fourth shift register A4 are coupled to the cascade output signal terminal CR of the first shift register A1, and the output signal of the cascade output signal terminal CR of the first shift register A1 is used as the input signal STU; the input signal terminals STU of the fifth-stage shift register A5 and the sixth-stage shift register A6 are coupled to the cascade output signal terminal CR of the third-stage shift register A3, and an output signal of the cascade output signal terminal CR of the third-stage shift register A3 is used as the input signal STU.

The global reset signal line TRST is configured to supply a global reset signal TRST to the global reset signal terminals TRST of all the shift registers 130, so that each stage of the shift registers 130 is coupled to the global reset signal line TRST.

The reset signal line STD is configured to supply a reset signal STD to a reset signal terminal STD in the shift register 130, and the last four-stage shift register 130 in the gate drive circuit 13 is coupled to the reset signal line STD.

The random signal line OE is configured to supply a random signal OE to a random signal terminal OE in the shift register 130, for example, to the shift registers 130 of the odd stages (i.e., the first stage shift register A1, the third stage shift register A3, and the fifth stage shift register A5).

The power supply lines VDDA and VDDB are configured to provide a power supply voltage signal VDDA to a power supply voltage signal terminal VDDA and a power supply voltage signal VDDB to a power supply voltage signal terminal VDDB in the shift register 130. Wherein the power supply line VDDA is configured to supply the power supply voltage signal VDDA to the shift registers 130 of the odd stages (i.e., the first stage shift register A1, the third stage shift register A3, and the fifth stage shift register A5); the power supply line VDDB is configured to supply the power supply voltage signal VDDB to the shift registers 130 of the even-numbered stages (i.e., the second-stage shift register A2, the fourth-stage shift register A4, and the sixth-stage shift register A6).

The clock signal line CLKA is configured to provide a clock signal CLKA to a clock signal terminal CLKA in the shift register 130, for example, to provide the clock signal CLKA to each stage of the shift register 130, so that each stage of the shift register 130 needs to be coupled with the clock signal line CLKA.

The clock signal line CLKD is configured to supply the clock signal CLKD to a clock signal terminal CLKD in the shift register 130, for example, to the shift registers 130 of odd stages (i.e., the first stage shift register A1, the third stage shift register A3, and the fifth stage shift register A5); specifically, for example, the clock signal CLKD1 is supplied to the first stage shift register A1; a clock signal CLKD3 is supplied to the third stage shift register A3; a clock signal CLKD5 is supplied to the fifth stage shift register A5; the clock signals CLKD1, CLKD3, and CLKD5 may be the same or different, and are not limited in this embodiment of the disclosure.

The clock signal line CLKE is configured to provide the clock signal CLKE to the clock signal terminal CLKE in the shift register 130, e.g., to provide the clock signal CLKE to each stage of the shift register 130, such that each stage of the shift register 130 needs to be coupled with the clock signal line CLKE; specifically, a first stage shift register A1 is coupled to a clock signal line CLKE1, a second stage shift register A2 is coupled to a clock signal line CLKE2, a third stage shift register A3 is coupled to a clock signal line CLKE3, a fourth stage shift register A4 is coupled to a clock signal line CLKE4, a fifth stage shift register A5 is coupled to a clock signal line CLKE5, and a sixth stage shift register A6 is coupled to a clock signal line CLKE 6; the clock signals CLKE1, CLKE2, CLKE3, CLKE4, CLKE5, and CLKE6 may be the same or different, which is not limited in this embodiment of the disclosure.

The clock signal line CLKF is configured to provide a clock signal CLKF to a clock signal terminal CLKF in the shift register 130, e.g., to provide the clock signal CLKF to each stage of the shift register 130, such that each stage of the shift register 130 needs to be coupled to the clock signal line CLKF; specifically, a first-stage shift register A1 is coupled to a clock signal line CLKF1, a second-stage shift register A2 is coupled to a clock signal line CLKF2, a third-stage shift register A3 is coupled to a clock signal line CLKF3, a fourth-stage shift register A4 is coupled to a clock signal line CLKF4, a fifth-stage shift register A5 is coupled to a clock signal line CLKF5, and a sixth-stage shift register A6 is coupled to a clock signal line CLKF 6; the clock signals CLKF1, CLKF2, CLKF3, CLKF4, CLKF5, and CLKF6 may be the same or different, and the embodiment of the present disclosure is not limited thereto.

In some embodiments, clock signal CLKE is the same as clock signal CLKF, i.e., clock signal CLKE1 is the same as clock signal CLKF1, clock signal CLKE2 is the same as clock signal CLKF2, clock signal CLKE3 is the same as clock signal CLKF3, clock signal CLKE4 is the same as clock signal CLKF4, clock signal CLKE5 is the same as clock signal CLKF5, and clock signal CLKE6 is the same as clock signal CLKF 6.

Fig. 5 is an equivalent circuit structure diagram of a shift register provided according to some embodiments of the present disclosure.

As shown in fig. 5, based on the cascade connection pattern of the plurality of shift registers 130 as shown above, the shift register 130 provided by the embodiment of the present disclosure may include: blanking input subcircuit 1301, display input subcircuit 1302, control subcircuit 1303, output subcircuit 1304, reset subcircuit 1305, and global reset subcircuit 1306.

For example, for the shift register 130 of the nth stage, the blanking input sub-circuit 1301 is configured to control the gate driving circuit 13 to output a blanking control signal to the pixel driving circuit 12, for example, to output a first gate signal G11 to the first gate signal terminal G1 and output a second gate signal G21 to the second gate signal terminal G2, under the control of the first gate signal G11, the thin film transistor T1 is turned on, under the control of the second gate signal G21, the thin film transistor T2 is turned on, a signal of the node S may be transmitted to the sensing signal terminal Sense, and the sensing signal Sense may be obtained by measuring the signal magnitude on the sensing signal terminal Sense. In the blanking period, the pixel driving circuit 12 does not drive the light emitting element D to emit light, but obtains the threshold voltage of the thin film transistor T3 in order to obtain the threshold voltage of the thin film transistor T3, which has been described above, and thus is not described again.

The blanking input sub-circuit 1301 includes, for example, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, an eleventh transistor M11, and a first capacitor C1.

The gate of the first transistor M1 is coupled to the random signal terminal OE, the first pole of the first transistor M1 is coupled to the cascade output signal terminal CR < N >, and the second pole of the first transistor M1 is coupled to the first pole of the second transistor M2. The gate of the second transistor M2 is coupled to the random signal terminal OE, the first pole of the second transistor M2 is coupled to the second pole of the third transistor M3, and the second pole of the second transistor M2 is coupled to the node H. The gate of the third transistor M3 is coupled to the node H, the first pole of the third transistor M3 is coupled to the power voltage signal terminal VDD, and the second pole of the third transistor M3 is coupled to the second pole of the first transistor M1. The gate of the fourth transistor M4 is coupled to the node H, the first pole of the fourth transistor M4 is coupled to the clock signal terminal CLKA, and the second pole of the fourth transistor M4 is coupled to the node N < N >. A gate of the fifth transistor M5 is coupled to the clock signal terminal CLKA, a first pole of the fifth transistor M5 is coupled to the node N < N >, and a second pole of the fifth transistor M5 is coupled to a first pole of the sixth transistor M6. The gate of the sixth transistor M6 is coupled to the clock signal terminal CLKA, the first pole of the sixth transistor M6 is further coupled to the leakage-preventing node OFF < N >, and the second pole of the sixth transistor M6 is coupled to the pull-up node Q < N >. The gate of the eleventh transistor M11 is coupled to the pull-up node Q < N >, the first pole of the eleventh transistor M11 is coupled to the power voltage signal terminal VDD, and the second pole of the eleventh transistor M11 is coupled to the leakage prevention node OFF < N >. One end of the first capacitor C1 is coupled to the node H, and the other end is coupled to the first voltage signal terminal VGL 1.

The display input sub-circuit 1302 is configured to control the gate driving circuit 13 to output a display control signal to the pixel driving circuit 12, for example, to output a first gate signal G12 to the first gate signal terminal G1 and output a second gate signal G22 to the second gate signal terminal G2, the thin film transistor T1 is turned on under the control of the first gate signal G12, the thin film transistor T2 is turned on under the control of the second gate signal G22, and a reset signal provided by the sensing signal terminal Sense is transmitted to the node S through the thin film transistor T2 during a display period of an image frame. In the display period, the pixel driving circuit 12 will drive the light emitting element D to emit light, and the process of driving the light emitting element D to emit light by the pixel driving circuit 12 is described above, and therefore will not be described in detail.

The display input sub-circuit 1302 includes, for example: a seventh transistor M7 and an eighth transistor M8.

The gate and the first pole of the seventh transistor M7 are coupled to the input signal terminal STU, and the second pole of the seventh transistor M7 is coupled to the first pole of the eighth transistor M8 and the leakage-preventing node OFF < N >. A gate of the eighth transistor M8 is coupled to the input signal terminal STU, and a second pole of the eighth transistor M8 is coupled to the pull-up node Q < N >. In the display period, the seventh transistor M7 and the eighth transistor M8 are turned on under the control of the input signal STU provided from the input signal terminal STU, and transmit the input signal STU of a high level to the pull-up node Q < N > and the leakage preventing node OFF < N >, and pull up the potentials of the pull-up node Q < N > and the leakage preventing node OFF < N >.

The control sub-circuit 1303 is configured to control the potential balance of the pull-up node Q < N > and the first pull-down node QBA, for example, when the pull-up node Q < N > is high level, the control sub-circuit 1303 controls the potential of the first pull-down node QBA to be low level, and when the potential of the first pull-down node QBA is high level, the control sub-circuit 1303 controls the potential of the pull-up node Q < N > to be high level.

The control sub-circuit 1303 includes, for example: an eighteenth transistor M18, a nineteenth transistor M19, a twentieth transistor M20, a twenty-first transistor M21, a twentieth transistor M22, a twenty-third transistor M23, and a twenty-fourth transistor M24.

The gate and the first pole of the eighteenth transistor M18 are coupled to the power supply voltage signal terminal VDDA, and the second pole of the eighteenth transistor M18 is coupled to the gate of the nineteenth transistor M19. A first pole of the nineteenth transistor M19 is coupled to the power supply voltage signal terminal VDDA, and a second pole of the nineteenth transistor M19 is coupled to the first pull-down node QBA. A gate of the twentieth transistor M20 is coupled to the pull-up node Q < N >, a first pole of the twentieth transistor M20 is coupled to the gate of the nineteenth transistor M19, and a second pole of the twentieth transistor M20 is coupled to the first voltage signal terminal VGL 1. The gate of the twenty-first transistor M21 is coupled to the pull-up node Q < N >, the first pole of the twenty-first transistor M21 is coupled to the first voltage signal terminal VGL1, and the second pole of the twenty-first transistor M21 is coupled to the first pull-down node QBA. A gate of the twentieth transistor M22 is coupled to the clock signal terminal CLKA, a first pole of the twentieth transistor M22 is coupled to the first pull-down node QBA, and a second pole of the twentieth transistor M22 is coupled to a second pole of the twenty-third transistor M23. A gate of the twenty-third transistor M23 is coupled to the node H, and a first pole of the twenty-third transistor M23 is coupled to the first voltage signal terminal VGL 1. A gate of the twenty-fourth transistor M24 is coupled to the input signal terminal STU, a first pole of the twenty-fourth transistor M24 is coupled to the first voltage signal terminal VGL1, and a second pole of the twenty-fourth transistor M24 is coupled to the first pull-down node QBA. The eighteenth transistor M18 is turned on under the control of the power supply voltage signal VDDA provided from the power supply voltage signal terminal VDDA, and the second pole of the eighteenth transistor M18 transmits the power supply voltage signal VDDA of the high level to the gate of the nineteenth transistor M19, so as to control the nineteenth transistor M19 to be turned on, and after the nineteenth transistor M19 is turned on, the power supply voltage signal VDDA of the high level may be transmitted to the first pull-down node QBA, so as to charge the first pull-down node QBA. When the pull-up node Q < N > is at a high level, the twentieth transistor M20 and the twenty-first transistor M21 are turned on, wherein the twentieth transistor M20 transmits the first voltage signal VGL1 of a low level provided from the first voltage signal terminal VGL1 to the gate of the nineteenth transistor M19, so that the nineteenth transistor M19 is turned off; when the twenty-first transistor M21 is turned on, the first voltage signal VGL1 of a low level may be transmitted to the first pull-down node QBA to discharge the first pull-down node QBA. Under the control of the high-level input signal STU provided from the input signal terminal STU, the twenty-fourth transistor M24 is turned on, and transmits the low-level first voltage signal VGL1 to the first pull-down node QBA to discharge the first pull-down node QBA. When the level of the node H is at a high level, the twenty-third transistor M23 is turned on, and the first voltage signal VGL1 at a low level provided by the first voltage signal terminal VGL1 is transmitted to the first pole of the twenty-second transistor M22; when the clock signal CLKA provided by the clock signal terminal CLKA is also at a high level, the twenty-second transistor M22 is turned on, transmitting the first voltage signal VGL1 at a low level to the first pull-down node QBA to pull down the potential of the first pull-down node QBA. In the display period, when the input signal STU of high level is present, the seventh transistor M7 and the eighth transistor M8 are turned on to charge the pull-up node Q < N >, and when the pull-up node Q < N > is high level, the first pull-down node QBA needs to be low level, so that the potential relationship between the pull-up node Q < N > and the first pull-down node QBA can be controlled by the twenty-four transistor M24. In the blanking period, when the clock signal terminal CLKA supplies the clock signal CLKA at the high level and the node H at the high level, the pull-up node Q < N > will be at the high level, and thus it is necessary to control the potential relationship between the pull-up node Q < N > and the first pull-down node QBA through the twenty-second and twenty-third transistors M23. When the pull-up node Q < N > is at a high level, the twentieth transistor M20 is turned on, turning off the nineteenth transistor M19, thereby causing the supply voltage signal terminal VDDA to stop charging the first pull-down node QBA, while the twenty-first transistor M21 is turned on, transmitting the first voltage signal VGL1 at a low level to the first pull-down node QBA to pull down the potential of the first pull-down node QBA. Accordingly, the control sub-circuit 1303 realizes control of the potentials of the pull-up node Q < N > and the first pull-down node QBA.

The output sub-circuit 1304 is configured to output the first gate signal G11 and the second gate signal G21 in a blanking period of one image frame, and output the first gate signal G12 and the second gate signal G22 in a display period of one image frame.

The output sub-circuit 1304 includes, for example: a twenty-fifth transistor M25, a twenty-eighth transistor M28, a thirty-first transistor M31, a second capacitor C2, and a third capacitor C3.

A gate of the twenty-fifth transistor M25 is coupled to the pull-up node Q < N >, a first pole of the twenty-fifth transistor M25 is coupled to the clock signal terminal CLKD1, and a second pole of the twenty-fifth transistor M25 is coupled to the cascade output signal terminal CR < N >. The gate pull-up node Q < N > of the twenty-eighth transistor M28 is coupled, a first pole of the twenty-eighth transistor M28 is coupled to the clock signal terminal CLKE1, and a second pole of the twenty-eighth transistor M28 is coupled to the first output signal terminal OUT 1. A gate of the thirty-first transistor M31 is coupled to the pull-up node Q < N >, a first pole of the thirty-first transistor M31 is coupled to the clock signal terminal CLKF1, and a second pole of the thirty-first transistor M31 is coupled to the second output signal terminal OUT2. One end of the second capacitor C2 is coupled to the gate of the twenty-eighth transistor M28, and the other end is coupled to the first output signal terminal OUT 1. One end of the third capacitor C3 is coupled to the gate of the thirty-first transistor M31, and the second end is coupled to the second output signal terminal OUT2. When the pull-up node Q < N > is at a high level, the twenty-fifth transistor M25, the twenty-eighth transistor M28, and the thirty-first transistor M31 are turned on, wherein the twenty-fifth transistor M25 transmits the clock signal CLKD1 provided by the clock signal terminal CLKD1 to the cascade output signal terminal CR < N >, the twenty-eighth transistor M28 transmits the clock signal CLKE1 provided by the clock signal terminal CLKE1 to the first output signal terminal OUT1, and a signal output from the first output signal terminal OUT1 is the first gate signal G1; the thirty-first transistor M31 transmits the clock signal CLKF1 provided by the clock signal terminal CLKF1 to the second output signal terminal OUT2, and the signal output from the second output signal terminal OUT2 is the second gate signal G2. The second capacitor C2 is used for holding the gate potential of the twenty-eighth transistor M28, so that the twenty-eighth transistor M28 can be kept in an on state, and outputs the clock signal CLKE1; the third capacitor C3 is used for holding the gate potential of the thirty-first transistor M31, so that the thirty-first transistor M31 can be kept in an on state, and the clock signal CLKF1 is output. The cascade signal CR < N > output by the cascade output signal terminal CR < N > is received by, for example, the first pole of the first transistor M1, and thus serves as an input signal for the blanking input sub-circuit 1301.

The output sub-circuit 1304 includes a first output signal terminal OUT1 and a second output signal terminal OUT2. Referring to fig. 3, the first output signal terminal OUT1 is configured to provide the first gate signal G1 to the first gate signal terminal G1, and the second output signal terminal OUT2 is configured to provide the second gate signal G2 to the second gate signal terminal G2, so that the first gate signal G1 and the second gate signal G2 may be the same or different on the premise of ensuring that the pixel driving circuit 12 can operate normally, which is not limited in this disclosure.

The reset sub-circuit 1305 is configured to reset the pull-up node Q < N >, the first pull-down node QBA, the leakage preventing node OFF < N >, and the output sub-circuit 1304. The reset sub-circuit 1305 includes, for example, a first reset sub-circuit 13051 and a second reset sub-circuit 13052, wherein the first reset sub-circuit 13051 is configured to reset the pull-up node Q < N >, the first pull-down node QBA, and the output sub-circuit 1304; the second reset sub-circuit 13052 is configured to reset the pull-up node Q < N > and the leakage preventing node OFF < N >.

The first reset sub-circuit 13051 includes, for example: a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, a twenty sixth transistor M26, a twenty seventh transistor M27, a twenty ninth transistor M29, a thirty transistor M30, a thirty second transistor M32, and a thirty third transistor M33. The gate of the fourteenth transistor M14 is coupled to the first pull-down node QBA, the first pole of the fourteenth transistor M14 is coupled to the leakage-preventing node OFF < N >, and the second pole of the fourteenth transistor M14 is coupled to the pull-up node Q < N >. The gate of the fifteenth transistor M15 is coupled to the first pull-down node QBA, a first pole of the fifteenth transistor M15 is coupled to the first voltage signal terminal VGL1, and a second pole of the fifteenth transistor M15 is coupled to the leakage-preventing node OFF < N >. A gate of the twenty-sixth transistor M26 is coupled to the first pull-down node QBA, a first pole of the twenty-sixth transistor M26 is coupled to the first voltage signal terminal VGL1, and a second pole of the twenty-sixth transistor M26 is coupled to the cascade output signal terminal CR < N >. A gate of the twenty-ninth transistor M29 is coupled to the first pull-down node QBA, a first pole of the twenty-ninth transistor M29 is coupled to the second voltage signal terminal VGL2, and a second pole of the twenty-ninth transistor M29 is coupled to the first output signal terminal OUT 1. A gate of the thirty-second transistor M32 is coupled to the first pull-down node QBA, a first pole of the thirty-second transistor M32 is coupled to the second voltage signal terminal VGL2, and a second pole of the thirty-second transistor M32 is coupled to the second output signal terminal OUT2. When the first pull-down node QBA is at a high level, the fourteenth transistor M14, the fifteenth transistor M15, the twenty-sixth transistor M26, the twenty-ninth transistor M29 and the thirty-second transistor M32 are all turned on, wherein the fifteenth transistor M15 transmits the first voltage signal VGL1 provided by the first voltage signal terminal VGL1 to the anti-leakage node OFF < N > for resetting, and the potential of the anti-leakage node OFF < N > is at a low level, and the low level signal is equal to the first voltage signal VGL1, for example, and when the fourteenth transistor M14 is turned on, the low level signal can be transmitted to the pull-up node Q < N >, and the pull-up node Q < N > is reset; when the twenty-sixth transistor M26 is turned on, the first voltage signal VGL1 provided by the first voltage signal terminal VGL1 may be transmitted to the cascade output signal terminal CR < N > to reset the cascade output signal terminal CR < N >; when the twenty-ninth transistor M29 is turned on, the second voltage signal VGL2 provided by the second voltage signal terminal VGL2 may be transmitted to the first output signal terminal OUT1 to reset the first output signal terminal OUT 1; when the thirty-second transistor M32 is turned on, the second voltage signal VGL2 provided by the second voltage signal terminal VGL2 may be transmitted to the second output signal terminal OUT2 to reset the second output signal terminal OUT2. When the second pull-down node QBB is at a high level, the sixteenth transistor M16, the seventeenth transistor M17, the twenty seventh transistor M27, the thirty third transistor M30, and the thirty third transistor M33 are turned on, wherein the sixteenth transistor M16 has the same function as the fourteenth transistor M14, the seventeenth transistor M17 has the same function as the fifteenth transistor M15, the twenty seventh transistor M27 has the same function as the twenty sixth transistor M26, the thirty transistor M30 has the same function as the twenty ninth transistor M29, and the thirty third transistor M33 has the same function as the thirty second transistor M32, so that the operations of the sixteenth transistor M16, the seventeenth transistor M17, the twenty seventh transistor M27, the thirty third transistor M30, and the thirty third transistor M33 will be understood with reference to the description of the fourteenth transistor M14, the fifteenth transistor M15, the twenty sixth transistor M26, the twenty ninth transistor M29, and the thirty second transistor M32 in the foregoing.

The second reset subcircuit 13052 includes, for example: a twelfth transistor M12 and a thirteenth transistor M13. A gate of the twelfth transistor M12 is coupled to the reset signal terminal STD, a first pole of the twelfth transistor M12 is coupled to the leakage preventing node OFF < N >, and a second pole of the twelfth transistor M12 is coupled to the pull-up node Q < N >. A gate of the thirteenth transistor M13 is coupled to the reset signal terminal STD, a first pole of the thirteenth transistor M13 is coupled to the first voltage signal terminal VGL1, and a second pole of the thirteenth transistor M13 is coupled to the leakage prevention node OFF < N >. When the reset signal STD provided from the reset signal terminal STD is at a high level, the twelfth transistor M12 and the thirteenth transistor M13 are turned on; after the thirteenth transistor M13 is turned on, the first voltage signal VGL1 provided by the first voltage signal terminal VGL1 may be transmitted to the anti-leakage node OFF < N >, and the anti-leakage node OFF < N > is reset; when the twelfth transistor M12 is turned on, a low level signal (e.g., the first voltage signal VGL 1) at the anti-leakage node OFF < N > may be transmitted to the pull-up node Q < N >, and the pull-up node Q < N > may be reset, or it may be understood that the twelfth transistor M12 may transmit the first voltage signal VGL1 to the pull-up node Q < N > through the thirteenth transistor M13.

The global reset subcircuit 1306 is configured to reset the pull-up node Q < N > and the anticreeping node OFF < N > twice.

The global reset subcircuit 1306 includes, for example: a ninth transistor M9 and a tenth transistor M10. A gate of the ninth transistor M9 is coupled to the global reset signal terminal TRST, a first pole of the ninth transistor M9 is coupled to a second pole of the tenth transistor M10, and the second pole of the ninth transistor M9 is coupled to the pull-up node Q < N >. A gate of the tenth transistor M10 is coupled to the global reset signal terminal TRST, a first pole of the tenth transistor M10 is coupled to the first voltage signal terminal VGL1, and a second pole is coupled to the leakage preventing node OFF < N > node. When the global reset signal TRST provided by the global reset signal terminal TRST is at a high level, the ninth transistor M9 and the tenth transistor M10 are turned on, wherein the tenth transistor M10 transmits the first voltage signal VGL1 provided by the first voltage signal terminal VGL1 to the anti-leakage node OFF < N > node and the first pole of the ninth transistor M9 to reset the anti-leakage node OFF < N > node, and simultaneously the ninth transistor M9 may transmit the first voltage signal VGL1 to the pull-up node Q < N > to reset the pull-up node Q < N >.

The above is an explanation of the structure of the shift register 130 of the nth stage, and referring to fig. 5, the structure of the shift register of the (N + 1) th stage is similar to that of the shift register of the nth stage, in which the shift register of the nth stage and the shift register of the (N + 1) th stage share a part of the thin film transistors. For example, referring to fig. 5, the N +1 th stage shift register 130 includes, for example: a thirty-fourth transistor M34, a thirty-fifth transistor M35, and a fortieth transistor M40 for constituting the blanking input sub-circuit 1301; a thirty-sixth transistor M36 and a thirty-seventh transistor M37 for constituting the display input sub-circuit 1302; a forty-seventh transistor M47, a forty-eighth transistor M48, a forty-ninth transistor M49, a fifty-fifth transistor M50, a fifty-first transistor M51, a fifty-fifth transistor M52, and a fifty-third transistor M53 for constituting the control sub-circuit 1303; a fifty-fourth transistor M54, a fifty-seventh transistor M57, a fourth capacitor C4, and a fifth capacitor C5 for constituting the output sub-circuit 1304; a forty-third transistor M43, a forty-fourth transistor M44, a forty-fifth transistor M45, a forty-sixth transistor M46, a fifty-fifth transistor M55, a fifty-sixth transistor M56, a fifty-eighth transistor M58, and a fifty-ninth transistor M59 for constituting a first reset sub-circuit 13051 in the reset sub-circuit 1305; a forty-first transistor M41 and a forty-second transistor M42 for constituting a second reset sub-circuit 13052; a thirty-eighth transistor M38 and a thirty-ninth transistor M39 for constituting the global reset sub-circuit 1306.

The blank input sub-circuit 1301 in the N +1 th row shares the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, and the first capacitor C1 with the blank input sub-circuit in the nth row, so that the number of thin film transistors can be reduced.

The first pull-down node QBA of the nth row is coupled to the first pull-down node QBA of the N +1 th row, and the second pull-down node QBB of the nth row is coupled to the first pull-down node QBB of the N +1 th row. The first pull-down node QBA and the second pull-down node QBB in the nth row are coupled to an external voltage signal terminal, and the potentials of the first pull-down node QBA and the second pull-down node QBB may jump to a high potential through the external voltage signal terminal. Meanwhile, the first pull-down node QBA of the nth row is coupled to the first pull-down node QBA of the N +1 th row, and the second pull-down node QBB of the nth row is coupled to the first pull-down node QBB of the N +1 th row, so that the number of thin film transistors can be reduced, and the working pressure of the thin film transistors can be reduced; and the first pull-down node QBA and the second pull-down node QBB are arranged in each row, so that the first pull-down node QBA and the second pull-down node QBB can work alternately, and the working pressure of the thin film transistor is reduced.

Fig. 6 is a timing diagram corresponding to the shift register in fig. 5 according to some embodiments of the disclosure.

As shown in fig. 6, in one image frame, the display period is before the blanking period, that is, the shift register 130 outputs the first gate signal G12 and the second gate signal G22 to the pixel driving circuit 12, and outputs the first gate signal G11 and the second gate signal G21 to the pixel driving circuit 12.

For the nth stage shift register 130, in the display period, first, the global reset signal provided by the global reset signal terminal TRST is at a high level, the global reset sub-circuit 1306 starts to operate, the ninth transistor M9 and the tenth transistor M10 are turned on, and the pull-up node Q < N > and the anti-leakage node OFF < N > are reset respectively; a random signal OE provided by a random signal end OE is at a high level, a first transistor M1 and a second transistor M2 are turned on, since there is no output signal at a cascade output signal end CR < N >, the potential of a node H is at a low level, a power supply voltage signal VDDA provided by a power supply voltage signal end VDDA is at a high level, an eighteenth transistor M18 and a nineteenth transistor M19 in the control sub-circuit 1303 are turned on, and the first pull-down node QBA is charged, so that the potential of the first pull-down node QBA is at a high level; next, the input signal STU provided by the input signal terminal STU is at a high level, the twenty-fourth transistor M24 is turned on, and the first voltage signal VGL1 is transmitted to the first pull-down node QBA so that the potential of the first pull-down node QBA becomes a low level; when the input signal STU is at a high level, the display input sub-circuit 1302 starts to operate, the seventh transistor M7 and the eighth transistor M8 are turned on, and the pull-up node Q < N > and the leakage-prevention node OFF < N > are charged, so that potentials of the pull-up node Q < N > and the leakage-prevention node OFF < N > are at a high level; when the potential of the pull-up node Q < N > is high level, the twentieth transistor M20 and the twenty-first transistor M21 are turned on, thereby turning off the nineteenth transistor M19 and keeping the potential of the first pull-down node QBA low level; when the potential of the pull-up node Q < N > is at a high level, the twenty-fifth transistor M25, the twenty-eighth transistor M28, and the thirty-first transistor M31 are turned on, and the cascade output signal terminal CR < N >, the first output signal terminal OUT1, and the second output signal terminal OUT2 start to output signals, respectively, where the signal output by the cascade output signal terminal CR < N > is, for example, the input signal STU of the N +2 th or N +3 th stage shift register 130, the first output signal output by the first output signal terminal OUT1 is, for example, the first gate signal G12, and the second output signal output by the second output signal terminal OUT2 is, for example, the second gate signal G22; when the potential of the pull-up node Q < N > is at a high level, the eleventh transistor M11 is turned on, the power supply voltage signal VDD provided by the power supply voltage signal terminal VDD is transmitted to the anti-leakage node OFF < N >, the potential of the anti-leakage node OFF < N > is at a high level, at this time, for the sixth transistor M6, the first pole of the sixth transistor M6 is coupled to the anti-leakage node OFF < N >, and is therefore at a high level, the second pole of the sixth transistor M6 is coupled to the pull-up node Q < N >, and is also at a high level, so that the charge of the pull-up node Q < N > can be prevented from leaking through the sixth transistor M6, and the anti-leakage effect is realized; when the clock signal CLKD1 provided by the clock signal terminal CLKD1 is at a high level and the random signal OE is also at a high level, the blanking input sub-circuit 1301 charges the node H through the first transistor M1 and the second transistor M2, the high level of the node H can be maintained for a period of time due to the presence of the first capacitor C1, the fourth transistor M4 is turned on and the twenty-third transistor M23 is turned on when the potential of the node H is at a high level, the potential of the node N coupled to the second pole of the fourth transistor M4 is always at a low level in the display period because the clock signal CLKA provided by the clock signal terminal CLKA is at a low level throughout the display period, and the fifth transistor M5 and the sixth transistor M6 are always at a cut-off state in the display period; when the sixth transistor M6 has no output signal, the eleventh transistor M11 is in an off state; finally, when the reset signal STD provided by the reset signal terminal STD is at a high level, the twelfth transistor M12 and the thirteenth transistor M13 are turned on, and the pull-up node Q < N > and the anti-leakage node OFF < N > are reset, so that the levels of the pull-up node Q < N > and the anti-leakage node OFF < N > become low levels, when the potential of the pull-up node Q < N > becomes low levels, the cascade output signal terminal CR < N >, the first output signal terminal OUT1, and the second output signal terminal OUT2 stop outputting signals, and since the power supply voltage signal VDDA is at a high level, the potential of the first pull-down node QBA returns to a high level, and when the potential of the first pull-down node QBA is at a high level, the fourteenth transistor M14, the fifteenth transistor M15, the twenty-sixth transistor M26, the twenty-ninth transistor M29, and the thirty-second transistor M32 are turned on; the fourteenth transistor M14 and the fifteenth transistor M15 may respectively transmit the first voltage signal VGL1 to the pull-up node Q < N > and the anti-leakage node OFF < N > to reset the pull-up node Q < N > and the anti-leakage node OFF < N >; the twenty-sixth transistor M26 may transmit the first voltage signal VGL1 to the cascade output signal terminal CR < N > to reset it, and the twenty-ninth transistor M29 and the thirty-second transistor M32 may transmit the second voltage signal VGL2 of a low level provided from the second voltage signal terminal VGL2 to the first output signal terminal OUT1 and the first output signal terminal OUT2, respectively, to reset the first output signal terminal OUT1 and the first output signal terminal OUT2, and the display period ends.

In the blanking period, since the clock signal CLKA is at a high level and the potential of the node H can be maintained to the blanking period, the fourth transistor M4 can output a signal of a high electrical level to the node N, the potential of the node N is at a high level, and since the clock signal CLKA and the potential of the node H are at a high level, both the twenty-third transistor M23 and the twenty-second transistor M22 are turned on, and the first voltage signal VGL1 of a low level provided by the first voltage signal terminal VGL1 is transmitted to the first pull-down node QBA, so that the potential of the first pull-down node QBA becomes a low level; since the clock signal CLKA is at a high level, the fifth transistor M5 and the sixth transistor M6 are turned on, transmitting the signal of the node N to the pull-up node Q < N >, so that the potential of the pull-up node Q < N > becomes a high level; when the potential of the pull-up node Q < N > becomes high level, the clock signal CLKD1 is low level and the clock signal CLKE1 is high level, so that the first output signal terminal OUT1 starts outputting the first gate signal G11 and the second output signal terminal OUT2 starts outputting the second gate signal G21.

When the external voltage signal terminal makes the second pull-down node QBB high, the sixteenth transistor M16, the seventeenth transistor M17, the twenty-seventh transistor M27, the thirtieth transistor M30, and the thirty-third transistor M33 are turned on; the sixteenth transistor M16 and the seventeenth transistor M17 may transmit the first voltage signal VGL1 to the pull-up node Q < N > and the anti-leakage node OFF < N > respectively, so as to reset the pull-up node Q < N > and the anti-leakage node OFF < N >; the twenty-seventh transistor M27 may transmit the first voltage signal VGL1 to the cascade output signal terminal CR < N > to reset it; the thirty-third and thirty-fourth transistors M30 and M33 may transmit the second voltage signal VGL2 to the first and second output signal terminals OUT1 and OUT2 to reset the first and second output signal terminals OUT1 and OUT2.

In the image frame, the clock signal CLKE is the same as the clock signal CLKF, the first voltage signal VGL1 and the second voltage signal VGL2 are both low level signals all the time, and the power supply voltage signal terminal VDD is a high level signal all the time, which is not shown in fig. 5. In an image frame, the first voltage signal VGL1 and the second voltage signal VGL2 are low-level voltage signals, which may be the same or different, and this disclosure does not limit this.

It will be understood by those skilled in the art that the high level and the low level in the present disclosure are relative values, for example, the high level is 15V, and the low level is 5V, and therefore, the low level is limited to be 0V or less.

The timing diagram shown in fig. 6 corresponds to the thin film transistors in the shift register 130 being all N-type, as an example only.

It will be understood by those skilled in the art that the structure and number of the shift registers 130 and the number and type of the control signal lines 132 included in the gate driving circuit 13 are exemplary descriptions, and thus the structure and number of the shift registers 130 and the number and type of the control signal lines 132 in the present disclosure are not limited thereto.

The plurality of transistors included in the nth stage shift register 130 and the N +1 th stage shift register 130 may be referred to as first thin film transistors, for example, and the plurality of first thin film transistors included in each stage of the shift register 130 may be divided into a plurality of first thin film transistor groups 131, each of the first thin film transistor groups 131 including at least one first thin film transistor. For example, each of the sub-circuits included in the nth stage shift register 130 includes, for example, at least one first thin film transistor group 131.

It should be noted that the first thin film transistors included in the gate driving circuit 13 may be all located in the display region of the display panel, for example, in the non-emitting region of the display region. The first thin film transistor included in the gate driving circuit 13 may be partially located in the display region of the display panel, for example, a portion of the first thin film transistor is disposed in a non-emitting region of the display region, and a portion of the first thin film transistor is disposed in the non-display region.

The shift register 130 includes a plurality of first thin film transistor groups 131, at least one first thin film transistor group 131 is located in the display region 10 and is distributed between adjacent sub-pixels P in the same row of sub-pixels P. Since at least one first thin film transistor group 131 in the shift register 130 is disposed in the display region 10, the area occupied by the gate driving circuit 13 in the non-display region 11 can be reduced, and the smaller the area occupied by the gate driving circuit 13 in the non-display region 11 is, the more favorable the narrow frame of the display panel 1 'can be realized, so that the market competitiveness of the display panel 1' can be improved.

Since at least part of the gate driving circuit 13 may be located in the display region 10, when the output sub-circuit 1304 is located in the display region 10, referring to fig. 5, the first output signal terminal OUT1 and the second output signal terminal OUT2 in the output sub-circuit 1304 need to be coupled to gate lines, the pixel driving circuits 12 located in the same row are coupled to the same gate lines, and the gate lines are configured to transmit the first gate signal G1 and the second gate signal G2 to the pixel driving circuits 12. Specifically, the first gate signal G1 and the second gate signal G2 may be transmitted through the gate lines.

Referring to fig. 2, at least one of the control signal lines 132 is located in a non-light-emitting region (a region where the light-emitting element D is located without the fill pattern is a light-emitting region, and a region surrounding the light-emitting region with the fill pattern is a non-light-emitting region) in the display region 10, and is located in a region other than the region occupied by the pixel driving circuit 12.

The material of the control signal line 132 is, for example, a metal material, such as molybdenum (Mo), titanium (Ti), copper (Cu), silver (Ag), or aluminum (Al). The control signal line 132 may be a metal stacked structure, which is not limited herein.

The display region 10 includes a light-emitting region and a non-light-emitting region, for example, the light-emitting element D is further provided in a region other than the region occupied by the pixel driving circuit 12, but since the region occupied by the light-emitting element D is the light-emitting region and the material of the control signal line 132 is a metal material, the transmittance with respect to light is low, and therefore the control signal line 132 cannot be provided in the region occupied by the light-emitting element D but can be provided only in the region other than the region occupied by the pixel driving circuit 12 and the light-emitting element D in the display region 10.

When at least one control signal line 132 of the plurality of control signal lines 132 is located in the display region 10, the area occupied by the gate driving circuit 13 in the non-display region 11 is further reduced, thereby further realizing the narrow frame of the display panel 1'.

In some embodiments, referring to fig. 2, at least one of the plurality of control signal lines 132 is located between two adjacent columns of the sub-pixels P, one for each row. For example, the arrangement order of the sub-pixels P may be the same.

It will be understood by those skilled in the art that the arrangement order is the same on the premise that the arrangement rule is the same, for example, for each row of sub-pixels P, the mth sub-pixel in each row may constitute the M-th column of sub-pixels P in a left-to-right or right-to-left order, where M is a positive integer and is less than or equal to the total number of sub-pixels P in each row.

When the plurality of sub-pixels P are distributed in a matrix form of a plurality of rows and a plurality of columns, the control signal line 132 is arranged between two adjacent columns of sub-pixels P, so that the control signal line 132 with a straight line in a top view structure can be formed, and the manufacturing difficulty of the control signal line 132 can be reduced.

Fig. 7 is a schematic structural diagram of a display panel provided according to an embodiment of the present disclosure.

As shown in fig. 7, in order to increase the pixel aperture ratio, a plurality of sub-pixels P may be used as one pixel unit. For example, the pixel driving circuits 12 of the sub-pixels P of the pixel unit are collectively disposed in the non-emitting region for the pixel unit, which contributes to reducing the size of the non-emitting region and increasing the pixel aperture ratio.

The gate driving circuit 13 and the pixel driving circuit 12 are coupled through gate lines G1, G2, and the gate driving circuit 13 is configured to provide a gate driving signal to the coupled pixel driving circuit 12 through the coupled gate lines G1, G2. Here, light emitted from the light-emitting element D is emitted through the base substrate, and an orthogonal projection of a portion of the gate driver circuit 13 located in the non-light-emitting region on the base substrate does not overlap with an orthogonal projection of the light-emitting element D and the pixel driver circuit 12 on the base substrate.

For example, when the arrangement of the sub-pixels P in the display panel 1' adopts the standard RGB mode, each pixel includes three sub-pixels P, and the light emitting colors of the three sub-pixels P are three primary colors, such as red, green and blue, in sequence. The RGB-mode arrangement is the most standard arrangement, and divides a square pixel into three equal parts, each of which is given a different color, thus facilitating the fabrication of the sub-pixel P.

For another example, when the arrangement of the sub-pixels P in the display panel 1' adopts an RGB Pentile (RGB arrangement) mode, each pixel unit 100 includes 4 sub-pixels P, the light emission colors of the four sub-pixels P are, for example, red, green, blue, and green in sequence, and the area of the sub-pixels whose light emission colors are red and blue is larger than that of the sub-pixels P whose light emission color is green.

The Pentile arrangement mainly reduces the number of the sub-pixels P by sharing the sub-pixels P with adjacent pixels, thereby achieving the effect of simulating high resolution with low resolution. The great benefit of the Pentile arrangement is that the permeability is increased, and the same brightness requires less power consumption, so that the endurance of the display panel 1 'can be improved, and the cost of the display panel 1' can be significantly reduced.

In the same row of sub-pixels P, the arrangement order of the emission colors of the sub-pixels P in each pixel unit 100 is the same, for example, among the four sub-pixels P included in each pixel unit 100 in the first row, the first sub-pixel P with the emission color of red, the second sub-pixel P with the emission color of green, the third sub-pixel P with the emission color of blue, and the fourth sub-pixel P with the emission color of green are also included, that is, in the pixel unit 100, the arrangement order of the emission colors of the sub-pixels P is red, green, blue, and green; while the light emitting colors of the sub-pixels P in the pixel units 100 in different rows are different, for example, in the sub-pixels P in the second row, the light emitting colors of the sub-pixels P in each pixel unit 100 are arranged in the order of blue, green, red and green.

Each pixel unit 100 includes three sub-pixels P, the first is a sub-pixel P with a red light emitting color, the second is a sub-pixel P with a green light emitting color, and the third is a sub-pixel P with a blue light emitting color, and the arrangement order of the light emitting colors of the sub-pixels P in the pixel units 100 in different rows is the same, that is, the sub-pixels P are all red, green, and blue. In this structure, one pixel unit 100 is one pixel.

When the plurality of sub-pixels P are divided into a plurality of pixel units 100, the gate driving circuit 13 may be disposed between adjacent two pixel units 100. For example, at least one first thin film transistor group 131 is located between two adjacent pixel units 100.

When the plurality of sub-pixels P are divided into the plurality of pixel units 100 and the first thin film transistor group 131 is disposed between two adjacent pixels P, since the pitch between two adjacent sub-pixels P is small in each pixel unit 100; on one hand, when one pixel unit 100 can be used as one pixel, adjacent pixels can be relatively independently displayed, thereby being beneficial to ensuring the display effect of the display panel 1'; on the other hand, since the number of the pixel units 100 is smaller than the number of the sub-pixels P, when the first thin film transistor group 131 is disposed in the vacant region between two adjacent pixel units 100, it is advantageous to increase the pixel density (PPI) of the display panel 1'.

In some embodiments, two adjacent gate lines of the gate lines G1 and G2 are located between two adjacent rows of pixel units 100. This helps to reduce the average distance between the gate lines and the gate driving circuit.

In some embodiments, the sub-pixels P in two adjacent rows are adjacent to the light emitting elements D in different rows, or the pixel driving circuits 12 in different rows are adjacent to each other. This helps reduce the area of the non-light emitting region.

Referring to fig. 7 and 10, the gate lines G1, G2 are distributed along the row direction of the plurality of sub-pixels P. In addition, the gate lines G1 and G2 may also extend in the column direction of the plurality of subpixels P. The pixel driving circuit 12, the capacitor Cst, and the light emitting element D for each sub-pixel P may be sequentially arranged. The gate lines G1 and G2 may be coupled to the first thin film transistor group 131 in the gate driving circuit. For example, the gate lines G1 and G2 and the first thin film transistor group 131 may be connected by a connection line. The first thin film transistor group 131 may also be coupled to one or more control signal lines. For example, the control signal line may be the same as the clock signal line CLKE shown in FIG. 4 ₁ Etc. are connected.

In some embodiments, a gate driving circuit 13 is disposed in each pixel unit 100.

For example, the gate driving circuit 13 includes a plurality of shift registers 130, the shift registers 130 include a plurality of thin film transistors, the plurality of thin film transistors are divided into a plurality of thin film transistor groups 131, and at least one thin film transistor group 131 is located in the non-light emitting region and is distributed between two adjacent rows of the sub-pixels P.

In some embodiments, since one gate driving circuit 13 may correspond to a plurality of pixel units 100, as long as the gate driving circuit 13 is disposed in some of the pixel units 100, the requirement of the display panel 1' for the gate driving circuit 13 can be satisfied. For example, the gate driving circuit 13 is disposed in a part of the pixel units 100, and the gate driving circuit 13 is not disposed in the remaining part of the pixel units 100.

The non-light emitting region where the gate driver circuit 13 is not provided may be in a non-pattern state at the same layer as each part of the gate driver circuit 13. In addition, dummy patterns (dummy patterns) may be provided in these regions in the non-Pattern state.

The "same layer" above refers to a layer structure formed by forming a film layer for forming a specific pattern by the same film formation process and then performing a patterning process once using the same mask plate. Depending on the specific pattern, the same patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and the specific patterns may be at different heights or have different thicknesses.

In some embodiments, the non-light-emitting region without the gate driving circuit 13 is not provided, and the electrostatic discharge pattern 14 may be provided at the same layer as the components of the gate driving circuit 13, so as to improve the space utilization of the non-light-emitting region on the display panel. The ends of the electrostatic discharge pattern 14 are coupled together by a wire 140.

It should be noted that, in the scheme of only disposing the gate driving circuit in a part of the display units, the output transistors in the gate driving circuit designed in this way may be concentrated in some display units in the display area, and if too many output transistors are disposed, the area where the display unit is disposed may generate heat seriously, which may result in pixel burnout. In addition, too few output transistors in the Gate driving circuit may result in insufficient Gate fall, resulting in insufficient charging rate and poor panel uniformity.

Fig. 8 isbase:Sub>A schematic cross-sectional view ofbase:Sub>A display panel inbase:Sub>A direction ofbase:Sub>A-base:Sub>A' in fig. 7.

As shown in fig. 8, the display panel includes a substrate base plate 17 and a buffer layer 19 on the substrate base plate 17. The substrate 17 includes, but is not limited to, an inorganic transparent material substrate, an organic transparent material substrate, and the like. The buffer layer 19 may be formed of a transparent dielectric material.

An active layer 1211 disposed on the buffer layer 19. The active layer 1211 may be formed of a semiconductor material and configured to constitute a source electrode and a drain electrode of the thin film transistor. The source and drain may be connected to an external circuit through the conductive member.

A gate dielectric layer 1212 is disposed over the active layer 1211. The materials of the gate dielectric layer 1212 include, but are not limited to: silicon dioxide, silicon oxynitride, silicon nitride, hafnium oxide, and the like.

A gate 1213 is disposed over the gate dielectric layer 1212. The gate 1213 may be made of a conductive material. For example, the gate electrode 1213 may be a metal material such as a tungsten material, an aluminum material, or a copper material.

An interlayer insulating layer 1214 is disposed around the active layer 1211, the gate dielectric layer 1212, and the gate electrode 1213. Materials of the interlayer insulating layer 1214 include, but are not limited to: silicon dioxide, silicon oxynitride, organic transparent materials, and the like.

Conductive lines 1215 are provided above the interlayer insulating layer 1214 and may be used to electrically connect to the source and drain electrodes for inputting and outputting signals to and from the source and drain electrodes. In the related art, the conductive line denoted by 1215 may not be present at the cross section in thebase:Sub>A-base:Sub>A' direction; or the region of the layer where the conductive line labeled 1215 is located is not patterned; or the conductive line, reference numeral 1215, exists as a dummy pattern and is not used for transmitting signals. As can be seen in fig. 8, the conductive line, reference 1215, is electrically isolated from the gate 1213.

In some embodiments, the at least one gate line G1, G2 includes a first conductive portion located between adjacent sub-pixels, the first conductive portion includes a first conductive sub-layer and a second conductive sub-layer, the first conductive sub-layer and the second conductive sub-layer are located at different layers, an insulating layer is included between the first conductive sub-layer and the second conductive sub-layer, and the first conductive sub-layer and the second conductive sub-layer are coupled by an insulating layer via hole.

Specifically, a metal layer may be formed over the substrate base plate 17 (between any layers or over a surface over the substrate), and a second conductive sub-layer may be formed on the metal layer by a process such as photolithography and etching. The second conductive sublayer can be electrically connected with the first conductive sublayer through the via hole to reduce the resistance of the first conductive sublayer.

In some embodiments, in order to avoid the need for adding a metal layer or adding a patterning process due to the addition of the second conductive sublayer, an unused region may be patterned in the existing conductive layer to form the second conductive sublayer, and the second conductive sublayer may be electrically connected to the first conductive sublayer through the via hole. This makes it possible to form the second conductive sub-layer at the same time as the other patterns are formed.

In certain embodiments, the second conductive sublayer is disposed in at least one of: a layer where the shading pattern is located, a layer where the gate electrode is located, a layer where the source and drain electrodes are located, or a layer where the cathode electrode is located. The layer where the shading pattern is located, the layer where the grid electrode is located, and the layer where the source electrode and the drain electrode are located can be metal material layers, and the layer where the cathode electrode is located can be a transparent conducting layer. It should be noted that the second conductive sub-layer for the first conductive sub-layer may also be disposed on the layer where the first conductive sub-layer is located, for example, by patterning to simultaneously form the first conductive sub-layer and the second conductive sub-layer connected to the first conductive sub-layer.

Fig. 9 is another schematic cross-sectional view taken along the directionbase:Sub>A-base:Sub>A' in fig. 7 according to an embodiment of the present disclosure.

As shown in fig. 9, using the conductive line electrically connected to the first conductive sublayer 1213 as the second conductive sublayer 1215 reduces the resistance of the first conductive sublayer 1213 while improving space utilization. For example, the second conductive sublayer 1215 is electrically connected to the first conductive sublayer 1213 through a third via K1, and the third via K1 is disposed on the interlayer dielectric layer 1214. The first conductive portion has at least two layers of metal wirings in the non-light emitting region, effectively reducing the resistance of the first conductive sublayer 1213.

Referring to fig. 7 and 9, the orthographic projections of the first conductive sublayer 1213 and the second conductive sublayer 1215 on the substrate overlap each other and extend in the same direction. Therefore, the size of the GOA output transistor TFT can be reduced, the Gate falling edge can be ensured, and the uniformity of the panel is improved. For example, the projection of the second conductive sublayer 1215 onto the substrate partially overlaps the projection of the first conductive sublayer 1213 onto the substrate. The second conductive sublayer 1215 may extend in the row direction and/or the column direction. One first conductive sublayer 1213 and one second conductive sublayer 1215 may be connected through one or more vias, such as 1 via, 2 vias, 3 vias, etc., and the number of vias may be determined according to the length of the second conductive sublayer, which is not limited herein.

In some embodiments, the plurality of gate lines includes a first gate line G1 and a second gate line G2 adjacent to each other. The first transistor T1 in each pixel driving circuit 12 includes a source drain 1215, an active layer 1211. The plurality of pixel drive circuits 12 include: a first pixel driving circuit coupled to one Data line Data and the first gate line G1, and a second pixel driving circuit coupled to the Data line Data and the second gate line G2. The source region is a region coupled to the source/drain after the semiconductor in the active layer 1211 is conducted (e.g., by doping).

In fig. 9, the pixel drive circuit 12 includes a thin film transistor. The thin film transistor includes a source and a drain, and the second conductive sublayer 1215 is located at the same layer as the source and the drain.

In some embodiments, the display panel 1' further comprises: the power supply lines ELVDD on the substrate 17 are disposed between at least a part of the adjacent two columns of the sub-pixels P or disposed at the sides of the edge columns of the sub-pixels P, each of the power supply lines ELVDD is used to supply power to the light emitting elements D of a given number of columns, and the power supply lines ELVDD is coupled to the pixel driving circuit 12. For example, the specified number may be 1 column, 2 columns, 3 columns, 4 columns, or the like.

In some embodiments, the display panel 1' further comprises: the Data signal line Data, the power supply line ELVDD, and the Data signal line Data are coupled to the pixel driving circuit 12. The power supply line ELVDD and the Data signal line Data are configured to supply a power supply voltage signal and a Data signal to the pixel driving circuit 12, respectively. The plurality of thin film transistors are distributed between adjacent sub-pixels in the same column of sub-pixels.

Specifically, the display panel 1' further includes: a Data signal line Data coupled to the pixel driving circuit 12 and configured to supply a Data signal to the pixel driving circuit 12; the plurality of first thin film transistor groups 131 includes at least the first thin film transistor group 131 as an output transistor in the shift register 130. A first distance between the first thin film transistor group as an output transistor and the power supply line is smaller than a second distance between the first thin film transistor group as an output transistor and the data signal line.

In some embodiments, the display panel 1 includes: a power supply voltage signal line ELVDD, and a Data signal line Data. Referring to fig. 7, the power supply voltage signal line ELVDD is configured to supply the power supply voltage signal ELVDD to the power supply voltage signal terminal ELVDD in the pixel driving circuit 12, and the Data signal line Data is configured to supply the Data signal Data to the Data signal terminal Data in the pixel driving circuit 12. The plurality of first thin film transistor groups 131 are located in the display region and distributed between adjacent sub-pixels P of the same row of sub-pixels P, and the plurality of first thin film transistor groups 131 at least include the first thin film transistor group 131 serving as an output transistor in the shift register 130.

Illustratively, referring to fig. 10 and 11, each first thin film transistor group 131 is located between adjacent display units 100 in the same row of display units 100, and each first thin film transistor group 131 includes one first thin film transistor, which is an output transistor, such as, for example, the twenty-fourth transistor M24 in the nth stage shift register 130.

The first thin film transistor group 131, which is an output transistor, is spaced apart from the power supply voltage signal line ELVDD less than the Data signal line Data. For example, referring to fig. 7 and 11, the spacing between the twenty-fourth transistor M24, which is an output transistor, and the power supply voltage signal line ELVDD on the right side thereof is smaller than the spacing between the twenty-fourth transistor M24 and the Data signal line Data on the right side thereof, so that the twenty-fourth transistor M24 can be made to operate more stably as less interference from the Data signal line Data is received. It should be noted that, when comparing the pitches between the twenty-fourth transistor M24 and the power supply voltage signal line ELVDD and the Data signal line Data, the first twenty-fourth transistor M24 is used in the left-to-right direction, and therefore, the power supply voltage signal line ELVDD and the Data signal line Data are both located on the right side of the twenty-fourth transistor M24, and the structure of the right side of the other twenty-fourth transistor M24 is the same as that of the first twenty-fourth transistor M24.

For example, the display panel 1' further includes: a power line ELVDD and a Data signal line Data. Referring to fig. 2, the power supply line ELVDD is configured to supply a power supply voltage signal ELVDD to a power supply voltage signal terminal ELVDD in the pixel driving circuit 12, and the Data signal line Data is configured to supply a Data signal Data to a Data signal terminal Data in the pixel driving circuit 12. The plurality of first thin film transistor groups 131 are located in the display region and distributed between adjacent sub-pixels P of the same row of sub-pixels P, and the plurality of first thin film transistor groups 131 at least include the first thin film transistor group 131 serving as an output transistor in the shift register 130.

Referring to fig. 7 and 10, each of the first tft groups 131 is located between adjacent pixel units 100 in the same row of pixel units 100, and each of the first tft groups 131 includes a first tft 1310, where the first tft 1310 is an output transistor, and the output transistor is, for example, a twenty-fourth transistor in the nth stage shift register 130.

In some embodiments, the plurality of first thin film transistor groups 131 functioning as output transistors are connected in parallel. A plurality of vias are disposed in the display panel 1', and the vias are used for coupling the respective film layers in the display panel 1'. Referring to fig. 11, the positions of the thin film transistor T1, the thin film transistor T2, the thin film transistor T3, the storage capacitor Cst, the power line ELVDD, the Data signal line Data, the sensing signal line Sense, and the gate line G1/G2 in the pixel driving circuit 12 are as shown in the figure, the pixel driving circuit 12 receives the first gate signal G1 and the second gate signal G2 from the gate line G1/G2, and the gate line G1/G2 is coupled to the twenty-fourth transistor, so that a signal is transmitted from the gate driving circuit 13 to the pixel driving circuit 12.

Fig. 11 is a schematic structural diagram of a display panel according to another embodiment of the present disclosure. Fig. 12 is a schematic cross-sectional structure view taken along the direction B-B' in fig. 11. Fig. 13 is a schematic sectional structure view for the direction C-C' in fig. 11. Fig. 14 is a schematic sectional view of the structure of fig. 11 taken along the direction D-D'.

Referring to fig. 11, 12 and 13, the thin film transistor includes an active layer. Accordingly, the display panel further includes: and a light shielding pattern 14, an orthogonal projection of the light shielding pattern 14 on the base substrate 17 overlapping an orthogonal projection of the pattern of the active layer 1211 on the base substrate. The light-shielding pattern 14 is configured to reduce negative bias of threshold voltage of the thin film transistor due to light irradiation, and the light-shielding pattern can make electrical connection of electrical signals more stable, thereby improving device stability.

In addition, the display panel 1' may further include a second conductive portion 18, and an orthogonal projection of the second conductive portion 18 on the substrate base 17 and an orthogonal projection of the pattern of the active layer 1211 on the substrate base are separated from each other.

Since the control signal line 133 is coupled to the clock signal line CLKE1, the signal transmitted by the control signal line 133 is the clock signal CLKE1. It should be noted that, in fig. 11, some components, such as the light emitting element D in a part of the sub-pixels P, are omitted in fig. 11 for making the structure diagram clearer, but it can be understood by those skilled in the art that the light emitting element D in the part of the sub-pixels P in the figure is not illustrated, and it is not considered that the light emitting element D is not present in the sub-pixels P, and the figure is only for embodying some components that need to be described with emphasis, and therefore, all components in the display panel 1' are not embodied.

In some embodiments, the display panel 1' may further include: and a storage capacitor electrode C1 disposed corresponding to the active layer 1211 of the first transistor T1, the storage capacitor electrode C1 being one electrode of the storage capacitor Cst. In the case where the light emitted from the driver exits from the substrate 17 side, the storage capacitor electrode C1 is a transparent pattern, and there is an overlap between the orthographic projection of the storage capacitor electrode C1 on the substrate 17 and the orthographic projection of the driver on the substrate 17. At this time, one electrode is opposed to the driving member. The capacitance can be increased while increasing the aperture ratio as much as possible.

The second conductive portion 18 may be disposed on a side of the storage capacitor electrode C1 close to the substrate base plate 17, and directly contact the storage capacitor electrode C1. It is possible to reduce the impedance of the storage capacitor electrode C1 while achieving light shielding.

The same meaning of the same layer as above is used here, and the description thereof is omitted. For example, as shown in fig. 9, the storage capacitor electrode C1 and the active layer pattern 10 may be formed through a one-time patterning process using the same mask.

In some embodiments, the second conductive portion 18 is electrically connected to the third conductive portion (the main portion of the power line ELVDD, refer to the power line ELVDD disposed in the column direction in fig. 7). The second conductive part 18 may be disposed on the layer where the light shielding pattern 14 is located. This makes it possible to form the auxiliary line or the patch line of the power supply line ELVDD by means of the layer on which the light shielding pattern is formed. The second conductive portion 18 may be formed of an opaque conductive material. For example, the second conductive portion 18 may be formed of a metal material.

In some embodiments, the plurality of gate lines G1, G2 extend in a first direction, the power line ELVDD extends in a second direction, the first direction and the second direction are different, and the power line includes a second conductive portion, an orthographic projection of the second conductive portion on the substrate at least partially overlapping an orthographic projection of at least one of the plurality of gate lines on the substrate 17. For example, the first direction may be a row direction, such as an X direction. The second direction may be a column direction, such as the Y direction.

Specifically, the orthographic projection of the second conductive part 18 on the substrate base 17 at least partially overlaps with the orthographic projection of the second conductive sub-layer 1215 on the substrate base 17, and the orthographic projection of the second conductive part 18 on the substrate base 17 is isolated from the orthographic projection of the first conductive sub-layer 1213 on the substrate base. This can reduce signal crosstalk by the second conductive part.

For example, the orthographic projection of the third conductive part on the substrate base and the orthographic projection of the first conductive sublayer 1213 on the substrate base 17 are isolated from each other, and the orthographic projection of the third conductive part on the substrate base 17 and the orthographic projection of the second conductive sublayer 1215 on the substrate base are isolated from each other.

In some embodiments, the thin film transistor includes a gate electrode; the light-shielding pattern 14 is provided on the substrate 17 in a region corresponding to the active layer 1211 of the thin film transistor of the pixel drive circuit 12. Accordingly, the insulating layer includes: a buffer layer 19 provided on a side of the light-shielding pattern 14 away from the base substrate 17; and an interlayer dielectric layer 1214 provided on the buffer layer 19 on the side away from the base substrate 17.

Specifically, the second conductive part 18 is located on the layer where the light shielding pattern 14 is located, and the second conductive part is electrically connected to the third conductive part through a first via hole K2 and a second via hole K3, where the first via hole K2 is disposed on the buffer layer 19, and the second via hole K3 is disposed on the interlayer dielectric layer 1214.

The third conductive part is electrically connected to the second conductive part 18 through a first via hole K2 and a second via hole K3, wherein the first via hole K2 is disposed on the buffer layer 19, and the second via hole K3 is disposed on the interlayer dielectric layer 1214. For example, the third conductive portion may be disposed on the layer where the source and drain are located, and in order to electrically connect the third conductive portion and the second conductive portion, referring to fig. 14, a first via K2 may be disposed on the buffer layer 19, and a second via K3 may be disposed on the interlayer dielectric layer 1214. The projections of the first via hole K2 and the second via hole K3 on the substrate base plate may overlap or be isolated from each other (connected by a connection line). For example, an orthographic projection of the first via K2 on the substrate base and an orthographic projection of the second via K3 on the substrate base overlap. Since the light-shielding pattern 14 and the storage capacitor electrode C1 are formed in the same process, and accordingly, the second conductive portion 18 may be formed in the same process, a layer of the same material as the storage capacitor electrode C1 may remain on the second conductive portion 18.

In this embodiment, the SD layer is formed on the gate lines G1 and G2, which are formed by double metal layers, at the overlapping position with the power line ELVDD, and the power line ELVDD is replaced with a layer on which the light-shielding pattern is formed. Referring to fig. 12, this allows two insulating layers, i.e., an interlayer insulating layer (e.g., an interlayer dielectric layer (ILD)) 1214 and a buffer layer 19, between the gate lines G1 and G2 (corresponding to the second conductive sub-layer 123 and the power line ELVDD (corresponding to the light shielding pattern 14) at the overlap region, thereby increasing the capacitance distance in the overlap region and reducing the overlap capacitance.

In some embodiments, the display panel 1' further comprises: a light emitting element disposed in the light emitting region, the light emitting element comprising: an anode; the anode is coupled to the drain of the thin film transistor of the pixel driving circuit.

Referring to fig. 11 and 13, light emitted from the light emitting element D exits through the base substrate; the orthographic projection of the portion of the gate driver circuit 13 located in the display region 10 on the substrate does not overlap the orthographic projection of the light emitting element D and the pixel driver circuit 12 on the substrate.

When light emitted by the light emitting element D is emitted through the base substrate, the display panel 1 'is a bottom emission type display panel, and when an orthographic projection of a portion of the gate driving circuit 13 located in the display region 10 on the base substrate does not overlap with an orthographic projection of the light emitting element D and the pixel driving circuit 12 on the base substrate, the gate driving circuit 13 does not affect the aperture ratio of the display panel 1', a region where the gate driving circuit 13 is located is a non-light emitting region, and a region where the light emitting element D is located is a light emitting region.

In some embodiments, the orthographic projection of the non-light-emitting region where the pixel driving circuit 12 is located on the substrate does not overlap with the orthographic projection of the light-emitting region where the light-emitting element D is located on the substrate.

In some embodiments, referring to fig. 7 and 11, the orthographic projection of the area where the pixel driving circuit 12 is located on the substrate and the orthographic projection of the light emitting area where the light emitting element D is located on the substrate partially overlap. The materials of the two plates of the storage capacitor Cst in the pixel driving circuit 12 are, for example, transparent conductive materials, and the material of one of the two plates is the same as that of the first active layer 1211, i.e., indium gallium zinc oxide, and at this time, the plate and the first active layer 1211 can be fabricated at the same time, so that the number of masks can be reduced; the other plate is made of, for example, indium Tin Oxide (ITO), and in this case, an orthographic projection of the storage capacitor Cst on the substrate overlaps an orthographic projection of the light emitting element D on the substrate. In this structure, since the two plates of the storage capacitor Cst are transparent, the storage capacitor Cst can be located in the light emitting region, and the region of the pixel driving circuit 12 except for the storage capacitor Cst is located in the non-light emitting region. When the storage capacitor Cst is positioned at the light emitting region, the aperture ratio of the display panel 1' may be increased.

For example, each pixel unit 100 includes 4 sub-pixels P, and the arrangement order of the light emitting colors of the 4 sub-pixels P is, for example, red, green, blue and any one color, such as green, blue or White (White, W). When white is matched, the arrangement of the sub-pixels P with such a structure can improve the brightness of the pixel unit 100, thereby being beneficial to improving the display effect of the display panel 1'.

In some embodiments, the light emitted from the light emitting device D exits toward the side away from the substrate. The display panel 1' having such a structure is a top emission type display panel. In the display panel of the top emission type, the orthographic projection of the portion of the gate driver circuit 13 located in the display region 10 on the base substrate may overlap with the orthographic projection of the light emitting element D on the base substrate without affecting the aperture ratio of the display panel 1'.

As shown in fig. 13, regardless of whether the display panel 1 'is a bottom emission type display panel or a top emission type display panel, the structure of the display panel 1' is as shown in fig. 11, and the display panel 1 'includes a light shielding layer 18, a buffer layer 19, a thin film transistor 1210, an anode 110 and a planarization layer 111 disposed on a substrate 17 along the thickness direction of the display panel 1', wherein the thin film transistor 1210 is a driving transistor T3 in the pixel driving circuit 12, and the thin film transistor 1210 includes, for example, a first active layer 1211, a first gate insulating layer 1212, a first gate electrode 1213, an interlayer insulating layer 1214, an SD layer (source drain layer) 1215 and a passivation layer 1216.

The material of the light-shielding layer 18 is, for example, a light-shielding material, such as a black matrix material or a metal material, for example, in fig. 11, so that the light-shielding layer 18 needs to be coupled with the SD layer to form a structure similar to an upper and lower dual channel, thereby improving the electrical performance of the thin film transistor 1210. The light-shielding layer 18 is configured to prevent light incident from the substrate base 17 from affecting the first active layer 1211, thereby affecting the performance of the thin film transistor 1210.

The material of the first active layer 1211 is, for example, metal oxide, polysilicon, or amorphous silicon; the metal oxide is, for example, indium gallium zinc oxide.

The material of the first gate electrode 1213 is, for example, a metal material such as molybdenum, titanium, copper, silver, or aluminum, and the structure thereof is, for example, a single-layer structure.

In certain embodiments, the cathode comprises a material that is a transparent conductive material and the anode comprises a material that is a metallic material. The metal material may be a material with high conductivity and high reflectivity, so that when the light emitted from the light emitting layer 141 is directed to the substrate side, the light is reflected by the anode to the top of the pixel unit 100 to emit light, which is helpful to improve the light emitting efficiency and reduce the energy consumption.

The SD layer 1215 is made of a metal material, for example, a metal material such as molybdenum, titanium, copper, silver, or aluminum, and may have a single-layer structure or a stacked-layer structure. For example, the conductive layer of the source and drain material may be Ti/Al/Ti, etc.

Specifically, the gate material may include a metal material, such as Mo, al, cu, etc., and alloys thereof. The source and drain electrode material may include a metal material, such as Mo, al, cu, and the like, and alloys thereof. The semiconductor material constituting the active layer may include, for example, amorphous silicon, polycrystalline silicon, an oxide semiconductor, or the like, and the oxide semiconductor material may include, for example, IGZO (indium gallium zinc oxide), znO (zinc oxide), or the like.

The buffer layer 19, the first gate insulating layer 1212, the interlayer insulating layer 1214, and the passivation layer 1216 are each made of, for example, an inorganic insulating material, such as at least one of silicon oxide (SiOx) and silicon nitride (SiN).

The material of the anode 110 is, for example, a conductive material, for example, including ITO, and may have a single-layer structure or a stacked-layer structure.

The material of the planarization layer 111 is, for example, an organic material such as Polyimide (PI), and the planarization layer 111 performs planarization.

Since the at least one first thin film transistor group 131 included in the scan driving circuit 13 of the display panel 1 'in the embodiment of the present disclosure is disposed in the display area 10, it is beneficial to the display panel 1' in the embodiment of the present disclosure to realize a narrow frame or even no frame. Because the space of the GIA (the GIA is that the gate driving circuit is arranged in the display area, and the narrow edges of the left frame and the right frame of the display screen are realized by not occupying the frames) area is larger, the gate lines G1 and G2 can be wired in a double-layer way in the GIA area, so that the Resistance (RC) of the first conductive sublayer can be reduced. The line of power cord ELVDD is wider (e.g., the line of the third conductive part is wider), so that the overlapping of the third conductive part and the first conductive sub-layer can generate a larger capacitance, the overlapping part of the gate lines G1 and G2 of the double-layer metal and the extending direction of the power cord ELVDD is walked, the SD layer is walked by the second conductive sub-layer, and meanwhile, the power cord ELVDD is replaced by a layer where the shading pattern is located, so that two insulating layers are arranged in the middle: the interlayer dielectric layer ILD and the BUFFER layer BUFFER increase the capacitance distance of the overlapping region and reduce the overlapping capacitance.

Another aspect of the present disclosure provides a display device. The display device comprises a display panel 1' as shown above.

As shown in fig. 15, the display apparatus 1500 includes one or more display panels 1' as described above. The display panel 1' includes a display region and a non-display region having a small width, thereby implementing a display device having a narrow bezel.

Additionally, the display device 1500 may include one or more processors 1510 and a computer-readable storage medium 1520.

In particular, processor 1510 may include, for example, a general purpose microprocessor, an instruction set processor and/or related chip sets and/or a special purpose microprocessor (e.g., an Application Specific Integrated Circuit (ASIC)), among others. The processor 1510 may also include onboard memory for caching purposes.

The computer-readable storage medium 1520, for example, may be a non-volatile computer-readable storage medium, specific examples including, but not limited to: magnetic storage devices, such as magnetic tape or Hard Disk Drives (HDDs); optical storage devices, such as compact disks (CD-ROMs); memory such as Random Access Memory (RAM) or flash memory, etc.

The computer-readable storage medium 1520 may include a program 1521, which program 1521 may include code/computer-executable instructions that, when executed by the processor 1510, cause the processor 1510 to perform image display data processing. For example, in an example embodiment, code in program 1521 may include one or more program modules, including, for example, program module 1521A, program module 1521B, … ….

The display device may include any device or product having a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a Personal Digital Assistant (PDA), a Portable Multimedia Player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (e.g., a head-mounted device, an electronic apparel, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, or the like.

Although the present disclosure is described in connection with the accompanying drawings, the embodiments disclosed in the drawings are intended to be illustrative of the embodiments of the disclosure, and should not be construed as a limitation of the disclosure. The dimensional proportions in the drawings are merely illustrative and are not to be construed as limiting the disclosure.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can appreciate that the variations or substitutions within the technical scope of the present disclosure should be covered by the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A display panel, comprising:

a substrate base plate;

a plurality of pixel units disposed on the substrate, the plurality of pixel units being arranged in an array in a row direction and a column direction on a display area of the substrate, each pixel unit including at least one sub-pixel including a light emitting element and a pixel driving circuit coupled to the light emitting element;

the gate driving circuit is arranged on the substrate and comprises a plurality of cascaded shift registers and a plurality of grid lines, wherein one shift register is coupled with a plurality of pixel driving circuits in at least one row of pixel units through at least one grid line, and the shift register is used for providing gate driving signals for the plurality of pixel driving circuits through at least one grid line; and

a power line on the substrate, the power line being between adjacent sub-pixels, the power line being for providing power signals to the sub-pixels,

wherein the shift register comprises a plurality of first thin film transistors, the plurality of first thin film transistors are divided into a plurality of first thin film transistor groups, at least one first thin film transistor group is positioned in the display area and distributed between at least part of adjacent sub-pixels in the same row of sub-pixels, the at least one gate line comprises a first conductive part positioned between the adjacent sub-pixels, the first conductive part comprises a first conductive sub-layer and a second conductive sub-layer, the first conductive sub-layer and the second conductive sub-layer are positioned on different layers, an insulating layer is arranged between the first conductive sub-layer and the second conductive sub-layer, and the first conductive sub-layer and the second conductive sub-layer are coupled through via holes of the insulating layer,

the plurality of gate lines extend along a first direction, the power line extends along a second direction, the first direction and the second direction are different, the power line comprises a second conductive part, the orthographic projection of the second conductive part on the substrate is at least partially overlapped with the orthographic projection of at least one gate line of the plurality of gate lines on the substrate,

the orthographic projection of the second conductive part on the substrate base plate is at least partially overlapped with the orthographic projection of the second conductive sub-layer on the substrate base plate, and the orthographic projection of the second conductive part on the substrate base plate is mutually isolated from the orthographic projection of the first conductive sub-layer on the substrate base plate.

2. The display panel of claim 1, wherein the power supply line further comprises a third conductive portion, the third conductive portion and the second conductive portion being on different layers.

3. The display panel of claim 2, wherein an orthographic projection of the third conductive portion on the substrate base plate is isolated from an orthographic projection of the first conductive sub-layer on the substrate base plate, and an orthographic projection of the third conductive portion on the substrate base plate is isolated from an orthographic projection of the second conductive sub-layer on the substrate base plate.

4. The display panel according to claim 1, wherein the pixel driving circuit comprises a thin film transistor; and

the thin film transistor comprises a source electrode and a drain electrode, and the second conductive sublayer and the source electrode and the drain electrode are located on the same layer.

5. The display panel according to claim 1, wherein the power supply line includes a second conductive portion and a third conductive portion; the thin film transistor includes a gate electrode;

the display panel further includes:

a light shielding pattern disposed on the substrate in a region corresponding to an active layer of a thin film transistor of the pixel driving circuit;

the insulating layer includes:

the buffer layer is arranged on one side of the shading pattern far away from the substrate base plate; and

and the interlayer dielectric layer is arranged on one side of the buffer layer far away from the substrate base plate.

6. The display panel according to claim 5, wherein the second conductive portion is located on a layer where the light shielding pattern is located, and the second conductive portion is electrically connected to the third conductive portion via a first via hole and a second via hole, wherein the first via hole is provided on the buffer layer, and the second via hole is provided on the interlayer dielectric layer.

7. The display panel of claim 6, wherein an orthographic projection of the first via on the substrate base plate and an orthographic projection of the second via on the substrate base plate overlap.

8. The display panel of claim 5, wherein the second conductive sublayer is electrically connected to the first conductive sublayer through a third via disposed on the interlevel dielectric layer.

9. The display panel of claim 6, wherein the sub-pixel comprises a light emitting element comprising an anode; and

the anode is coupled to a drain of a thin film transistor of the pixel driving circuit.

10. The display panel according to any one of claims 1 to 9, wherein orthographic projections of the first conductive sublayer and the second conductive sublayer on the base substrate overlap each other and extend in the same direction.

11. The display panel according to any one of claims 1 to 9, wherein the second conductive sublayer is provided in at least one of: a layer where the light-shielding pattern is located, a layer where the source and drain electrodes are located, or a layer where the cathode electrode is located.

12. The display panel according to any one of claims 1 to 9, further comprising:

a light shielding pattern disposed on the substrate in a region corresponding to an active layer of a thin film transistor of the pixel driving circuit; and

a storage capacitor electrode disposed on a side of the light shielding pattern away from the substrate;

wherein an orthographic projection of the light shielding pattern on the substrate base plate is at least partially overlapped with an orthographic projection of the storage capacitor electrode on the substrate base plate.

13. The display panel according to any one of claims 1 to 9, wherein light emitted from the light-emitting element is emitted through the base substrate;

the orthographic projection of the part of the gate drive circuit, which is positioned in the display area, on the substrate does not overlap with the orthographic projection of the light-emitting element and the pixel drive circuit on the substrate.

14. The display panel according to any one of claims 1 to 9, wherein the light emitting elements located in different rows or the pixel drive circuits located in different rows are adjacent in the sub-pixels of two adjacent rows.

15. The display panel according to any one of claims 1 to 9, further comprising: a data signal line coupled with the pixel driving circuit and configured to provide a data signal to the pixel driving circuit; the plurality of first thin film transistor groups at least comprise a first thin film transistor group which is used as an output transistor in the shift register; and

a first interval between the first thin film transistor group as an output transistor and the power supply line is smaller than a second interval between the first thin film transistor group as an output transistor and the data signal line.

16. A display device comprising the display panel according to any one of claims 1 to 15.