CN110706599B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN110706599B CN110706599B CN201911020711.4A CN201911020711A CN110706599B CN 110706599 B CN110706599 B CN 110706599B CN 201911020711 A CN201911020711 A CN 201911020711A CN 110706599 B CN110706599 B CN 110706599B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
Abstract
The invention discloses a display panel and a display device. The scanning driving circuit adopting a three-layer metal framework is designed in the display area, and the transistors in the scanning driving circuit are arranged among the rows of the pixel areas, so that the frame size of the display panel is reduced, the ultra-narrow frame or even no frame display effect can be realized, and the overlap of the power signal lines of the scanning driving circuit to the pixels is small, so that the aperture ratio of the display area is increased. In addition, the design of the scanning driving circuit is convenient for realizing the driving display of the special-shaped screen.
Description
Technical Field
The invention belongs to the technical field of display, and particularly relates to a display panel and a display device.
Background
With the continuous maturity of display technologies, the variety of display products is also diversified. In the prior art, a display panel is generally a rectangular screen, and includes a display area and a non-display area surrounding the display area, and a scan driving circuit, a data driving circuit, and the like are generally disposed in the non-display area of the display panel to avoid affecting the display of the display panel.
With the display area of the display panel becoming larger and smaller, the non-display area also becomes smaller and smaller, and the narrow frame design has become the mainstream development trend. Therefore, the process requirements are also increasing. Among them, the GOA (Gate Driver on Array) technology of the display area is one of the important technologies for realizing frameless display.
The existing mainstream GOA circuit is designed to design GOA areas on two sides of a display area, and the narrow frame effect is achieved by shrinking the area of the GOA areas. At present, the process of frameless display effect has certain technical defects, such as: although the GOA area is narrow (about 5mm), there still exists a certain frame area, and the GOA circuit design has many difficulties in the design of curved frames.
Therefore, how to realize a circuit design that does not affect the irregular screen while reducing the bezel is an important issue in the display technology.
Disclosure of Invention
Embodiments of the present invention provide a display panel, in which a scan driving circuit with a three-layer metal structure is designed in a display area, and transistors in the scan driving circuit are disposed between rows of a plurality of pixel areas, so as to reduce a frame size of the display panel, thereby achieving an ultra-narrow frame or even frameless display effect, and a power signal line of the scan driving circuit has a small overlap with pixels, so as to increase an aperture ratio of the display area. In addition, the design of the scanning driving circuit is convenient for realizing the driving display of the special-shaped screen.
According to an aspect of the present invention, there is provided a display panel including: a display area; the scanning driving circuit is arranged in the three-layer metal framework of the display area; and the plurality of gate lines and the plurality of data lines are insulated and crossed to define a plurality of pixel regions, wherein the plurality of pixel regions are positioned in the display region, and a plurality of transistors of the scanning driving circuit are arranged in the rows of the plurality of pixel regions.
Further, the three-layer metal architecture comprises: a first metal layer for forming the plurality of scan lines; the grid insulation layer is arranged on the first metal layer; an active layer disposed on the gate insulating layer; the second metal layer is used for forming the data lines and arranged on the active layer; the passivation layer is arranged on the second metal layer; and a third metal layer for forming a power signal line of the scan driving circuit, the third metal layer being disposed on the passivation layer.
Further, the third metal layer is conducted with the first metal layer through a first via hole, wherein the first via hole is sequentially formed in the passivation layer, the second metal layer, the active layer and the gate insulating layer.
Further, the third metal layer is conducted to the second metal layer through a second via hole, wherein the second via hole is disposed in the passivation layer.
Further, the plurality of transistors of the scan driving circuit include: a first transistor, a second transistor, a third transistor and a fourth transistor, wherein the first transistor, the second transistor, the third transistor and the fourth transistor are all located among the pixel region rows.
Further, a gate and a drain of the first transistor are electrically connected to a first scan line of the plurality of scan lines, and a source of the first transistor is electrically connected to a gate of the second transistor and a drain of the fourth transistor, respectively.
Further, a gate of the second transistor is electrically connected to a source of the first transistor, a drain of the second transistor is electrically connected to the power signal line, and a source of the second transistor is electrically connected to a second scan line of the plurality of scan lines and a drain of the third transistor, respectively.
Furthermore, a gate of the third transistor is electrically connected to a gate of the fourth transistor and a third scan line of the plurality of scan lines, a drain of the third transistor is electrically connected to a source of the second transistor and a second scan line of the plurality of scan lines, and a source of the third transistor is electrically connected to a source of the fourth transistor and a source signal line.
Further, a gate of the fourth transistor is electrically connected to the gate of the third transistor and a third scan line of the plurality of scan lines, a drain of the fourth transistor is electrically connected to the source of the first transistor and the gate of the second transistor, and a source of the fourth transistor is electrically connected to the source of the third transistor and a source signal line.
According to another aspect of the present invention, there is provided a display device comprising the display panel as described above.
According to the embodiment of the invention, the scanning driving circuit adopting a three-layer metal framework is designed in the display area, and the transistors in the scanning driving circuit are arranged among the rows of the pixel areas, so that the frame size of the display panel is reduced, and the ultra-narrow frame or even no frame display effect is realized. In addition, the design of the scanning driving circuit is convenient for realizing the driving display of the special-shaped screen.
Drawings
The technical solution and the advantages of the present invention will be apparent from the following detailed description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a three-layer metal structure according to an embodiment of the present invention.
Fig. 3 is a schematic layout structure of a scan driving circuit and a pixel region according to an embodiment of the invention.
Fig. 4 is a schematic structural diagram of a scan driving circuit according to an embodiment of the present invention.
Fig. 5 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," "third," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the objects so described are interchangeable under appropriate circumstances. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions.
In particular embodiments, the drawings discussed below and the embodiments used to describe the principles of the present disclosure are by way of illustration only and should not be construed to limit the scope of the present disclosure. Those skilled in the art will understand that the principles of the present invention may be implemented in any suitably arranged system. Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. Further, a terminal according to an exemplary embodiment will be described in detail with reference to the accompanying drawings. Like reference symbols in the various drawings indicate like elements.
The terminology used in the detailed description is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concepts. Unless the context clearly dictates otherwise, expressions used in the singular form encompass expressions in the plural form. In the present specification, it is to be understood that terms such as "comprising," "having," and "containing" are intended to specify the presence of stated features, integers, steps, acts, or combinations thereof, as taught in the present specification, and are not intended to preclude the presence or addition of one or more other features, integers, steps, acts, or combinations thereof. Like reference symbols in the various drawings indicate like elements.
As shown in fig. 1, an embodiment of the invention provides a display panel 1 (as denoted by reference numeral 1 in fig. 5), which includes a display area 10, a non-display area (not labeled in the figure) disposed around the display area 10, a Chip On Film (COF) and a scan driving circuit 20.
The scan driving circuit 20 is disposed in the display area 10, and compared with the prior art, due to the design, the size of the frame can be reduced, and ultra-narrow frame display or even frame-free display can be realized. How to dispose the scan driving circuit 20 in the three-layer metal structure 80 (as shown in fig. 2, reference numeral 80) in the display area 10 will be further described below.
As shown in fig. 2, an embodiment of the invention provides a three-layer metal structure 80, which includes a first metal layer 11, a gate insulating layer 12, an active layer 13, a second metal layer 14, a passivation layer 15, a third metal layer 16, a first via 17, and a second via 18.
The scan driving circuit 20 is located in the three-layer metal structure 80, and the three-layer metal structure 80 is located in the display area 10. That is, the scan driving circuit 20 is disposed in the three-layer metal structure 80 of the display region 10.
The first metal layer 11 is used to form a plurality of scan lines. The plurality of scan lines may include, but are not limited to, a first scan line, a second scan line, a third scan line, and a fourth scan line as described below.
The gate insulating layer 12 is disposed on the first metal layer 11. The gate insulating layer 12 plays an insulating role.
The active layer 13 is disposed on the gate insulating layer 12. The material of the active layer 13 includes, but is not limited to, at least one of amorphous silicon, indium gallium zinc oxide, and polysilicon.
The second metal layer 14 is provided on the active layer 13. The second metal layer 14 is used to form a plurality of data lines.
A passivation layer 15 is provided on the second metal layer 14. The passivation layer 15 serves to protect the metal layer from corrosion.
A third metal layer 16 is provided on the passivation layer 15. The third metal layer 16 is used to form a power signal line of the scan driving circuit 20.
The first via 17 is sequentially disposed in the passivation layer 15, the second metal layer 14, the active layer 13, and the gate insulating layer 12. The first via 17 is used to connect and conduct the first metal layer 11 and the third metal layer 16, as shown in fig. 2.
A second via 18 is provided in the passivation layer 15. The second via 18 is used to connect and conduct the second metal layer 13 and the third metal layer 16, as shown in fig. 2.
The three-layer metal structure 80 provided in the embodiment of the present invention enables the power signal line of the scan driving circuit 20 to be formed in the third metal layer 16, and avoids being formed in the first metal layer 11, so that the overlap of the power signal line of the scan driving circuit 20 to the pixel can be reduced, and the aperture ratio of the display area can be increased.
As shown in fig. 3, an embodiment of the invention provides a layout structure of a scan driving circuit and a pixel region, which includes a scan driving circuit 20, a gate line 30, a data line 40, and a pixel region 50.
The gate lines 30 and the data lines 40 are insulated and crossed to define a plurality of pixel regions 50, wherein the pixel regions 50 are located in the display region 10.
A plurality of transistors of the scan driving circuit 20 are provided between the rows of the plurality of pixel regions 50.
As shown in fig. 4, specifically, the plurality of transistors of the scan driving circuit 20 include: a first transistor 100, a second transistor 200, a third transistor 300, and a fourth transistor 100, wherein the first transistor 100, the second transistor 200, the third transistor 300, and the fourth transistor 400 are all located between the rows of the pixel regions 50. Thus, by this layout design, the aperture ratio of the display area 10 can be increased.
The gate and the drain of the first transistor 100 are electrically connected to a first scan line G (N-1) of the plurality of scan lines, and the source of the first transistor 100 is electrically connected to the gate of the second transistor 200 and the drain of the fourth transistor 400, respectively. In addition, the channel width of the first transistor may be 200 micrometers, and the channel length may be 5 micrometers, although the size is not limited thereto.
The gate of the second transistor 200 is electrically connected to the source of the first transistor 100, the drain of the second transistor 200 is electrically connected to a power signal line, the power signal line includes a CK signal line or an XCK signal line, and the source of the second transistor 200 is electrically connected to the second scanning line g (n) of the plurality of scanning lines and the drain of the third transistor 300, respectively. In addition, the channel width of the second transistor may be selected to be 2000 micrometers, and the channel length may be selected to be 5 micrometers, although the size is not limited thereto.
The gate of the third transistor 300 is electrically connected to the gate of the fourth transistor 400 and a third scan line G (N +1) among the scan lines, the drain of the third transistor 300 is electrically connected to the source of the second transistor 400 and a second scan line G (N) among the scan lines, and the source of the third transistor 300 is electrically connected to the source of the fourth transistor 400 and a source signal line VSS. In addition, the channel width of the third transistor may be 500 micrometers, and the channel length may be 5 micrometers, although the size is not limited thereto.
The gate of the fourth transistor 400 is electrically connected to the gate of the third transistor 300 and the third scan line G (N +1) among the plurality of scan lines, the drain of the fourth transistor 400 is electrically connected to the source of the first transistor 100 and the gate of the second transistor 200, and the source of the fourth transistor 400 is electrically connected to the source of the third transistor 300 and a source signal line VSS. In addition, the channel width of the fourth transistor may be 500 micrometers, and the channel length may be 5 micrometers, although the size is not limited thereto.
As shown in fig. 5, an embodiment of the present invention further provides a display device 2, including the display panel 1 described above. The display device 2 may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
The display panel and the display device provided by the embodiment of the present invention are described in detail above, and the principle and the embodiment of the present invention are explained herein by applying specific examples, and the description of the above embodiments is only used to help understanding the method and the core idea of the present invention; meanwhile, for those skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (9)
1. A display panel, comprising:
a display area;
the scanning driving circuit is arranged in the three-layer metal framework of the display area; and
the display panel comprises a plurality of scanning lines and a plurality of data lines, wherein the plurality of scanning lines and the plurality of data lines are insulated and crossed to define a plurality of pixel regions, the plurality of pixel regions are positioned in the display region, and a plurality of transistors of the scanning driving circuit are arranged among rows of the plurality of pixel regions;
the three-layer metal architecture comprises:
a first metal layer for forming the plurality of scan lines;
the grid insulation layer is arranged on the first metal layer;
an active layer disposed on the gate insulating layer;
the second metal layer is used for forming the data lines and arranged on the active layer;
the passivation layer is arranged on the second metal layer; and
and a third metal layer for forming a power signal line of the scan driving circuit, the third metal layer being disposed on the passivation layer.
2. The display panel according to claim 1, wherein the third metal layer is electrically connected to the first metal layer through a first via hole, and wherein the first via hole is sequentially formed in the passivation layer, the second metal layer, the active layer, and the gate insulating layer.
3. The display panel of claim 1, wherein the third metal layer is in conductive communication with the second metal layer through a second via, wherein the second via is disposed in the passivation layer.
4. The display panel according to claim 1, wherein the plurality of transistors of the scan driver circuit include: a first transistor, a second transistor, a third transistor and a fourth transistor, wherein the first transistor, the second transistor, the third transistor and the fourth transistor are all located among the pixel region rows.
5. The display panel according to claim 4, wherein a gate and a drain of the first transistor are electrically connected to a first scan line of the plurality of scan lines, and a source of the first transistor is electrically connected to a gate of the second transistor and a drain of the fourth transistor, respectively.
6. The display panel according to claim 4, wherein a gate of the second transistor is electrically connected to a source of the first transistor, a drain of the second transistor is electrically connected to the power signal line, and a source of the second transistor is electrically connected to a second scan line of the plurality of scan lines and a drain of the third transistor, respectively.
7. The display panel according to claim 4, wherein a gate of the third transistor is electrically connected to a gate of the fourth transistor and a third scan line of the plurality of scan lines, respectively, a drain of the third transistor is electrically connected to a source of the second transistor and a second scan line of the plurality of scan lines, respectively, and a source of the third transistor is electrically connected to a source of the fourth transistor and a source signal line, respectively.
8. The display panel according to claim 4, wherein a gate of the fourth transistor is electrically connected to a gate of the third transistor and a third scan line of the plurality of scan lines, respectively, a drain of the fourth transistor is electrically connected to a source of the first transistor and a gate of the second transistor, respectively, and a source of the fourth transistor is electrically connected to a source of the third transistor and a source signal line, respectively.
9. A display device comprising the display panel according to any one of claims 1 to 8.
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| CN201911020711.4A CN110706599B (en) | 2019-10-25 | 2019-10-25 | Display panel and display device |
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| CN201911020711.4A CN110706599B (en) | 2019-10-25 | 2019-10-25 | Display panel and display device |
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| CN110706599A CN110706599A (en) | 2020-01-17 |
| CN110706599B true CN110706599B (en) | 2022-01-25 |
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| CN113362770B (en) * | 2021-06-02 | 2022-10-28 | 合肥京东方卓印科技有限公司 | Display panel and display device |
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| JP4868934B2 (en) * | 2006-05-11 | 2012-02-01 | ルネサスエレクトロニクス株式会社 | Semiconductor memory device |
| JP5280671B2 (en) * | 2006-12-20 | 2013-09-04 | 富士フイルム株式会社 | Image detector and radiation detection system |
| CN102403320B (en) * | 2010-09-16 | 2015-05-20 | 上海天马微电子有限公司 | Array substrate, fabricating method for same and liquid crystal display panel |
| CN104538400B (en) * | 2014-12-16 | 2017-08-04 | 深圳市华星光电技术有限公司 | A kind of LTPS array base paltes |
| CN106483726B (en) * | 2016-12-21 | 2023-07-25 | 昆山龙腾光电股份有限公司 | Thin film transistor array substrate, manufacturing method and liquid crystal display panel |
| CN108305888B (en) * | 2017-01-12 | 2020-10-16 | 上海和辉光电股份有限公司 | Array substrate and display panel |
| CN106782340B (en) * | 2017-03-16 | 2018-09-07 | 深圳市华星光电技术有限公司 | A kind of pixel-driving circuit and OLED display |
| CN107134460B (en) * | 2017-04-11 | 2019-08-02 | 深圳市华星光电半导体显示技术有限公司 | Display device and its GOA circuit |
| CN109671748B (en) * | 2018-12-12 | 2020-06-16 | 武汉华星光电半导体显示技术有限公司 | Display panel and manufacturing method thereof |
| CN110211527A (en) * | 2019-05-10 | 2019-09-06 | 深圳市华星光电半导体显示技术有限公司 | Micro LED display panel and display device |
| CN110137084B (en) * | 2019-05-30 | 2022-07-29 | 京东方科技集团股份有限公司 | Thin film transistor, preparation method thereof, electronic device substrate and electronic device |
| CN110265409B (en) * | 2019-06-20 | 2021-07-23 | 武汉华星光电半导体显示技术有限公司 | TFT array substrate, preparation method thereof and display panel thereof |
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