CN113333306A - Sorting method and system for poor chip appearance - Google Patents

Abstract

The invention provides a sorting method and a sorting system for poor chip appearance, wherein the method comprises the following steps: detecting and identifying a chip with poor appearance, and printing a poor appearance calibration identification code on the chip with poor appearance; scanning each chip in real time in the chip transmission process, and determining whether a bad appearance calibration identification code exists on the chip; when the poor appearance calibration identification code is detected to exist in the chip, controlling the pushing device to push the chip with the poor appearance calibration identification code to a conveying area where the poor appearance chip of the chip conveying belt is located, and counting the pushing times of the first pushing device in the running direction on the chip conveying belt; and controlling a reverse pushing device to carry out recheck detection on the chips in the conveying area where the chips with poor appearances are located, and sorting the chips with poor appearance calibration identification codes in the conveying area where the chips with poor appearances are located after the compound detection is correct. The system comprises modules corresponding to the method steps.

Description

Sorting method and system for poor chip appearance

Technical Field

The invention provides a sorting method and system for poor chip appearance, and belongs to the technical field of chip detection.

Background

The bad appearance of the chip is detected in the production process, the chip with the bad appearance is not sorted under the normal condition, but the chip with the bad appearance is marked with symbols, but in the links of subsequent chip electrical property detection and the like, the chip with the bad appearance can still be subjected to the same detection treatment, so that the chip with the bad appearance cannot be effectively screened and filtered, the data statistics abnormity such as the chip performance and the like easily occurs in the subsequent chip production link, and the production and processing process causes the problem of the reduction of the production and processing efficiency because the chip with the bad appearance is also subjected to the processing treatment of each link.

Disclosure of Invention

The invention provides a sorting method and a sorting system for poor chip appearance, which are used for solving the problems that in the existing chip production and processing process, only chips with poor appearance are marked, but the subsequent chip processing links still need to correspondingly process the chips with poor appearance due to no sorting, so that the production data is redundant, and the chips with poor appearance cannot be effectively screened subsequently, and adopt the following technical scheme:

a sorting method for bad chip appearance is provided, a dividing line is arranged at the center of a chip conveyor belt in the longitudinal direction; the two sides of the dividing line are respectively a conveying area where the chips with poor appearances are positioned and a conveying area where the chips with good appearances are positioned; a plurality of pushing devices arranged along the chip conveying belt are arranged on one side of the conveying area where the chips with good appearance are located; a plurality of reverse pushing devices arranged along the chip conveying belt are arranged on one side of the conveying area where the chips with poor appearances are located, and the sorting method comprises the following steps:

detecting and identifying a chip with poor appearance, printing a poor appearance calibration identification code on the chip with poor appearance, and counting the frequency of printing the poor appearance calibration identification code;

scanning each chip in real time in the chip transmission process, and determining whether a bad appearance calibration identification code exists on the chip;

when the poor appearance calibration identification code is detected to exist in the chip, controlling a pushing device to push the chip with the poor appearance calibration identification code to a conveying area where the poor appearance chip of the chip conveying belt is located, and counting the pushing times of a first pushing device in the running direction on the chip conveying belt;

and controlling the reverse pushing device to carry out recheck detection on the chips in the conveying area where the chips with poor appearances are located, and sorting the chips with poor appearance calibration identification codes in the conveying area where the chips with poor appearances are located as far as possible after the composite detection is error-free.

Further, the method further comprises:

when a first pushing device in the running direction on the chip conveyor belt counts the pushing times, judging whether the pushing counting times of the first pushing device are consistent with the times of printing the bad appearance calibration identification codes or not;

and if the pushing counting number of the first pushing device is inconsistent with the counting number of the bad appearance calibration identification code printing times, performing problem elimination processing according to the quantity relation between the pushing counting number of the first pushing device and the counting number of the bad appearance calibration identification code printing times.

Further, performing problem elimination processing according to a quantity relationship between the pushing count number of the first pushing device and the number count of the bad appearance calibration identification codes, including:

if the pushing counting times of the first pushing device is smaller than the counting times of the bad appearance calibration identification code, acquiring a difference value between the current pushing counting times and the counting times of the bad appearance calibration identification code, and repeatedly identifying and pushing according to the difference value;

if the pushing counting times of the first pushing device is larger than the number counting of the bad appearance calibration identification codes, the chips pushed when the pushing counting times of the first pushing device is larger than the number counting of the bad appearance calibration identification codes are marked, the reverse pushing device is controlled to reversely push the chips which are sent to the conveying area where the bad appearance chips are located and correspond to the number counting of the times of the bad appearance calibration identification codes, to the conveying area where the good appearance chips are located, and the pushing counting times of the first pushing device is reduced by one.

Further, performing repeated identification push processing according to the difference value, including:

controlling the first pushing device to send the difference value to all pushing devices in the transmission sending direction of the subsequent conveying belt;

after the subsequent pushing devices receive the difference, the first pushing device immediately supplements the current pushing counting times to the times which are the same as the times of the bad appearance calibration identification code printing according to the number of the difference;

the subsequent pushing device carries out repeated scanning and identification on the chip, carries out supplementary pushing on the identified chip with the bad appearance calibration identification code, pushes the chip to a conveying area where the chip with bad appearance is located, and records the supplementary pushing times;

when the total supplementary pushing times of the subsequent pushing devices are the same as the difference value, stopping the operation of all the subsequent pushing devices;

and performing repeated identification push processing according to the difference value, further comprising:

the reverse pushing device carries out real-time scanning and identification on the chips additionally pushed by the subsequent pushing device;

if the reverse pushing device identifies that the chips additionally pushed by the subsequent pushing device do not have the bad appearance calibration identification codes, the chips without the bad appearance calibration identification codes are reversely pushed to the conveying area where the chips with good appearances are located; sending the supplementary pushing error information to the last three pushing devices in the subsequent lifting and sending devices;

when the last three pushing devices in the subsequent pushing devices receive the supplement error information for one time, the current supplement pushing times are subjected to subtraction processing for one time to obtain the recheck chip number, and recheck identification and supplement pushing of the chips are carried out according to the recheck chip number; and stopping pushing operation when other subsequent pushing devices except the last three pushing devices finish the current supplementary pushing to the number corresponding to the difference value.

Further, control the backstepping device and carry out rechecking detection to the chip in the conveying area where the bad chip of outward appearance is located, include:

controlling the reverse thrust device to monitor the chips in the conveying area where the appearance defective chips are located in real time to perform rechecking identification of the defective appearance calibration identification codes;

if the chips which are not marked with the bad appearance calibration identification codes are identified to be in the transmission area where the bad appearance chips are located, the chips which are not marked with the bad appearance calibration identification codes in the transmission area where the bad appearance chips are located are reversely pushed to the transmission area where the good appearance chips are located; sending the current reverse pushing times to subsequent pushing devices except the first pushing device in the running direction on the chip conveyor belt;

and the subsequent pushing device identifies the bad appearance calibration identification code of the chip on the chip conveyor belt again according to the reverse pushing times sent by the reverse pushing device, and pushes the identified chip with the bad appearance calibration identification code to the conveying area where the bad appearance chip is located.

A sorting system for bad chip appearance is provided, wherein a dividing line is arranged at the center of a chip conveyor belt in the longitudinal direction; the two sides of the dividing line are respectively a conveying area where the chips with poor appearances are positioned and a conveying area where the chips with good appearances are positioned; a plurality of pushing devices arranged along the chip conveying belt are arranged on one side of the conveying area where the chips with good appearance are located; bad chip place conveying area one side of outward appearance is equipped with a plurality of reverse thrust units that set up along the chip conveyer belt, the letter sorting system includes:

the bad detection module is used for detecting and identifying a chip with bad appearance, marking a bad appearance calibration identification code on the chip with bad appearance and counting the frequency of marking the bad appearance calibration identification code;

the scanning module is used for scanning each chip in real time in the chip transmission process and determining whether a bad appearance calibration identification code exists on the chip;

the pushing control module is used for controlling the pushing device to push the chip with the bad appearance calibration identification code to a conveying area of the chip conveyor belt where the bad appearance chip is located and counting the pushing times of the first pushing device in the running direction on the chip conveyor belt when the bad appearance calibration identification code is detected to exist in the chip;

and the reverse pushing and sorting control module is used for controlling the reverse pushing device to carry out rechecking detection on the chips in the conveying area where the chips with poor appearances are located, and sorting the chips with poor appearance calibration identification codes in the conveying area where the chips with poor appearances are located as far as possible after the composite detection is error-free.

Further, the system further comprises:

the counting and judging module is used for judging whether the pushing counting times of the first pushing device and the counting times of the bad appearance calibration identification code printing are consistent or not when the first pushing device in the running direction on the chip conveyor belt counts the pushing times;

and the elimination processing module is used for eliminating the problems according to the quantity relation between the pushing counting times of the first pushing device and the counting times of the bad appearance calibration identification code marking if the pushing counting times of the first pushing device are inconsistent with the counting times of the bad appearance calibration identification code marking.

Further, the exclusion processing module includes:

the processing module I is used for acquiring a difference value between the current push counting number and the number of times of printing the bad appearance calibration identification code if the push counting number of the first push device is smaller than the number of times of printing the bad appearance calibration identification code, and performing repeated identification push processing according to the difference value;

and the processing module II is used for marking the chips pushed when the pushing counting times of the first pushing device is greater than the times of printing the bad appearance calibration identification codes if the pushing counting times of the first pushing device is greater than the times of printing the bad appearance calibration identification codes, controlling the reverse pushing device to reversely push the chips which are sent to the conveying area where the bad appearance chips are located and correspond to the times of printing the bad appearance calibration identification codes in the current pushing counting times to the conveying area where the good appearance chips are located, and subtracting one from the pushing counting times of the first pushing device.

Further, the first processing module comprises:

the sending module is used for controlling the first pushing device to send the difference value to all pushing devices in the transmission sending direction of the subsequent conveyor belt;

the supplementing module is used for supplementing the current pushing counting times to the times which are the same as the times of the marking of the bad appearance calibration identification codes by the first pushing device according to the number of the difference values immediately after the subsequent pushing devices receive the difference values;

the re-identification module is used for the subsequent pushing device to repeatedly scan and identify the chip, additionally push the identified chip with the bad appearance calibration identification code to a transmission area where the chip with the bad appearance is located, and simultaneously record the times of the additional push;

the operation stopping module is used for stopping all the subsequent pushing devices from operating when the total supplementary pushing times of the subsequent pushing devices are the same as the difference value;

the first processing module further comprises:

the backward-pushing scanning module is used for the backward-pushing device to carry out real-time scanning and identification on the chips additionally pushed by the subsequent pushing device;

the backward-pushing control module is used for backward pushing the chips without the bad appearance calibration identification codes to a transmission area where the chips with good appearance are located if the backward-pushing device identifies that the chips which are additionally pushed by the subsequent pushing device do not have the bad appearance calibration identification codes; sending the supplementary pushing error information to the last three pushing devices in the subsequent lifting and sending devices;

the supplement rechecking module is used for carrying out once reduction processing on the current supplement pushing times when the last three pushing devices in the subsequent pushing devices receive the supplement error information once to obtain the rechecked chip number, and carrying out rechecking identification and supplement pushing on the chips according to the rechecked chip number; and stopping pushing operation when other subsequent pushing devices except the last three pushing devices finish the current supplementary pushing to the number corresponding to the difference value.

Further, the reverse pushing and sorting control module comprises:

the real-time monitoring module is used for controlling the backstepping device to monitor the chips in the conveying area where the appearance defective chips are located in real time to perform rechecking identification on the defective appearance calibration identification codes;

the information sending module is used for reversely pushing the chip which is not marked with the bad appearance calibration identification code in the transmission area where the bad appearance chip is located to the transmission area where the good appearance chip is located if the chip which is not marked with the bad appearance calibration identification code is identified to be in the transmission area where the bad appearance chip is located; sending the current reverse pushing times to subsequent pushing devices except the first pushing device in the running direction on the chip conveyor belt;

and the rechecking push control module is used for the subsequent push device to re-identify the bad appearance calibration identification code of the chip on the chip conveyor belt according to the number of the backward push times sent by the backward push device, and push the identified chip with the bad appearance calibration identification code to the conveying area where the bad appearance chip is located.

The invention has the beneficial effects that:

the sorting method and system for poor chip appearance provided by the invention can effectively and accurately screen and sort chips with poor appearance, effectively improve the screening accuracy and comprehensiveness of the chips with poor appearance, and effectively reduce the screening omission of the chips with poor appearance. Meanwhile, through the matching between the pushing device and the reverse pushing device, the error pushing condition of the chip can be further rechecked and corrected, and the screening accuracy of the chips with bad appearances is further improved. On the other hand, through the pushing counting statistics and the pushing times and the specific statistics of the chip pushing conditions in combination with the counting mode in the reverse pushing process, the sorting and the statistics of other chips which are tightly caught in the link can be not influenced under the condition that the accuracy of the specific screening condition statistics in the poor chip sorting process is effectively improved, the independent execution and the execution among the technologies and the statistics among the first pushing device, the subsequent pushing devices and the last three pushing devices for final rechecking can be realized, the mutual interference is avoided, and the screening processing process of other subsequent chips entering the link is not influenced while the rechecking correction is carried out.

Drawings

FIG. 1 is a flow chart of the method of the present invention;

FIG. 2 is a system block diagram of the system of the present invention;

FIG. 3 is a schematic view of the installation of the pushing device and the thrust reverser according to the present invention;

(1, chip conveyor belt; 2, pushing device; 3, reverse pushing device).

Detailed Description

The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.

The invention provides a sorting method for poor chip appearance.A dividing line is arranged at the center of a chip conveyor belt in the longitudinal direction; the two sides of the dividing line are respectively a conveying area where the chips with poor appearances are positioned and a conveying area where the chips with good appearances are positioned; a plurality of pushing devices arranged along the chip conveying belt are arranged on one side of the conveying area where the chips with good appearance are located; a plurality of reverse pushing devices arranged along the chip conveyor belt are arranged on one side of the conveying area where the chips with poor appearances are located, the specific flow is shown in figure 1, and the sorting method comprises the following steps:

s1, detecting and identifying a chip with poor appearance, printing a poor appearance calibration identification code on the chip with poor appearance, and counting the frequency of printing the poor appearance calibration identification code;

s2, scanning each chip in real time in the chip transmission process, and determining whether a bad appearance calibration identification code exists on the chip;

s3, when the chips are detected to have poor appearance calibration identification codes, controlling a pushing device to push the chips with the poor appearance calibration identification codes to a conveying area where the poor appearance chips of the chip conveying belt are located, and counting the pushing times of a first pushing device in the running direction on the chip conveying belt;

and S4, controlling the reverse thrust device to carry out recheck detection on the chips in the conveying area where the chips with poor appearances are located, and sorting the chips with poor appearance calibration identification codes in the conveying area where the chips with poor appearances are located as far as possible after the composite detection is error-free.

The working principle of the technical scheme is as follows: firstly, detecting and identifying a chip with poor appearance, printing a poor appearance calibration identification code on the chip with poor appearance, and counting the frequency of printing the poor appearance calibration identification code; then, scanning each chip in real time in the chip transmission process, and determining whether a bad appearance calibration identification code exists on the chip; then, when the poor appearance calibration identification code is detected to exist in the chip, controlling a pushing device to push the chip with the poor appearance calibration identification code to a conveying area where the poor appearance chip of the chip conveying belt is located, and counting the pushing times of a first pushing device in the running direction on the chip conveying belt; and finally, controlling the reverse pushing device to carry out recheck detection on the chips in the conveying area where the chips with poor appearances are located, and sorting the chips with poor appearance calibration identification codes in the conveying area where the chips with poor appearances are located as far as possible after the composite detection is error-free.

The effect of the above technical scheme is as follows: can effectively carry out accurate screening and letter sorting to the chip that has bad outward appearance, effectively improve the screening accuracy and the comprehensiveness of bad outward appearance chip, can effectively reduce bad outward appearance chip screening omission nature. Meanwhile, through the matching between the pushing device and the reverse pushing device, the error pushing condition of the chip can be further rechecked and corrected, and the screening accuracy of the chips with bad appearances is further improved. On the other hand, through the pushing counting statistics and the pushing times and the specific statistics of the chip pushing conditions in combination with the counting mode in the reverse pushing process, the sorting and the statistics of other chips which are tightly caught in the link can be not influenced under the condition that the accuracy of the specific screening condition statistics in the poor chip sorting process is effectively improved, the independent execution and the execution among the technologies and the statistics among the first pushing device, the subsequent pushing devices and the last three pushing devices for final rechecking can be realized, the mutual interference is avoided, and the screening processing process of other subsequent chips entering the link is not influenced while the rechecking correction is carried out.

In one embodiment of the present invention, the method further comprises:

step 1, when a first pushing device in the running direction on the chip conveyor belt counts the pushing times, judging whether the pushing counting times of the first pushing device are consistent with the counting times of the times of printing the bad appearance calibration identification codes or not;

and 2, if the pushing count number of the first pushing device is inconsistent with the number count of the bad appearance calibration identification codes, performing problem elimination processing according to the quantity relation between the pushing count number of the first pushing device and the number count of the bad appearance calibration identification codes.

The working principle of the technical scheme is as follows: firstly, when a first pushing device in the running direction on the chip conveyor belt counts the pushing times, judging whether the pushing counting times of the first pushing device is consistent with the counting times of the times of printing the bad appearance calibration identification codes or not; then, if the pushing count number of the first pushing device is inconsistent with the number count of the bad appearance calibration identification codes, problem elimination processing is performed according to the number relation between the pushing count number of the first pushing device and the number count of the bad appearance calibration identification codes.

The effect of the above technical scheme is as follows: can effectively carry out accurate screening and letter sorting to the chip that has bad outward appearance, effectively improve the screening accuracy and the comprehensiveness of bad outward appearance chip, can effectively reduce bad outward appearance chip screening omission nature. Meanwhile, through the matching between the pushing device and the reverse pushing device, the error pushing condition of the chip can be further rechecked and corrected, and the screening accuracy of the chips with bad appearances is further improved.

According to an embodiment of the present invention, the problem elimination processing according to a quantity relationship between the pushing count number of the first pushing device and the count number of the bad appearance calibration identification code marking, includes:

step 101, if the number of times of pushing counting of the first pushing device is less than the number of times of printing the bad appearance calibration identification code, acquiring a difference value between the number of times of pushing counting currently and the number of times of printing the bad appearance calibration identification code, and performing repeated identification pushing processing according to the difference value;

102, if the pushing count number of the first pushing device is greater than the number of times of printing the bad appearance calibration identification code, marking the chip pushed when the pushing count number of the first pushing device is greater than the number of times of printing the bad appearance calibration identification code, controlling the reverse pushing device to reversely push the chip which is sent to the transmission area where the bad appearance chip is located and corresponds to the number of times of printing the bad appearance calibration identification code to the transmission area where the good appearance chip is located, and subtracting the pushing count number of the first pushing device by one.

Wherein, the repeated identification and pushing processing is carried out according to the difference value, comprising the following steps:

step 1011, controlling the first pushing device to send the difference value to all pushing devices in the transmission and sending directions of the subsequent conveyor belts;

step 1012, after the subsequent pushing devices receive the difference, the first pushing device immediately supplements the current pushing count number to the number of times the same as the number of times of the bad appearance calibration identification code printing according to the number of the difference;

step 1013, the subsequent pushing device performs repeated scanning and identification on the chip, performs supplementary pushing on the identified chip with the bad appearance calibration identification code, pushes the chip to a transmission area where the chip with bad appearance is located, and records the supplementary pushing times;

step 1014, when the total supplementary pushing times of the subsequent pushing devices are the same as the difference value, stopping the operation of all the subsequent pushing devices;

and performing repeated identification push processing according to the difference value, further comprising:

step 1015, the backward pushing device performs real-time scanning and identification on the chips additionally pushed by the subsequent pushing device;

step 1016, if the reverse pushing device recognizes that the chips which are additionally pushed by the subsequent pushing device do not have the bad appearance calibration identification codes, the chips which do not have the bad appearance calibration identification codes are reversely pushed to the transmission area where the chips with good appearance are located; sending the supplementary pushing error information to the last three pushing devices in the subsequent lifting devices, wherein the last three pushing devices are used as the last rechecking pushing devices;

1017, when the last three pushing devices in the subsequent pushing devices receive the supplement error information, performing subtraction processing on the current supplement pushing times for one time to obtain the recheck chip number, and performing recheck identification and supplement pushing on the chips according to the recheck chip number; and stopping pushing operation when other subsequent pushing devices except the last three pushing devices finish the current supplementary pushing to the number corresponding to the difference value.

The effect of the above technical scheme is as follows: through the propelling movement count statistics and the specific statistics of the propelling movement number of times and the chip propelling movement condition of the counting mode of combining in the backstepping process, can effectively improve the condition of the specific screening condition statistics accuracy in the bad chip sorting process, do not influence the sorting and the statistics of other chips which are driven into the link tightly, can realize independent execution and go on between the technology and the statistics of the first propelling movement device, the follow-up propelling movement device and the last three propelling movement devices used for final rechecking, do not interfere with each other, guarantee that the screening processing process of other follow-up chips entering the link is not influenced when rechecking is corrected.

Meanwhile, the error troubleshooting efficiency and the correction efficiency can be effectively improved through the re-identification process, the correction independence of each link can be effectively improved through the independent correction and rechecking of the first pushing device, the subsequent pushing devices and the last three pushing devices, and the problems that correction logics are too complex and tedious, correction errors are generated, and the correction efficiency is reduced due to the fact that correction of each link is correlated are prevented.

In an embodiment of the present invention, in a large chip production line, the number of the pushing devices is often more than ten, and in this case, the last rechecking pushing device may be directly set as the last three pushing devices according to the number of the pushing devices, or the number of the last rechecking pushing devices may be determined by using the following formula according to the set number of the pushing devices of the actual chip production line:

L≤

L

wherein N represents the number of the last rechecked push devices; m represents the total number of pushing devices; INT [ 2 ]]Representing taking only values on integer bits; l is₁Representing the preset transmission distance length of the conveyor belt at the last rechecking detection stage; l represents a slave transfer distance length of a transfer belt for chip transfer; alpha represents a first quantity determination coefficient with the range of 1.1-1.8, preferably 1.5, and beta represents a second quantity determination coefficient with the range of 1.5-2.3, preferably 2.0.

The working principle and the effect of the technical scheme are as follows: the specific number of the last rechecking pushing devices is determined according to the actual installation situation of the pushing devices on the production line for chip production and processing, the specific number of the last rechecking pushing devices obtained through the formula can be matched with the actual situation of the production line, the reasonability of the number setting of the last rechecking pushing devices is improved, and under the condition that enough subsequent pushing devices for supplementing pushing are arranged between the first pushing device and the last rechecking pushing devices, the last rechecking pushing devices can be guaranteed to be enough to recheck the last chips. Meanwhile, the matching degree of the final rechecking stage and the actual production line can be further improved by the aid of the subsequent rechecking stage of the conveyor belt, and under the condition that sufficient supplementary pushing transportation distance and time are reserved for the subsequent pushing device of the middle section, sufficient rechecking distance and rechecking time can be provided for subsequent final core screening and rechecking, and accuracy of chip screening is further improved.

In an embodiment of the present invention, controlling the reverse-thrust device to perform recheck detection on the chip in the transfer area where the chip with poor appearance is located includes:

s401, controlling the reverse thrust device to monitor the chips in the transmission area where the appearance defective chips are located in real time to perform rechecking identification of the defective appearance calibration identification codes;

s402, if the chip which is not marked with the bad appearance calibration identification code is identified to be in the transmission area where the bad appearance chip is located, the chip which is not marked with the bad appearance calibration identification code and is in the transmission area where the bad appearance chip is located is reversely pushed to the transmission area where the good appearance chip is located; sending the current reverse pushing times to subsequent pushing devices except the first pushing device in the running direction on the chip conveyor belt;

and S403, the subsequent pushing device identifies the bad appearance calibration identification code of the chip on the chip conveyor belt again according to the reverse pushing times sent by the reverse pushing device, and pushes the identified chip with the bad appearance calibration identification code to a conveying area where the bad appearance chip is located.

The working principle of the technical scheme is as follows: firstly, controlling the reverse thrust device to monitor the chips in the conveying area where the appearance defective chips are located in real time to perform rechecking identification of the defective appearance calibration identification codes; then, if the chip which is not marked with the bad appearance calibration identification code is identified to be in the transmission area where the bad appearance chip is located, the chip which is not marked with the bad appearance calibration identification code and is in the transmission area where the bad appearance chip is located is reversely pushed to the transmission area where the good appearance chip is located; sending the current reverse pushing times to subsequent pushing devices except the first pushing device in the running direction on the chip conveyor belt; and finally, the subsequent pushing device identifies the bad appearance calibration identification code of the chip on the chip conveyor belt again according to the reverse pushing times sent by the reverse pushing device, and pushes the identified chip with the bad appearance calibration identification code to a conveying area where the bad appearance chip is located.

The effect of the above technical scheme is as follows: can effectively carry out accurate screening and letter sorting to the chip that has bad outward appearance, effectively improve the screening accuracy and the comprehensiveness of bad outward appearance chip, can effectively reduce bad outward appearance chip screening omission nature. Meanwhile, through the matching between the pushing device and the reverse pushing device, the error pushing condition of the chip can be further rechecked and corrected, and the screening accuracy of the chips with bad appearances is further improved.

In one embodiment of the invention, a sorting system for poor chip appearance is provided, wherein a dividing line is arranged at the center of a chip conveyor belt in the longitudinal direction; the two sides of the dividing line are respectively a conveying area where the chips with poor appearances are positioned and a conveying area where the chips with good appearances are positioned; a plurality of pushing devices arranged along the chip conveying belt are arranged on one side of the conveying area where the chips with good appearance are located; bad chip place conveying area one side of outward appearance is equipped with a plurality of reverse thrust unit that set up along the chip conveyer belt, as shown in fig. 2, letter sorting system includes:

the bad detection module is used for detecting and identifying a chip with bad appearance, marking a bad appearance calibration identification code on the chip with bad appearance and counting the frequency of marking the bad appearance calibration identification code;

the scanning module is used for scanning each chip in real time in the chip transmission process and determining whether a bad appearance calibration identification code exists on the chip;

the pushing control module is used for controlling the pushing device to push the chip with the bad appearance calibration identification code to a conveying area of the chip conveyor belt where the bad appearance chip is located and counting the pushing times of the first pushing device in the running direction on the chip conveyor belt when the bad appearance calibration identification code is detected to exist in the chip;

and the reverse pushing and sorting control module is used for controlling the reverse pushing device to carry out rechecking detection on the chips in the conveying area where the chips with poor appearances are located, and sorting the chips with poor appearance calibration identification codes in the conveying area where the chips with poor appearances are located as far as possible after the composite detection is error-free.

The working principle of the technical scheme is as follows: firstly, detecting and identifying a chip with poor appearance by using a poor detection module, printing a poor appearance calibration identification code on the chip with poor appearance, and counting the frequency of printing the poor appearance calibration identification code; then, scanning each chip in real time in the chip transmission process through a scanning module, and determining whether a bad appearance calibration identification code exists on the chip; then, when the pushing control module is adopted to detect that the bad appearance calibration identification code exists in the chip, the pushing device is controlled to push the chip with the bad appearance calibration identification code to a conveying area where the bad appearance chip of the chip conveying belt is located, and the pushing times of the first pushing device in the running direction on the chip conveying belt are counted; and finally, controlling the reverse pushing device to carry out rechecking detection on the chips in the conveying area where the chips with poor appearances are located through the reverse pushing and sorting control module, and sorting the chips with poor appearance calibration identification codes in the conveying area where the chips with poor appearances are located as far as possible after the composite detection is error-free.

The effect of the above technical scheme is as follows: can effectively carry out accurate screening and letter sorting to the chip that has bad outward appearance, effectively improve the screening accuracy and the comprehensiveness of bad outward appearance chip, can effectively reduce bad outward appearance chip screening omission nature. Meanwhile, through the matching between the pushing device and the reverse pushing device, the error pushing condition of the chip can be further rechecked and corrected, and the screening accuracy of the chips with bad appearances is further improved. On the other hand, through the pushing counting statistics and the pushing times and the specific statistics of the chip pushing conditions in combination with the counting mode in the reverse pushing process, the sorting and the statistics of other chips which are tightly caught in the link can be not influenced under the condition that the accuracy of the specific screening condition statistics in the poor chip sorting process is effectively improved, the independent execution and the execution among the technologies and the statistics among the first pushing device, the subsequent pushing devices and the last three pushing devices for final rechecking can be realized, the mutual interference is avoided, and the screening processing process of other subsequent chips entering the link is not influenced while the rechecking correction is carried out.

In one embodiment of the present invention, the system further comprises:

the counting and judging module is used for judging whether the pushing counting times of the first pushing device and the counting times of the bad appearance calibration identification code printing are consistent or not when the first pushing device in the running direction on the chip conveyor belt counts the pushing times;

and the elimination processing module is used for eliminating the problems according to the quantity relation between the pushing counting times of the first pushing device and the counting times of the bad appearance calibration identification code marking if the pushing counting times of the first pushing device are inconsistent with the counting times of the bad appearance calibration identification code marking.

The working principle of the technical scheme is as follows: firstly, when a first pushing device in the running direction of the chip conveyor belt counts the pushing times by using a counting judgment module, judging whether the pushing counting times of the first pushing device is consistent with the counting times of the times of printing the bad appearance calibration identification codes or not; then, if the pushing count number of the first pushing device is inconsistent with the number count of the bad appearance calibration identification code, a problem elimination processing module is adopted to carry out problem elimination processing according to the quantity relation between the pushing count number of the first pushing device and the number count of the bad appearance calibration identification code.

The effect of the above technical scheme is as follows: can effectively carry out accurate screening and letter sorting to the chip that has bad outward appearance, effectively improve the screening accuracy and the comprehensiveness of bad outward appearance chip, can effectively reduce bad outward appearance chip screening omission nature. Meanwhile, through the matching between the pushing device and the reverse pushing device, the error pushing condition of the chip can be further rechecked and corrected, and the screening accuracy of the chips with bad appearances is further improved.

In one embodiment of the present invention, the exclusion processing module includes:

the processing module I is used for acquiring a difference value between the current push counting number and the number of times of printing the bad appearance calibration identification code if the push counting number of the first push device is smaller than the number of times of printing the bad appearance calibration identification code, and performing repeated identification push processing according to the difference value;

and the processing module II is used for marking the chips pushed when the pushing counting times of the first pushing device is greater than the times of printing the bad appearance calibration identification codes if the pushing counting times of the first pushing device is greater than the times of printing the bad appearance calibration identification codes, controlling the reverse pushing device to reversely push the chips which are sent to the conveying area where the bad appearance chips are located and correspond to the times of printing the bad appearance calibration identification codes in the current pushing counting times to the conveying area where the good appearance chips are located, and subtracting one from the pushing counting times of the first pushing device.

Wherein, the first processing module comprises:

the sending module is used for controlling the first pushing device to send the difference value to all pushing devices in the transmission sending direction of the subsequent conveyor belt;

the supplementing module is used for supplementing the current pushing counting times to the times which are the same as the times of the marking of the bad appearance calibration identification codes by the first pushing device according to the number of the difference values immediately after the subsequent pushing devices receive the difference values;

the re-identification module is used for the subsequent pushing device to repeatedly scan and identify the chip, additionally push the identified chip with the bad appearance calibration identification code to a transmission area where the chip with the bad appearance is located, and simultaneously record the times of the additional push;

the operation stopping module is used for stopping all the subsequent pushing devices from operating when the total supplementary pushing times of the subsequent pushing devices are the same as the difference value;

the first processing module further comprises:

the backward-pushing scanning module is used for the backward-pushing device to carry out real-time scanning and identification on the chips additionally pushed by the subsequent pushing device;

the backward-pushing control module is used for backward pushing the chips without the bad appearance calibration identification codes to a transmission area where the chips with good appearance are located if the backward-pushing device identifies that the chips which are additionally pushed by the subsequent pushing device do not have the bad appearance calibration identification codes; sending the supplementary pushing error information to the last three pushing devices in the subsequent lifting and sending devices;

the supplement rechecking module is used for carrying out once reduction processing on the current supplement pushing times when the last three pushing devices in the subsequent pushing devices receive the supplement error information once to obtain the rechecked chip number, and carrying out rechecking identification and supplement pushing on the chips according to the rechecked chip number; and stopping pushing operation when other subsequent pushing devices except the last three pushing devices finish the current supplementary pushing to the number corresponding to the difference value.

The working principle of the technical scheme is as follows: the operation process of the elimination processing module comprises the following steps:

firstly, if the pushing counting times of the first pushing device is smaller than the counting times of marking the bad appearance calibration identification code, acquiring a difference value between the current pushing counting times and the counting times of marking the bad appearance calibration identification code by using a processing module I, and repeatedly identifying and pushing according to the difference value;

and then, if the pushing counting number of the first pushing device is greater than the number of times of printing the bad appearance calibration identification code, marking the chips pushed by the first pushing device when the pushing counting number of the first pushing device is greater than the number of times of printing the bad appearance calibration identification code, controlling the reverse pushing device to reversely push the chips which are sent to the conveying area where the chips with good appearance are located and correspond to the number of times of printing the bad appearance calibration identification code of the current pushing counting number to the conveying area where the chips with good appearance are located, and subtracting one from the pushing counting number of times of the first pushing device.

The operation process of the processing module I comprises the following steps:

firstly, a sending module controls the first pushing device to send the difference value to all pushing devices in the transmission sending direction of a subsequent conveyor belt;

then, after the difference is received by the subsequent pushing devices by adopting a supplementing module, the first pushing device immediately supplements the current pushing counting times to the times which are the same as the times of counting the bad appearance calibration identification codes according to the number of the difference;

then, a re-identification module is used for controlling a subsequent pushing device to repeatedly scan and identify the chip, the identified chip with the bad appearance calibration identification code is pushed supplementarily to a transmission area where the chip with the bad appearance is located, and the supplementary pushing times are recorded;

then, stopping the operation of all subsequent pushing devices by adopting an operation stopping module when the total supplementary pushing times of the subsequent pushing devices are the same as the difference value;

the operation process of the first processing module further comprises the following steps:

utilizing a reverse-push scanning module to control the reverse-push device to carry out real-time scanning and identification on the chips which are additionally pushed by the subsequent pushing device;

then, a reverse control module is adopted to reversely push the chips without the bad appearance calibration identification codes to a transmission area where the chips with good appearance are located if the reverse device identifies that the chips which are additionally pushed by the subsequent pushing device do not have the bad appearance calibration identification codes; sending the supplementary pushing error information to the last three pushing devices in the subsequent lifting and sending devices;

finally, the last three pushing devices in the subsequent pushing devices are controlled by the supplementary rechecking module to receive supplementary error information once, the current supplementary pushing times are subjected to subtraction processing once to obtain the number of rechecked chips, and rechecking identification and supplementary pushing of the chips are carried out according to the number of the rechecked chips; and stopping pushing operation when other subsequent pushing devices except the last three pushing devices finish the current supplementary pushing to the number corresponding to the difference value.

The effect of the above technical scheme is as follows: through the propelling movement count statistics and the specific statistics of the propelling movement number of times and the chip propelling movement condition of the counting mode of combining in the backstepping process, can effectively improve the condition of the specific screening condition statistics accuracy in the bad chip sorting process, do not influence the sorting and the statistics of other chips which are driven into the link tightly, can realize independent execution and go on between the technology and the statistics of the first propelling movement device, the follow-up propelling movement device and the last three propelling movement devices used for final rechecking, do not interfere with each other, guarantee that the screening processing process of other follow-up chips entering the link is not influenced when rechecking is corrected.

Meanwhile, the error troubleshooting efficiency and the correction efficiency can be effectively improved through the re-identification process, the correction independence of each link can be effectively improved through the independent correction and rechecking of the first pushing device, the subsequent pushing devices and the last three pushing devices, and the problems that correction logics are too complex and tedious, correction errors are generated, and the correction efficiency is reduced due to the fact that correction of each link is correlated are prevented.

In one embodiment of the present invention, the reverse pushing and sorting control module comprises:

the real-time monitoring module is used for controlling the backstepping device to monitor the chips in the conveying area where the appearance defective chips are located in real time to perform rechecking identification on the defective appearance calibration identification codes;

the information sending module is used for reversely pushing the chip which is not marked with the bad appearance calibration identification code in the transmission area where the bad appearance chip is located to the transmission area where the good appearance chip is located if the chip which is not marked with the bad appearance calibration identification code is identified to be in the transmission area where the bad appearance chip is located; sending the current reverse pushing times to subsequent pushing devices except the first pushing device in the running direction on the chip conveyor belt;

and the rechecking push control module is used for the subsequent push device to re-identify the bad appearance calibration identification code of the chip on the chip conveyor belt according to the number of the backward push times sent by the backward push device, and push the identified chip with the bad appearance calibration identification code to the conveying area where the bad appearance chip is located.

The working principle of the technical scheme is as follows: the operation process of the reverse pushing and sorting control module comprises the following steps:

firstly, controlling the backstepping device to monitor the chips in the transmission area where the appearance defective chips are located in real time through a real-time monitoring module to perform rechecking identification of the defective appearance calibration identification codes; then, if the information sending module identifies that the chip which is not marked with the bad appearance calibration identification code is in the transmission area where the bad appearance chip is located, the information sending module reversely pushes the chip which is not marked with the bad appearance calibration identification code in the transmission area where the bad appearance chip is located to the transmission area where the good appearance chip is located; sending the current reverse pushing times to subsequent pushing devices except the first pushing device in the running direction on the chip conveyor belt; and finally, the rechecking push control module is used for controlling the subsequent push device to re-identify the bad appearance calibration identification code of the chip on the chip conveyor belt according to the number of the backward push times sent by the backward push device, and pushing the identified chip with the bad appearance calibration identification code to a conveying area where the bad appearance chip is located.

The effect of the above technical scheme is as follows: can effectively carry out accurate screening and letter sorting to the chip that has bad outward appearance, effectively improve the screening accuracy and the comprehensiveness of bad outward appearance chip, can effectively reduce bad outward appearance chip screening omission nature. Meanwhile, through the matching between the pushing device and the reverse pushing device, the error pushing condition of the chip can be further rechecked and corrected, and the screening accuracy of the chips with bad appearances is further improved.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (10)

1. A sorting method for bad chip appearance is characterized in that a dividing line is arranged at the center of a chip conveyor belt in the longitudinal direction; the two sides of the dividing line are respectively a conveying area where the chips with poor appearances are positioned and a conveying area where the chips with good appearances are positioned; a plurality of pushing devices arranged along the chip conveying belt are arranged on one side of the conveying area where the chips with good appearance are located; a plurality of reverse pushing devices arranged along the chip conveying belt are arranged on one side of the conveying area where the chips with poor appearances are located, and the sorting method comprises the following steps:

detecting and identifying a chip with poor appearance, printing a poor appearance calibration identification code on the chip with poor appearance, and counting the frequency of printing the poor appearance calibration identification code;

scanning each chip in real time in the chip transmission process, and determining whether a bad appearance calibration identification code exists on the chip;

when the poor appearance calibration identification code is detected to exist in the chip, controlling a pushing device to push the chip with the poor appearance calibration identification code to a conveying area where the poor appearance chip of the chip conveying belt is located, and counting the pushing times of a first pushing device in the running direction on the chip conveying belt;

and controlling the reverse pushing device to carry out recheck detection on the chips in the conveying area where the chips with poor appearances are located, and sorting the chips with poor appearance calibration identification codes in the conveying area where the chips with poor appearances are located as far as possible after the composite detection is error-free.

2. The method of claim 1, further comprising:

when a first pushing device in the running direction on the chip conveyor belt counts the pushing times, judging whether the pushing counting times of the first pushing device are consistent with the times of printing the bad appearance calibration identification codes or not;

and if the pushing counting number of the first pushing device is inconsistent with the counting number of the bad appearance calibration identification code printing times, performing problem elimination processing according to the quantity relation between the pushing counting number of the first pushing device and the counting number of the bad appearance calibration identification code printing times.

3. The method according to claim 2, wherein performing problem elimination processing according to a quantity relationship between the pushing count number of the first pushing device and the count number of times of printing the bad appearance calibration identification code comprises:

if the pushing counting times of the first pushing device is smaller than the counting times of the bad appearance calibration identification code, acquiring a difference value between the current pushing counting times and the counting times of the bad appearance calibration identification code, and repeatedly identifying and pushing according to the difference value;

if the pushing counting times of the first pushing device is larger than the number counting of the bad appearance calibration identification codes, the chips pushed when the pushing counting times of the first pushing device is larger than the number counting of the bad appearance calibration identification codes are marked, the reverse pushing device is controlled to reversely push the chips which are sent to the conveying area where the bad appearance chips are located and correspond to the number counting of the times of the bad appearance calibration identification codes, to the conveying area where the good appearance chips are located, and the pushing counting times of the first pushing device is reduced by one.

4. The method of claim 3, wherein performing repeated recognition push processing according to the difference value comprises:

controlling the first pushing device to send the difference value to all pushing devices in the transmission sending direction of the subsequent conveying belt;

after the subsequent pushing devices receive the difference, the first pushing device immediately supplements the current pushing count number to the number of times the same as the number of times of the bad appearance calibration identification code printing according to the difference;

the subsequent pushing device carries out repeated scanning and identification on the chip, carries out supplementary pushing on the identified chip with the bad appearance calibration identification code, pushes the chip to a conveying area where the chip with bad appearance is located, and records the supplementary pushing times;

when the total supplementary pushing times of the subsequent pushing devices are the same as the difference value, stopping the operation of all the subsequent pushing devices;

and performing repeated identification push processing according to the difference value, further comprising:

the reverse pushing device carries out real-time scanning and identification on the chips additionally pushed by the subsequent pushing device;

if the reverse pushing device identifies that the chips additionally pushed by the subsequent pushing device do not have the bad appearance calibration identification codes, the chips without the bad appearance calibration identification codes are reversely pushed to the conveying area where the chips with good appearances are located; sending the supplementary pushing error information to the last three pushing devices in the subsequent lifting and sending devices;

when the last three pushing devices in the subsequent pushing devices receive the supplement error information for one time, the current supplement pushing times are subjected to subtraction processing for one time to obtain the recheck chip number, and recheck identification and supplement pushing of the chips are carried out according to the recheck chip number; and stopping pushing operation when other subsequent pushing devices except the last three pushing devices finish the current supplementary pushing to the number corresponding to the difference value.

5. The method of claim 1, wherein controlling the reverse-thrust device to perform recheck detection on the chips in the conveying area where the chips with poor appearance are located comprises:

controlling the reverse thrust device to monitor the chips in the conveying area where the appearance defective chips are located in real time to perform rechecking identification of the defective appearance calibration identification codes;

if the chips which are not marked with the bad appearance calibration identification codes are identified to be in the transmission area where the bad appearance chips are located, the chips which are not marked with the bad appearance calibration identification codes in the transmission area where the bad appearance chips are located are reversely pushed to the transmission area where the good appearance chips are located; sending the current reverse pushing times to subsequent pushing devices except the first pushing device in the running direction on the chip conveyor belt;

and the subsequent pushing device identifies the bad appearance calibration identification code of the chip on the chip conveyor belt again according to the reverse pushing times sent by the reverse pushing device, and pushes the identified chip with the bad appearance calibration identification code to the conveying area where the bad appearance chip is located.

6. A sorting system for bad chip appearance is characterized in that a dividing line is arranged at the center of a chip conveyor belt in the longitudinal direction; the two sides of the dividing line are respectively a conveying area where the chips with poor appearances are positioned and a conveying area where the chips with good appearances are positioned; a plurality of pushing devices arranged along the chip conveying belt are arranged on one side of the conveying area where the chips with good appearance are located; bad chip place conveying area one side of outward appearance is equipped with a plurality of reverse thrust units that set up along the chip conveyer belt, the letter sorting system includes:

the bad detection module is used for detecting and identifying a chip with bad appearance, marking a bad appearance calibration identification code on the chip with bad appearance and counting the frequency of marking the bad appearance calibration identification code;

the scanning module is used for scanning each chip in real time in the chip transmission process and determining whether a bad appearance calibration identification code exists on the chip;

the pushing control module is used for controlling the pushing device to push the chip with the bad appearance calibration identification code to a conveying area of the chip conveyor belt where the bad appearance chip is located and counting the pushing times of the first pushing device in the running direction on the chip conveyor belt when the bad appearance calibration identification code is detected to exist in the chip;

and the reverse pushing and sorting control module is used for controlling the reverse pushing device to carry out rechecking detection on the chips in the conveying area where the chips with poor appearances are located, and sorting the chips with poor appearance calibration identification codes in the conveying area where the chips with poor appearances are located as far as possible after the composite detection is error-free.

7. The system of claim 6, further comprising:

the counting and judging module is used for judging whether the pushing counting times of the first pushing device and the counting times of the bad appearance calibration identification code printing are consistent or not when the first pushing device in the running direction on the chip conveyor belt counts the pushing times;

and the elimination processing module is used for eliminating the problems according to the quantity relation between the pushing counting times of the first pushing device and the counting times of the bad appearance calibration identification code marking if the pushing counting times of the first pushing device are inconsistent with the counting times of the bad appearance calibration identification code marking.

8. The system of claim 7, wherein the exclusion processing module comprises:

the processing module I is used for acquiring a difference value between the current push counting number and the number of times of printing the bad appearance calibration identification code if the push counting number of the first push device is smaller than the number of times of printing the bad appearance calibration identification code, and performing repeated identification push processing according to the difference value;

and the processing module II is used for marking the chips pushed when the pushing counting times of the first pushing device is greater than the times of printing the bad appearance calibration identification codes if the pushing counting times of the first pushing device is greater than the times of printing the bad appearance calibration identification codes, controlling the reverse pushing device to reversely push the chips which are sent to the conveying area where the bad appearance chips are located and correspond to the times of printing the bad appearance calibration identification codes in the current pushing counting times to the conveying area where the good appearance chips are located, and subtracting one from the pushing counting times of the first pushing device.

9. The system of claim 8, wherein the first processing module comprises:

the sending module is used for controlling the first pushing device to send the difference value to all pushing devices in the transmission sending direction of the subsequent conveyor belt;

the supplementing module is used for supplementing the current pushing counting times to the times which are the same as the times of the marking of the bad appearance calibration identification codes by the first pushing device immediately according to the difference after the subsequent pushing devices receive the difference;

the re-identification module is used for the subsequent pushing device to repeatedly scan and identify the chip, additionally push the identified chip with the bad appearance calibration identification code to a transmission area where the chip with the bad appearance is located, and simultaneously record the times of the additional push;

the operation stopping module is used for stopping all the subsequent pushing devices from operating when the total supplementary pushing times of the subsequent pushing devices are the same as the difference value;

the first processing module further comprises:

the backward-pushing scanning module is used for the backward-pushing device to carry out real-time scanning and identification on the chips additionally pushed by the subsequent pushing device;

the backward-pushing control module is used for backward pushing the chips without the bad appearance calibration identification codes to a transmission area where the chips with good appearance are located if the backward-pushing device identifies that the chips which are additionally pushed by the subsequent pushing device do not have the bad appearance calibration identification codes; sending the supplementary pushing error information to the last three pushing devices in the subsequent lifting and sending devices;

the supplement rechecking module is used for carrying out once reduction processing on the current supplement pushing times when the last three pushing devices in the subsequent pushing devices receive the supplement error information once to obtain the rechecked chip number, and carrying out rechecking identification and supplement pushing on the chips according to the rechecked chip number; and stopping pushing operation when other subsequent pushing devices except the last three pushing devices finish the current supplementary pushing to the number corresponding to the difference value.

10. The system of claim 6, wherein the back-push and sort control module comprises:

the real-time monitoring module is used for controlling the backstepping device to monitor the chips in the conveying area where the appearance defective chips are located in real time to perform rechecking identification on the defective appearance calibration identification codes;

the information sending module is used for reversely pushing the chip which is not marked with the bad appearance calibration identification code in the transmission area where the bad appearance chip is located to the transmission area where the good appearance chip is located if the chip which is not marked with the bad appearance calibration identification code is identified to be in the transmission area where the bad appearance chip is located; sending the current reverse pushing times to subsequent pushing devices except the first pushing device in the running direction on the chip conveyor belt;

and the rechecking push control module is used for the subsequent push device to re-identify the bad appearance calibration identification code of the chip on the chip conveyor belt according to the number of the backward push times sent by the backward push device, and push the identified chip with the bad appearance calibration identification code to the conveying area where the bad appearance chip is located.

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