CN113327889A - Contact hole manufacturing method of NAND flash memory device - Google Patents
Contact hole manufacturing method of NAND flash memory device Download PDFInfo
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- CN113327889A CN113327889A CN202110593161.6A CN202110593161A CN113327889A CN 113327889 A CN113327889 A CN 113327889A CN 202110593161 A CN202110593161 A CN 202110593161A CN 113327889 A CN113327889 A CN 113327889A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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Abstract
The invention provides a method for manufacturing a contact hole of a NAND flash memory device, which comprises the following steps: forming a gate structure and an air gap on a substrate; depositing a first interlayer dielectric layer on the substrate; carrying out chemical mechanical polishing on the first interlayer dielectric layer, and polishing the upper surface of the first interlayer dielectric layer to be flat; depositing a subsequent interlayer dielectric layer on the substrate; forming a contact hole on the substrate. The manufacturing method of the contact hole of the NAND flash memory device enables the first interlayer dielectric layer to be kept horizontal and further enables the subsequent interlayer dielectric layers to be kept horizontal, thereby ensuring that the etching direction of the contact hole and the interlayer dielectric layers of different layers form the same contact angle in the contact hole forming process, further ensuring the size of a contact hole process window and improving the reliability of the device.
Description
Technical Field
The invention relates to the field of integrated circuit manufacturing, in particular to a method for manufacturing a contact hole of a NAND flash memory device.
Background
The NAND flash memory is a nonvolatile memory, is very suitable for storing data due to its advantages of large capacity, fast erasing speed, low cost, and the like, and is widely used in the fields of consumption, automobiles, industrial electronics, and the like.
NAND memory arrays are typically made up of blocks, each block including a number of word lines, contact holes, and metal interconnect lines. With the development of science and technology, the process window of the contact hole process is smaller and smaller, referring to fig. 1, fig. 1 is a schematic diagram of a device in a contact hole manufacturing method of a conventional nand flash memory device, and the contact hole manufacturing method of the conventional nand flash memory device generally includes the following steps:
s1, forming a gate structure and an air gap on a substrate;
s2, depositing interlayer media of each layer, and carrying out chemical mechanical grinding on the finally deposited interlayer media;
s3, forming a contact hole on the substrate;
then the next layer of intermetallic medium deposition is carried out. However, in the process of forming the contact hole, referring to fig. 1, because the height of the front layer device is different, each layer of dielectric is not horizontal, referring to fig. 2, the etching direction of the contact hole forms different contact angles with the dielectric layers with different heights, which causes a significant difference in etching amount even if the contact hole is exposed and developed with only a very small horizontal direction shift during etching, so that the process window of the contact hole is very small, which is a great challenge to reliability.
Therefore, how to improve the contact hole manufacturing method of the existing nand flash memory device so as to avoid too small process window of the subsequent contact hole due to the step formed in the interlayer dielectric deposition process after the front-stage device is completed, thereby ensuring the reliability of the subsequent process is a problem to be solved urgently at present.
Disclosure of Invention
The invention aims to provide a method for manufacturing a contact hole of a NAND flash memory device, which can avoid too small a subsequent contact hole process window caused by the step formed in the interlayer medium deposition process after a front-stage device is finished, and further ensure the reliability of the subsequent process.
In order to achieve the above object, the present invention provides a method for fabricating a contact hole of a nand type flash memory device, comprising:
s1, forming a gate structure and an air gap on a substrate;
s2, depositing a first interlayer dielectric layer on the substrate;
s3, carrying out chemical mechanical polishing on the first interlayer dielectric layer, and polishing the upper surface of the first interlayer dielectric layer to be flat;
s4, depositing a subsequent interlayer dielectric layer on the substrate;
and S5, forming a contact hole on the substrate.
Optionally, the step of forming a contact hole on the substrate includes:
forming a patterned photoresist on the substrate, wherein the patterned photoresist exposes the position of the contact hole;
etching the substrate and cleaning;
depositing a bonding layer on the substrate, and depositing metal tungsten on the substrate.
Optionally, the subsequent interlayer dielectric layer includes a second interlayer dielectric layer and a third interlayer dielectric layer, the second interlayer dielectric layer is silicon nitride, and the third interlayer dielectric layer is silicon oxide.
Optionally, in the etching process, a boundary between the first interlayer dielectric layer and the second interlayer dielectric layer and a boundary between the second interlayer dielectric layer and the third interlayer dielectric layer are used as stop layers under different etching conditions.
Optionally, the bonding layer is titanium nitride.
Optionally, the first interlayer dielectric layer is silicon oxide.
Optionally, in S2, the method further includes performing a heat treatment on the substrate.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
according to the contact hole manufacturing method of the NAND flash memory device, the first interlayer dielectric layer can be kept horizontal by chemically and mechanically grinding the first interlayer dielectric layer, so that the subsequent interlayer dielectric layers can be kept horizontal, the same contact angle between the etching direction of the contact hole and the interlayer dielectric layers of different layers is ensured in the contact hole forming process, the size of a contact hole process window is ensured, and the reliability of the device is improved.
Drawings
FIGS. 1-2 are schematic diagrams of a contact hole structure of a conventional NAND flash memory device;
fig. 3 is a flowchart of a method of fabricating a contact hole of a nand type flash memory device according to the present invention;
FIGS. 4 to 8 are schematic device structures illustrating the contact hole fabricating method of the NAND flash memory device according to the present invention.
Wherein the reference numerals of the drawings are as follows:
11-a gate; 12-air gap; 13-a first interlayer dielectric layer; 14-a second interlayer dielectric layer; 15-a third interlayer dielectric layer; 16-contact holes.
Detailed Description
In order to make the objects, advantages and features of the present invention clearer, the following will explain the method for forming the contact hole of the nand flash memory device in detail with reference to fig. 3 to 8. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
An embodiment of the present invention provides a method for manufacturing a contact hole of a nand-type flash memory device, and referring to fig. 3, fig. 3 is a flowchart of a method for manufacturing a contact hole of a nand-type flash memory device according to an embodiment of the present invention, the method for manufacturing a contact hole of a nand-type flash memory device including:
s1: forming a gate structure and an air gap on a substrate;
s2: depositing a first interlayer dielectric layer on the substrate;
s3: carrying out chemical mechanical polishing on the first interlayer dielectric layer, and polishing the upper surface of the first interlayer dielectric layer to be flat;
s4: depositing a subsequent interlayer dielectric layer on the substrate;
s5: forming a contact hole on the substrate.
The method for fabricating a contact hole of a nand flash memory device according to the present embodiment is described in more detail with reference to fig. 4 to 8, and fig. 4 to 8 are schematic diagrams of the nand flash memory device shown in fig. 3.
Firstly, according to step S1, providing a substrate on which a gate 11 structure and an air gap 12 are formed, the substrate having a peripheral region and a storage region;
then, depositing a first interlayer dielectric layer 13 on the substrate, wherein the first interlayer dielectric layer 13 is thicker, and the purpose of the larger thickness is to provide more redundancy for the subsequent chemical mechanical polishing process so as to prevent the subsequent chemical mechanical polishing process from being incapable of leveling the whole upper surface of the first interlayer dielectric layer 13; the first interlayer dielectric layer 13 covers the substrate, that is, the first interlayer dielectric layer 13 covers the gate structure 11 and the air gap 12; the material of the first interlayer dielectric layer 13 may be silicon oxide; carrying out primary heat treatment on the substrate to remove impurities such as hydrogen and the like of the substrate;
then, carrying out chemical mechanical polishing on the first interlayer dielectric layer 13, polishing the upper surface of the first interlayer dielectric layer 13 flat, and polishing the upper surface of the first interlayer dielectric layer 13 to be horizontal, so that the filling of subsequent interlayer dielectrics can be kept horizontal, and further, in the final contact hole forming process, the same contact angle between the etching direction of the contact hole and the dielectric of each layer is ensured, the size of a contact hole process window is ensured, and the reliability of the device is improved;
then, depositing a subsequent interlayer dielectric layer on the substrate, wherein the subsequent interlayer dielectric layer comprises a second interlayer dielectric layer 14 and a third interlayer dielectric layer 15, the second interlayer dielectric layer 14 is silicon nitride, the third interlayer dielectric layer 15 is silicon oxide, and specifically, depositing a second interlayer dielectric layer 14 on the first interlayer dielectric layer 13 which has been ground flat, depositing a third interlayer dielectric layer 15 on the second interlayer dielectric layer 14, since the first interlayer dielectric layer 13 is ground flat, the second interlayer dielectric layer 14 and the third interlayer dielectric layer 15 can be kept horizontal, in the subsequent etching process, the boundary between the first interlayer dielectric layer 13 and the second interlayer dielectric layer 14 and the boundary between the second interlayer dielectric layer 14 and the third interlayer dielectric layer 15 are used as stop layers under different etching conditions;
finally, forming a contact hole 16 on the substrate, specifically comprising:
forming a patterned photoresist on the substrate, wherein the patterned photoresist exposes the position of the contact hole;
etching the substrate, specifically including: firstly, taking the boundary of the second interlayer dielectric layer 14 and the third interlayer dielectric layer 15 as a stop layer, and etching the third interlayer dielectric layer 15 downwards at the position of the contact hole 16 exposed on the substrate by the photoresist; then, taking the boundary of the second interlayer dielectric layer 14 and the first interlayer dielectric layer 13 as a stop layer, and continuously etching the second interlayer dielectric layer 14 downwards at the position of the contact hole 16; continuing etching until the etching of the contact hole 16 is completed; because the second interlayer dielectric layer 14 and the third interlayer dielectric layer 15 are kept horizontal, the etching direction of the contact hole 16 and the dielectric of each layer form the same contact angle, the size of a contact hole process window is ensured, and the reliability of the device is improved;
cleaning the etched substrate, wherein the cleaning of the etched by-product is mainly carried out to clean the photoresist;
depositing a bonding layer on the substrate, wherein the bonding layer is a thin layer and covers the upper surface of the third interlayer dielectric 15 and the inner surface of the contact hole 16, the bonding layer can be made of titanium nitride, and the bonding layer is beneficial to the adhesion of a subsequent tungsten layer on an oxide layer (namely the third interlayer dielectric layer);
depositing metal tungsten on the substrate, wherein the metal tungsten fills the contact hole 16, and due to the existence of the bonding layer, the metal tungsten can be better attached to the oxide layer (namely, the third interlayer dielectric layer).
In summary, the method for manufacturing a contact hole of a nand flash memory device according to the present invention includes: forming a gate structure and an air gap on a substrate; depositing a first interlayer dielectric layer on the substrate; carrying out chemical mechanical polishing on the first interlayer dielectric layer, and polishing the upper surface of the first interlayer dielectric layer to be flat; depositing a subsequent interlayer dielectric layer on the substrate; forming a contact hole on the substrate. The manufacturing method of the contact hole of the NAND flash memory device enables the first interlayer dielectric layer to be kept horizontal and further enables the subsequent interlayer dielectric layers to be kept horizontal, thereby ensuring that the etching direction of the contact hole and the interlayer dielectric layers of different layers form the same contact angle in the contact hole forming process, further ensuring the size of a contact hole process window and improving the reliability of the device.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (7)
1. A method for fabricating a contact hole of a NAND type flash memory device, comprising:
s1, forming a gate structure and an air gap on a substrate;
s2, depositing a first interlayer dielectric layer on the substrate;
s3, carrying out chemical mechanical polishing on the first interlayer dielectric layer, and polishing the upper surface of the first interlayer dielectric layer to be flat;
s4, depositing a subsequent interlayer dielectric layer on the substrate;
and S5, forming a contact hole on the substrate.
2. The method of manufacturing a contact hole of a nand-type flash memory device as claimed in claim 1, wherein the step of forming a contact hole on the substrate comprises:
forming a patterned photoresist on the substrate, wherein the patterned photoresist exposes the position of the contact hole;
etching the substrate and cleaning;
depositing a bonding layer on the substrate, and depositing metal tungsten on the substrate.
3. The method for fabricating a contact hole between a nand-type flash memory device as claimed in claim 2, wherein the subsequent interlayer dielectric layer comprises a second interlayer dielectric layer and a third interlayer dielectric layer, the second interlayer dielectric layer is silicon nitride, and the third interlayer dielectric layer is silicon oxide.
4. The method of manufacturing a contact hole of a nand-type flash memory device as claimed in claim 3, wherein in the etching process, a boundary between the first interlayer dielectric layer and the second interlayer dielectric layer and a boundary between the second interlayer dielectric layer and the third interlayer dielectric layer are used as stop layers for different etching conditions.
5. The method of manufacturing a contact hole of a nand-type flash memory device according to claim 2, wherein the adhesive layer is titanium nitride.
6. The method of manufacturing a contact hole of a nand-type flash memory device as claimed in claim 1, wherein the first interlayer dielectric layer is silicon oxide.
7. The method for fabricating a contact hole of a nand-type flash memory device as claimed in claim 1, wherein the S2 further comprises heat-treating the substrate.
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| CN202110593161.6A CN113327889B (en) | 2021-05-28 | 2021-05-28 | Method for manufacturing contact hole of NAND flash memory device |
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| CN202110593161.6A CN113327889B (en) | 2021-05-28 | 2021-05-28 | Method for manufacturing contact hole of NAND flash memory device |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020075067A (en) * | 2001-03-23 | 2002-10-04 | 삼성전자 주식회사 | Method for forming a contact and bit line of flash memory device |
| CN101577244A (en) * | 2008-05-05 | 2009-11-11 | 中芯国际集成电路制造(北京)有限公司 | Flattening method of interlayer medium layer and forming method of contact hole |
| CN102054758A (en) * | 2009-11-10 | 2011-05-11 | 中芯国际集成电路制造(上海)有限公司 | Method for forming tungsten plug |
| US20180005886A1 (en) * | 2016-07-04 | 2018-01-04 | Semiconductor Manufacturing International (Shanghai) Corporation | Contact structure and associated method for flash memory |
| CN107731831A (en) * | 2017-08-24 | 2018-02-23 | 长江存储科技有限责任公司 | A kind of process for improving contact hole plug oxide depression |
| CN110634801A (en) * | 2019-10-18 | 2019-12-31 | 中国科学院微电子研究所 | Contact hole preparation method |
| TW202002170A (en) * | 2018-04-03 | 2020-01-01 | 日商東京威力科創股份有限公司 | Subtractive interconnect formation using a fully self-aligned scheme |
-
2021
- 2021-05-28 CN CN202110593161.6A patent/CN113327889B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020075067A (en) * | 2001-03-23 | 2002-10-04 | 삼성전자 주식회사 | Method for forming a contact and bit line of flash memory device |
| CN101577244A (en) * | 2008-05-05 | 2009-11-11 | 中芯国际集成电路制造(北京)有限公司 | Flattening method of interlayer medium layer and forming method of contact hole |
| CN102054758A (en) * | 2009-11-10 | 2011-05-11 | 中芯国际集成电路制造(上海)有限公司 | Method for forming tungsten plug |
| US20180005886A1 (en) * | 2016-07-04 | 2018-01-04 | Semiconductor Manufacturing International (Shanghai) Corporation | Contact structure and associated method for flash memory |
| CN107731831A (en) * | 2017-08-24 | 2018-02-23 | 长江存储科技有限责任公司 | A kind of process for improving contact hole plug oxide depression |
| TW202002170A (en) * | 2018-04-03 | 2020-01-01 | 日商東京威力科創股份有限公司 | Subtractive interconnect formation using a fully self-aligned scheme |
| CN110634801A (en) * | 2019-10-18 | 2019-12-31 | 中国科学院微电子研究所 | Contact hole preparation method |
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