CN114334989A - Manufacturing process of Nord flash memory device - Google Patents

Abstract

The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a manufacturing process of a Nord flash memory device. The process comprises the following steps: manufacturing a polysilicon floating gate layer, a polysilicon intermediate medium layer and a polysilicon control gate layer which are sequentially stacked from bottom to top on a substrate; etching the polysilicon control gate layer to form a first window in the polysilicon control gate layer; depositing a floating gate silicon nitride layer according to the surface appearance of the polysilicon control gate layer with the first window; etching the floating gate silicon nitride layer to enable the floating gate silicon nitride layer to be provided with a second window; depositing an oxide layer according to the surface appearance of the floating gate silicon nitride layer with the second window; etching the oxide layer; removing the inter-polysilicon dielectric layer at the position of the first window, and the oxide and the silicon nitride at the position of the side wall of the first window by using a pickling solution, so that the side surface of the polysilicon control gate layer and the upper surface of the polysilicon floating gate layer at the position of the first window are exposed; and manufacturing a word line structure of the Nord flash memory device.

Description

Manufacturing process of Nord flash memory device

Technical Field

The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a manufacturing process of a Nord flash memory device.

Background

Nord flash memory devices have become increasingly important in the field of non-volatile memories due to their performance advantages, such as low cost, low power consumption, and fast access speed. With the development of technology, data storage media applications are also exclusively applied to flash memory type memories from some traditional non-volatile memories, and mass solid-state storage devices with flash memories as main storage media have become one of the mainstream schemes for data storage today.

In general, a Nord flash memory device includes a floating gate and a control gate stacked together with a composite dielectric layer formed therebetween. Control of a read operation, a write operation, and an erase operation of the Nord flash memory device is achieved by applying different operation voltages to a control gate of the Nord flash memory device. The storage content of the Nord flash memory device depends on the state of electrons stored in the floating gate in the storage structure, if the floating gate is in a state without electrons, the data in the Nord flash memory device is 1, and if the floating gate is in a state with electrons, the data in the Nord flash memory device is 0.

In the related art, when a floating gate silicon nitride layer on a control gate layer is etched, over-etching is usually performed, so that an etching stop surface is located in the control gate layer, but the over-etching easily causes the appearance of the etching stop surface to be non-uniform, so that the thicknesses of the rest control gate layers are inconsistent, the storage of electrons in the floating gate is influenced, the current of data 0 and the current window of data 1 are insufficient, and the adverse influence is caused on the reliability of data reading and writing of the Nord flash memory device.

Disclosure of Invention

The application provides a manufacturing process of a Nord flash memory device, which can solve the problem that the current of data 0 and the current window of data 1 are insufficient in the related technology, and the reliability of reading and writing data of the Nord flash memory device is adversely affected.

In order to solve the technical problems described in the background, the present application provides a manufacturing process of a Nord flash memory device, including the following steps:

the first step is as follows: manufacturing a polysilicon floating gate layer, a polysilicon intermediate medium layer and a polysilicon control gate layer which are sequentially stacked from bottom to top on a substrate;

the second step is that: etching the polysilicon control gate layer to form a first window in the polysilicon control gate layer;

the third step: depositing a floating gate silicon nitride layer according to the surface appearance of the polysilicon control gate layer with the first window;

the fourth step: etching the floating gate silicon nitride layer to open a second window in the floating gate silicon nitride layer;

the fifth step: depositing an oxide layer according to the surface topography of the floating gate silicon nitride layer with the second window;

and a sixth step: etching the oxide layer;

the seventh step: removing the inter-polysilicon dielectric layer at the position of the first window, and the oxide and the silicon nitride at the position of the side wall of the first window by using a pickling solution, so that the side surface of the polysilicon control gate layer and the upper surface of the polysilicon floating gate layer at the position of the first window are exposed;

eighth step: and manufacturing a word line structure of the Nord flash memory device.

Optionally, the second step: etching the polysilicon control gate layer to form a first window in the polysilicon control gate layer,

and the upper surface of the interpoly dielectric layer at the position of the first window is exposed.

Optionally, the third step: in the step of depositing the floating gate silicon nitride layer according to the surface topography of the polysilicon control gate layer with the first window,

and the floating gate silicon nitride layer covers the surface of the rest polysilicon control gate layer and the upper surface of the interpoly dielectric layer exposed from the first window position.

Optionally, the fourth step: etching the floating gate silicon nitride layer to form a second window in the floating gate silicon nitride layer,

the first window and the polysilicon control gate layers positioned at two sides of the first window are positioned in the second window, and the polysilicon control gate layers at two sides of the first window and the upper surface of the inter-polysilicon dielectric layer positioned in the first window are exposed out of the second window.

Optionally, the fifth step: and in the step of depositing the oxide layer according to the surface topography of the floating gate silicon nitride layer with the second window, the oxide layer covers the surface of the rest floating gate silicon nitride layer, the surface of the polysilicon control gate layer exposed from the position of the second window and the upper surface of the interpoly dielectric layer.

Optionally, the sixth step: and in the step of etching the oxide layer, the oxide layer on the side wall of the second window is remained.

Optionally, the seventh step: removing the inter-polysilicon dielectric layer at the position of the first window, and the oxide and the silicon nitride at the position of the side wall of the first window by using a pickling solution, so that the side surface of the polysilicon control gate layer and the upper surface of the polysilicon floating gate layer at the position of the first window are exposed, and the method comprises the following steps of:

and removing the inter-polysilicon dielectric layer at the position of the first window, and the oxide and the silicon nitride at the position of the side wall of the first window by hydrofluoric acid and phosphoric acid, so that the side surface of the polysilicon control gate layer and the upper surface of the polysilicon floating gate layer at the position of the first window are exposed.

Optionally, at the seventh step: removing the inter-polysilicon dielectric layer at the position of the first window, and the oxide and the silicon nitride at the position of the side wall of the first window by using a pickling solution, so that after the steps of exposing the side surface of the polysilicon control gate layer and the upper surface of the polysilicon floating gate layer at the position of the first window are completed,

and a second window with the first side wall structure formed on the side wall and a third window formed by the first window without the medium layer between the crystalline silicon.

Optionally, the eighth step: the word line structure for manufacturing the Nord flash memory device comprises the following steps:

forming a second side wall structure on the side wall of the third window;

etching to remove the polysilicon floating gate layer which is positioned at the third window and is not covered with the second side wall structure, so that the third window extends downwards to form a fourth window;

forming a third side wall structure on the side surface of the polysilicon floating gate layer exposed from the fourth window;

etching and removing the gate oxide layer which is positioned at the fourth window and is not covered with the third side wall structure, so that the etching stop layer is positioned in the gate oxide layer, and the fourth window extends downwards to form a first word line filling window;

and filling the word line filling window with word line polysilicon.

The technical scheme at least comprises the following advantages: the polysilicon control gate layer is etched to form a first window in the polysilicon control gate layer, then depositing a floating gate silicon nitride layer according to the surface appearance of the polysilicon control gate layer with the first window, etching the floating gate silicon nitride layer, forming a second window in the floating gate silicon nitride layer, depositing an oxide layer according to the surface appearance of the floating gate silicon nitride layer with the second window, etching the oxide layer, removing the inter-polysilicon dielectric layer at the position of the first window by using a pickling solution, and oxide and silicon nitride on the side wall of the first window to expose the side surface of the polysilicon control gate layer and the upper surface of the polysilicon floating gate layer on the first window, therefore, the thickness of the polysilicon control gate layer is uniform, and the related problems caused by non-uniformity of the polysilicon control gate layer due to over-etching are avoided.

Drawings

In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a flow chart illustrating a process for fabricating a Nord flash memory device according to an embodiment of the present disclosure;

FIG. 2 is a schematic cross-sectional view of the device after step S2 is completed;

FIG. 3 is a schematic cross-sectional view of the device after step S4 is completed;

FIG. 4 is a schematic cross-sectional view of the device after step S7 is completed;

FIG. 5 is a schematic cross-sectional view of the device after step S81 is completed;

fig. 6 shows a schematic cross-sectional structural view of the device after completion of step S82;

fig. 7 shows a schematic cross-sectional structural diagram of the device after step S85 is completed.

Detailed Description

The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.

Fig. 1 is a flowchart illustrating a process for manufacturing a Nord flash memory device according to an embodiment of the present application, and as can be seen from fig. 1, the process for manufacturing the Nord flash memory device includes the following steps:

step S1: and manufacturing a polysilicon floating gate layer, a polysilicon intermediate medium layer and a polysilicon control gate layer which are sequentially stacked from bottom to top on the substrate.

Illustratively, the substrate may be a silicon substrate. The inter-polysilicon dielectric layer can be a multilayer structure, and when the inter-polysilicon dielectric layer is a multilayer structure, the inter-polysilicon dielectric layer comprises a silicon oxide layer, a silicon nitride layer and a silicon oxide layer which are sequentially stacked from bottom to top.

A gate oxide layer can also be formed between the substrate and the polysilicon floating gate layer.

Step S2: and etching the polysilicon control gate layer to form a first window in the polysilicon control gate layer.

Referring to fig. 2, which shows a schematic cross-sectional structure of the device after step S2 is completed, it can be seen from fig. 2 that the substrate 110 includes a gate oxide layer 101, a floating polysilicon gate layer 120, an inter-polysilicon dielectric layer 130, and a polysilicon control gate layer 140, which are stacked in sequence. A first window 150 is formed in the polysilicon control gate layer 140, and the upper surface of the interpoly dielectric layer 130 at the position of the first window 150 is exposed.

Step S3: and depositing a floating gate silicon nitride layer according to the surface appearance of the polysilicon control gate layer with the first window.

The deposited floating gate silicon nitride layer overlies the surface of the remaining polysilicon control gate layer 140 and the upper surface of the exposed interpoly dielectric layer 130 at the location of the first window 150 as shown in fig. 2. The surface of the remaining polysilicon control gate layer 140 covered by the floating gate silicon nitride layer includes the upper surface of the remaining polysilicon control gate layer 140 shown in fig. 2, and the side surface of the remaining polysilicon control gate layer 140 located at the position of the first window 150.

Step S4: and etching the floating gate silicon nitride layer to open a second window in the floating gate silicon nitride layer.

Referring to fig. 3, which shows a schematic cross-sectional structure of the device after step S4 is completed, it can be seen from fig. 3 that a second window 170 is opened in the floating gate silicon nitride layer 160, and the formed second window 170 is communicated with the first window 150.

The first window 150 and the polysilicon control gate layer 140 located at both sides of the first window 150 are located in the second window 170. The polysilicon control gate layer 140 on both sides of the first window 150 and the upper surface of the interpoly dielectric layer 130 in the first window 150 are exposed from the second window 170.

Due to the etching directionality, there will be nitride residues (not shown in fig. 3) such as floating gate silicon nitride layer on the side surface of the remaining polysilicon control gate layer 140 at the location of the first window 150 after the completion of step S4.

Step S5: and depositing an oxide layer according to the surface topography of the floating gate silicon nitride layer with the second window.

The oxide layer deposited by step S5 covers the upper surface of the remaining floating gate silicon nitride layer 160 and the surface of the second window 170, wherein the surface of the second window 170 includes the side surface of the floating gate silicon nitride layer 160 exposed from the second window 170, the side surface of the polysilicon control gate layer 140 exposed from the first window 150, and the upper surface of the interpoly dielectric layer 130 exposed from the first window 150.

Step S6: and etching the oxide layer.

Due to the directionality of the etching, the etching rate of the oxide layer covering the upper surface is greater than the etching rate of the oxide layer covering the side surface in performing step S6. Thus, after step S6 is completed, the oxide layer covering the upper surface of the remaining floating gate silicon nitride layer 160 and the oxide layer covering the upper surface of the interpoly dielectric layer 130 exposed from the first window 150 are completely removed by etching, and the oxide layer covering the side surface of the floating gate silicon nitride layer 160 and the oxide layer covering the side surface of the polysilicon control gate layer 140 remain.

Step S7: and removing the inter-polysilicon dielectric layer at the position of the first window, and the oxide and the silicon nitride at the position of the side wall of the first window by using a pickling solution, so that the side surface of the polysilicon control gate layer and the upper surface of the polysilicon floating gate layer at the position of the first window are exposed.

The nitride and oxide layers are left on the side surfaces of the polysilicon control gate layer 140 (i.e., at the position of the sidewalls of the first window) after the steps S4 and S6 are completed. And removing the oxide and the silicon nitride of the polysilicon control gate layer at the position of the side wall of the first window by using an acid washing solution, so that the side surface of the polysilicon control gate layer is exposed.

Optionally, the inter-polysilicon dielectric layer at the position of the first window, and the oxide and the silicon nitride at the position of the side wall of the first window can be removed by hydrofluoric acid and phosphoric acid removal pickling solution, so that the side surface of the polysilicon control gate layer and the upper surface of the polysilicon floating gate layer at the position of the first window are exposed.

Referring to fig. 4, which shows a schematic cross-sectional structure of the device after step S7 is completed, it can be seen from fig. 4 that only the oxide layer covering the side surface of the floating gate silicon nitride layer 160 is left to form the first sidewall structure 180 after step S7 is completed. The first sidewall structure 180 also covers the polysilicon control gate layer 140 on both sides of the first window 150.

With continued reference to fig. 4, after step S7 is completed, the second window 170 with the first sidewall structure 180 formed on the sidewall and the first window 150 with the inter-silicon dielectric layer 130 removed form a third window 190.

Step S8: and manufacturing a word line structure of the Nord flash memory device.

Step S8 may be implemented by an embodiment comprising:

step S81: and forming a second side wall structure on the side wall of the third window formed after the step S7 is completed.

Referring to fig. 5, which shows a schematic cross-sectional structure of the device after step S81 is completed, it can be seen from fig. 5 that, after step S81 is completed, the side wall of the third window 190 is covered with a second side wall structure 200, and the second side wall structure 200

Step S82: and etching to remove the polysilicon floating gate layer which is positioned at the third window and is not covered with the second side wall structure, so that the third window extends downwards to form a fourth window.

Referring to fig. 6, which shows a schematic cross-sectional structural view of the device after step S82 is completed, it can be seen from fig. 6 that, at the position of the third window 190 shown in fig. 4, the floating gate polysilicon layer 120 not covered with the second sidewall structure 200 is etched away, so that the third window 190 shown in fig. 4 extends downward to form a fourth window 210 shown in fig. 5, and the gate oxide layer 101 at the position of the fourth window 210 is exposed.

Step S83 is executed to form a third sidewall structure on the exposed side surface of the polysilicon floating gate layer in the fourth window.

As can be seen from fig. 6, after step S83 is completed, the side surface of the polysilicon floating gate layer 120 is exposed in the fourth window 210, and the third sidewall structure covers the side surface of the polysilicon floating gate layer exposed in the fourth window and covers the upper surfaces of both ends of the gate oxide layer 101 exposed in the fourth window 210.

Step S84: and etching to remove the gate oxide layer which is positioned at the fourth window and is not covered with the third side wall structure, so that the etching stop layer is positioned in the gate oxide layer, and the fourth window extends downwards to form a first word line filling window.

Step S85: and filling the word line filling window with word line polysilicon.

Referring to fig. 7, which shows a schematic cross-sectional structure of the device after step S85 is completed, it can be seen from fig. 7 that the etch stop layer 220 after step S84 is located in the gate oxide layer 101, and the word line filling window is filled with the word line polysilicon 230.

In the embodiment, the polysilicon control gate layer is etched first, so that a first window is formed in the polysilicon control gate layer, then depositing a floating gate silicon nitride layer according to the surface appearance of the polysilicon control gate layer with the first window, etching the floating gate silicon nitride layer, forming a second window in the floating gate silicon nitride layer, depositing an oxide layer according to the surface appearance of the floating gate silicon nitride layer with the second window, etching the oxide layer, removing the inter-polysilicon dielectric layer at the position of the first window by using a pickling solution, and oxide and silicon nitride on the side wall of the first window to expose the side surface of the polysilicon control gate layer and the upper surface of the polysilicon floating gate layer on the first window, therefore, the thickness of the polysilicon control gate layer is uniform, and the related problems caused by non-uniformity of the polysilicon control gate layer due to over-etching are avoided.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims (9)

1. A manufacturing process of a Nord flash memory device is characterized by comprising the following steps:

the first step is as follows: manufacturing a polysilicon floating gate layer, a polysilicon intermediate medium layer and a polysilicon control gate layer which are sequentially stacked from bottom to top on a substrate;

the second step is that: etching the polysilicon control gate layer to form a first window in the polysilicon control gate layer;

the third step: depositing a floating gate silicon nitride layer according to the surface appearance of the polysilicon control gate layer with the first window;

the fourth step: etching the floating gate silicon nitride layer to open a second window in the floating gate silicon nitride layer;

the fifth step: depositing an oxide layer according to the surface topography of the floating gate silicon nitride layer with the second window;

and a sixth step: etching the oxide layer;

the seventh step: removing the inter-polysilicon dielectric layer at the position of the first window, and the oxide and the silicon nitride at the position of the side wall of the first window by using a pickling solution, so that the side surface of the polysilicon control gate layer and the upper surface of the polysilicon floating gate layer at the position of the first window are exposed;

eighth step: and manufacturing a word line structure of the Nord flash memory device.

2. The process for fabricating a Nord flash memory device according to claim 1, wherein the second step: etching the polysilicon control gate layer to form a first window in the polysilicon control gate layer,

and the upper surface of the interpoly dielectric layer at the position of the first window is exposed.

3. The process for fabricating a Nord flash memory device according to claim 1, wherein the third step: in the step of depositing the floating gate silicon nitride layer according to the surface topography of the polysilicon control gate layer with the first window,

and the floating gate silicon nitride layer covers the surface of the rest polysilicon control gate layer and the upper surface of the interpoly dielectric layer exposed from the first window position.

4. The process for fabricating a Nord flash memory device according to claim 1, wherein the fourth step: etching the floating gate silicon nitride layer to form a second window in the floating gate silicon nitride layer,

the first window and the polysilicon control gate layers positioned at two sides of the first window are positioned in the second window, and the polysilicon control gate layers at two sides of the first window and the upper surface of the inter-polysilicon dielectric layer positioned in the first window are exposed out of the second window.

5. The process for fabricating a Nord flash memory device according to claim 1, wherein the fifth step: and in the step of depositing the oxide layer according to the surface topography of the floating gate silicon nitride layer with the second window, the oxide layer covers the surface of the rest floating gate silicon nitride layer, the surface of the polysilicon control gate layer exposed from the position of the second window and the upper surface of the interpoly dielectric layer.

6. The process for fabricating a Nord flash memory device according to claim 1, wherein the sixth step: and in the step of etching the oxide layer, the oxide layer on the side wall of the second window is remained.

7. The process for fabricating a Nord flash memory device according to claim 1, wherein the seventh step: removing the inter-polysilicon dielectric layer at the position of the first window, and the oxide and the silicon nitride at the position of the side wall of the first window by using a pickling solution, so that the side surface of the polysilicon control gate layer and the upper surface of the polysilicon floating gate layer at the position of the first window are exposed, and the method comprises the following steps of:

and removing the inter-polysilicon dielectric layer at the position of the first window, and the oxide and the silicon nitride at the position of the side wall of the first window by hydrofluoric acid and phosphoric acid, so that the side surface of the polysilicon control gate layer and the upper surface of the polysilicon floating gate layer at the position of the first window are exposed.

8. The process for fabricating a Nord flash memory device according to claim 1, wherein in the seventh step: removing the inter-polysilicon dielectric layer at the position of the first window, and the oxide and the silicon nitride at the position of the side wall of the first window by using a pickling solution, so that after the steps of exposing the side surface of the polysilicon control gate layer and the upper surface of the polysilicon floating gate layer at the position of the first window are completed,

and a second window with the first side wall structure formed on the side wall and a third window formed by the first window without the medium layer between the crystalline silicon.

9. The process for fabricating a Nord flash memory device according to claim 8, wherein the eighth step: the word line structure for manufacturing the Nord flash memory device comprises the following steps:

forming a second side wall structure on the side wall of the third window;

etching to remove the polysilicon floating gate layer which is positioned at the third window and is not covered with the second side wall structure, so that the third window extends downwards to form a fourth window;

forming a third side wall structure on the side surface of the polysilicon floating gate layer exposed from the fourth window;

etching and removing the gate oxide layer which is positioned at the fourth window and is not covered with the third side wall structure, so that the etching stop layer is positioned in the gate oxide layer, and the fourth window extends downwards to form a first word line filling window;

and filling the word line filling window with word line polysilicon.

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